CN109302173A - Input buffer - Google Patents

Abstract

This application discloses a kind of input buffer, including: the first buffer cell, the second buffer cell and control unit, the input port of the first buffer cell are connected with the input port of the second buffer cell；First buffer cell is used to receive the input signal of input buffer, generates reversed the first level signal and second electrical level signal, first output signal of the second electrical level signal as input buffer；Second buffer cell is used to receive the input signal and the first level signal, second electrical level signal of input buffer, generates the second output signal of input buffer；The control unit being connected with the second buffer cell, control unit are used to control the working condition of the second buffer cell for receiving reversed the first enable signal and the second enable signal, the first enable signal and the second enable signal.The application realizes the input buffer that an input pin exports four kinds of logic states, and the power consumption of the input buffer is reduced by control unit.

Description

Input buffer

Technical field

The present invention relates to electronic circuit technology field more particularly to a kind of input buffers.

Background technique

Input buffer is indispensable basic module in integrated circuit, its effect is that the data of sending peripheral hardware are temporary Shi Cunfang, so that processor takes it away.Currently, input buffer be widely used in audio-frequency power amplifier, converter, radio frequency, In sensor and power management chip.Input buffer common in the art is Schmidt's input buffer, and Schmidt is defeated An input pin for entering buffer can export two kinds of logic states: when incoming level is higher than threshold voltage, output logic electricity It is flat to become high from low；When incoming level is lower than threshold voltage, exporting logic level from height becomes low.

And as IC complexity increases, required input pin sharply increases.Such as: audio frequency power amplifier needs are set A variety of different I2C register address are set, to realize the application scenarios of multichannel, it is multiple that this just needs input buffer that can export Logic state.Since an input pin of Schmidt's input buffer in the prior art is only capable of two kinds of logic states of output, Realize the output of more logic states, it is necessary to multiple input pins, and under normal conditions, the pin resource in integrated circuit is non- It is often nervous, excessive pin can not be distributed as input pin.

Summary of the invention

Based on above-mentioned the deficiencies in the prior art, the invention proposes a kind of input buffers, to realize single input pin Four kinds of logic states, and the input buffer of low-power consumption can be exported.

To solve the above problems, the scheme now proposed is as follows:

The invention discloses a kind of input buffers, comprising:

First buffer cell, the second buffer cell and control unit, the input port of first buffer cell and institute The input port for stating the second buffer cell is connected, input pin of the tie point as the input buffer；Described control unit It is connected with second buffer cell；

First buffer cell is used to receive the input signal of the input buffer, generates reversed the first level letter Number and second electrical level signal, first output signal of the second electrical level signal as the input buffer；

Second buffer cell is used to receive the input signal, first level signal and institute of the input buffer Second electrical level signal is stated, the second output signal of the input buffer is generated；

Described control unit is enabled according to described first for receiving reversed the first enable signal and the second enable signal The high level or low level state of signal and second enable signal control the working condition of second buffer cell.

Optionally, in above-mentioned input buffer, second buffer cell, comprising: pull down resistor comparing unit, pull-up Resistance comparing unit, phase inverter and logic unit；Wherein:

The pull down resistor comparing unit is used to receive the input signal of the input buffer, generates third level letter Number；

The pull-up resistor comparing unit is connected with the input port of the pull down resistor comparing unit；For receiving The input signal of input buffer is stated, the 4th level signal is generated, the 4th level signal obtains the 5th electricity by phase inverter Ordinary mail number；

The logic unit is for receiving first level signal, the second electrical level signal, third level letter Number, the 4th level signal and the 5th level signal, and believed according to first level signal, the second electrical level Number, the third level signal, the 4th level signal and the 5th level signal, generate the of the input buffer Two output signals.

Optionally, in above-mentioned input buffer, described control unit, comprising:

First control subelement and the second control subelement；Wherein:

The first control subelement is for receiving first enable signal and second enable signal, according to described in The high level or low level state of first enable signal and second enable signal control the pull down resistor comparing unit Working condition；

The second control subelement is for receiving first enable signal and second enable signal, according to described in The high level or low level state of first enable signal and second enable signal control the pull-up resistor comparing unit Working condition.

Optionally, in above-mentioned input buffer, the pull down resistor comparing unit, comprising:

First end is respectively connected to the first switch tube and second switch of power supply, the control terminal of the first switch tube and institute The control terminal for stating second switch is connected；

Third switching tube of the first end as the input pin of the input buffer, the second end of the third switching tube It is connected with the second end of the first switch tube；

The 4th switching tube that first end is grounded by first resistor, the second end of the 4th switching tube are opened with described second The second end for closing pipe is connected；

The second end of the 5th switching tube that first end is grounded by second resistance, the 5th switching tube is connect by constant-current source Enter power supply；The control terminal of the control terminal of the third switching tube, the control terminal of the 4th switching tube and the 5th switching tube It is connected；

Output end accesses the first voltage comparator of logic unit, the non-inverting input terminal connection of the first voltage comparator The common end of the second end of the second end of the first switch tube and the third switching tube, the first voltage comparator it is anti- Phase input terminal connects the common end of the second end of the second switch and the second end of the 4th switching tube.

Optionally, in above-mentioned input buffer, the first control subelement, comprising:

First end accesses the 17th switching tube of power supply, and the second end of the 17th switching tube connects the first switch The common end of the control terminal of the control terminal of pipe and the second switch, the control terminal of the 17th switching tube receive described the One enable signal；

The eighteenmo of first end ground connection closes pipe, and the second end that the eighteenmo closes pipe connects the third switching tube The common end of control terminal and the control terminal of the 4th switching tube, the control terminal that the eighteenmo closes pipe, which receives described second, to be made It can signal.

Optionally, in above-mentioned input buffer, the pull-up resistor comparing unit, comprising:

Sixth switching tube of the first end as the input pin of the input buffer；

First end accesses the 7th switching tube of power supply by 3rd resistor；

First end accesses the 8th switching tube of power supply by the 4th resistance, and the second end of the 8th switching tube passes through electric current Source ground connection；

Control terminal, the control terminal of the 7th switching tube and the control terminal of the 8th switching tube of 6th switching tube It is connected；

9th switching tube of first end ground connection, the second end of the 9th switching tube connect the second of the 6th switching tube End；

Tenth switching tube of first end ground connection, the second end of the tenth switching tube connect the second of the 7th switching tube End；

The control terminal of 9th switching tube is connected with the control terminal of the tenth switching tube；

Output end accesses the second voltage comparator of the logic unit by the phase inverter, and the second voltage compares The non-inverting input terminal of device connects the common end of the second end of the 6th switching tube and the second end of the 9th switching tube, described The inverting input terminal of second voltage comparator connects the second end of the 7th switching tube and the second end of the tenth switching tube Common end.

Optionally, in above-mentioned input buffer, the second control subelement, comprising:

First end accesses the 19th switching tube of power supply, the second end connection of the 19th switching tube the 6th switch The common end of the control terminal of the control terminal of pipe and the 7th switching tube, the control terminal of the 19th switching tube receive described the One enable signal；

20th switching tube of first end ground connection, the second end of the 20th switching tube connect the 9th switching tube The common end of control terminal and the control terminal of the tenth switching tube, the control terminal of the 20th switching tube, which receives described second, to be made It can signal.

Optionally, in above-mentioned input buffer, the logic unit, comprising:

First NAND gate, the input terminal of first NAND gate access the second electrical level signal, third level letter Number and the 4th level signal, the output end of first NAND gate export the 6th level signal；

Second NAND gate, the input terminal of second NAND gate access first level signal, third level letter Number and the 5th level signal, the output end of second NAND gate export the 7th level signal；

Third NAND gate, the input terminal of the third NAND gate input the 6th level signal and the 7th level letter Number, the third NAND gate output end exports the second output signal of the input buffer.

Optionally, in above-mentioned input buffer, first buffer cell includes:

First end accesses the 11st switching tube of power supply, second end and the 12nd switching tube of the 11st switching tube First end is connected；

The 12nd switching tube that first end is connected with the second end of the 11st switching tube, the 12nd switch The second end of pipe is connected with the second end of the 14th switching tube；

First end connects the common end of the second end of the 11st switching tube and the first end of the 12nd switching tube The 13rd switching tube, the 13rd switching tube second end ground connection, the 13rd switching tube control terminal connection described in The common end of the second end of 12nd switching tube and the second end of the 14th switching tube；

The 14th switching tube that first end is connected with the second end of the 15th switching tube, the 14th switching tube Second end is connected with the second end of the 12nd switching tube；

The second end of 15th switching tube of first end ground connection, the 15th switching tube connects the 14th switching tube First end, the 11st switching tube, the 12nd switching tube, the 14th switching tube and the 15th switching tube Control terminal be connected and the input pin as the input buffer；

First end connects the common end of the first end of the 14th switching tube and the second end of the 15th switching tube Sixteenmo close pipe, the sixteenmo closes the second termination power of pipe, and the control terminal that the sixteenmo closes pipe connects institute State the control terminal of the 13rd switching tube；

Input terminal connects the common end of the control terminal of the 13rd switching tube and the control terminal of sixteenmo pass pipe The first phase inverter；

The second phase inverter that input terminal is connected with the output end of first phase inverter, described in second phase inverter output First level signal；

The third phase inverter that input terminal is connected with the output end of second phase inverter, described in third phase inverter output Second electrical level signal.

Optionally, in above-mentioned input buffer, further includes:

The data input pin of the first d type flip flop being connected with first buffer cell, first d type flip flop receives institute State first output signal, the clock input postpones signal of first d type flip flop, the of first d type flip flop One output end is used to deposit the logic state of first output signal；

The data input pin of the second d type flip flop being connected with second buffer cell, second d type flip flop receives institute State second output signal, the clock input postpones signal of second d type flip flop, the of second d type flip flop One output end is used to deposit the logic state of the second output signal.

It can be seen from the above technical scheme that input buffer provided by the invention passes through the first buffer cell output the One output signal exports second output signal by the second buffer cell, also, the input signal of two buffer cells is equal It is inputted by the same input pin of input buffer, i.e., single input pin can export four kinds of logic states, save collection At the pin resource in circuit.

In addition, the working condition of the second buffer cell is controlled by control unit, so that the input buffer is not defeated When entering signal, the second buffer cell is not at working condition, and inside does not have quiescent current, reduces the power consumption of input buffer.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis The attached drawing of offer obtains other attached drawings.

Fig. 1 is the circuit diagram of existing Schmidt's input buffer；

Fig. 2 is a kind of structure chart of input buffer disclosed by the embodiments of the present invention；

Fig. 3 is the circuit diagram of the first buffer cell in another input buffer disclosed by the embodiments of the present invention；

Fig. 4 is the structure chart of the second buffer cell in another input buffer disclosed by the embodiments of the present invention；

Fig. 5 is the circuit diagram of the pull down resistor comparing unit in another input buffer disclosed by the embodiments of the present invention；

Fig. 6 is the circuit diagram of the pull-up resistor comparing unit in another input buffer disclosed by the embodiments of the present invention；

Fig. 7 is the circuit diagram of the logic unit in another input buffer disclosed by the embodiments of the present invention；

Fig. 8 is the structure chart of the control unit in another input buffer disclosed by the embodiments of the present invention；

Fig. 9 is the circuit diagram of the first control subelement in another input buffer disclosed by the embodiments of the present invention；

Figure 10 is the circuit diagram of the second control subelement in another input buffer disclosed by the embodiments of the present invention；

Figure 11 is power supply signal disclosed in another embodiment of the present invention, power-on reset signal, postpones signal, the first enabled letter Number and the second enable signal relational graph；

Figure 12 is the circuit diagram of another input buffer disclosed by the embodiments of the present invention.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

Currently, existing Schmidt's input buffer, as shown in Figure 1, an input pin of Schmidt's input buffer Two kinds of logic states can be exported: when incoming level is higher than threshold voltage, output logic level becomes high from low；Work as incoming level When lower than threshold voltage, exporting logic level from height becomes low.

Since an input pin of Schmidt's input buffer in the prior art is only capable of two kinds of logic states of output, Realize the output of more logic states, it is necessary to multiple input pins, and under normal conditions, the pin resource in integrated circuit is very Anxiety can not distribute excessive pin as input pin.

In view of the above-mentioned problems, the embodiment of the present application proposes a kind of input buffer, to realize single input pin energy Export the function of four kinds of logic states.

The embodiment of the present application discloses a kind of input buffer, referring to fig. 2, comprising:

First buffer cell 201, the second buffer cell 202 and control unit 203, the input terminal of the first buffer cell 201 Mouth is connected with the input port of the second buffer cell 202, as the input pin of input buffer, control unit 203 and second Buffer cell 202 is connected.

First buffer cell 201 is used to receive the input signal of input buffer, generate reversed the first level signal and Second electrical level signal, first output signal OUT<1>of the second electrical level signal as input buffer；

Wherein, the first opposite level signal and second electrical level signal refer to the first level signal and second electrical level signal Logic level is on the contrary, the first level signal such as generated is low level, then second electrical level signal is just high level.

Optionally, referring to Fig. 3, in another embodiment of the application, a kind of embodiment of the first buffer cell 201, Include:

First end accesses the 11st switching tube M11 of power vd D, and the second end of the 11st switching tube M11 is opened with the 12nd The first end for closing pipe M12 is connected, and the 11st switching tube M11 is PMOS tube.

The 12nd switching tube M12 that first end is connected with the second end of the 11st switching tube M11, the 12nd switching tube M12 Second end be connected with the second end of the 14th switching tube M14, the 12nd switching tube M12 be PMOS tube.

First end connects the 13rd switching tube M13 of the second end of the 11st switching tube M11, the 13rd switching tube M13's Second end ground connection, the control terminal of the 13rd switching tube M13 connect the second end of the 12nd switching tube M12, the 13rd switching tube M13 For PMOS tube.

The 14th switching tube M14 that first end is connected with the second end of the 15th switching tube M15, the 14th switching tube M14 Second end be connected with the second end of the 12nd switching tube M12, the 14th switching tube M14 be NMOS tube.

The second end of 15th switching tube M15 of first end ground connection, the 15th switching tube M15 connect the 14th switching tube The first end of M14, the 11st switching tube M11, the 12nd switching tube M12, the 14th switching tube M14 and the 15th switching tube M15 Control terminal be connected and the input pin as input buffer, the 15th switching tube M15 be NMOS tube.

The sixteenmo that first end connects the first end of the 14th switching tube M14 closes pipe M16, and sixteenmo closes pipe M16's Second termination power vd D, the control terminal that sixteenmo closes pipe M16 connect the control terminal of the 13rd switching tube M13, and sixteenmo closes Pipe M16 is NMOS tube.

Wherein, first end is the source electrode of metal-oxide-semiconductor, and second end is the drain electrode of metal-oxide-semiconductor, and control terminal is the grid at the end MOS, other Unit describes method with this.

Input terminal connects the first phase inverter INV1 of the control terminal of the 13rd switching tube M13, input terminal and the first phase inverter The second phase inverter INV2 that the output end of INV1 is connected, the second phase inverter INV2 export the first level signal Q1, input terminal and the The output end of two phase inverter INV2 connected third phase inverter INV3, third phase inverter INV3 export second electrical level signal Q2.

Wherein, second electrical level signal Q2 is first output signal OUT<1>of the first buffer cell.

Second buffer cell 202, for receiving the input signal and the first level signal, second electrical level of input buffer Signal generates the second output signal OUT<0>of input buffer.

Optionally, referring to fig. 4, in another embodiment of the application, a kind of embodiment of the second buffer cell 202, Include:

Pull down resistor comparing unit 401, pull-up resistor comparing unit 402, phase inverter 403 and logic unit 404.Wherein:

Pull down resistor comparing unit 401 is used to receive the input signal of input buffer, generates third level signal.

Optionally, referring to Fig. 5, in another embodiment of the application, a kind of embodiment party of pull down resistor comparing unit 401 Formula, comprising:

First end is respectively connected to the first switch tube M1 and second switch M2 of power vd D, the control of first switch tube M1 End is connected with the control terminal of second switch M2, wherein first switch tube M1 and second switch M2 is PMOS tube.

Third switching tube M3 of the first end as the input pin of input buffer, the second end of third switching tube M3 and the The second end of one switching tube M1 is connected, wherein third switching tube M3 is NMOS tube.

The 4th switching tube M4 that first end is grounded by first resistor R1, the second end and second switch of the 4th switching tube M4 The second end of pipe M2 is connected, and the 4th switching tube M4 is NMOS tube.

The 5th switching tube M5 that first end is grounded by second resistance R2, the second end of the 5th switching tube M5 pass through constant-current source Access power vd D, control terminal, the control terminal of the 4th switching tube M4 and the control terminal phase of the 5th switching tube M5 of third switching tube M3 Even, the 5th switching tube M5 is NMOS tube.

Output end accesses the first voltage comparator A1 of logic unit 404, the non-inverting input terminal of first voltage comparator A1 Connect the common end of the second end of first switch tube M1 and the second end of third switching tube M3, the reverse phase of first voltage comparator A1 Input terminal connects the common end of the second end of second switch M2 and the second end of the 4th switching tube M4.

Wherein, the output end of first voltage comparator A1 exports third level signal Q3, and third level signal Q3 input is patrolled It collects in unit 404.

Pull-up resistor comparing unit 402 is connected with the input port of pull down resistor comparing unit 401, for receiving input The input signal of buffer, generates the 4th level signal, and the 4th level signal obtains the 5th level signal by phase inverter 403.

Optionally, referring to Fig. 6, in another embodiment of the application, a kind of embodiment party of pull-up resistor comparing unit 402 Formula, comprising:

Sixth switching tube M6 of the first end as the input pin of input buffer, the 6th switching tube M6 is PMOS tube.

First end accesses the 7th switching tube M7 of power vd D by 3rd resistor R3, and the 7th switching tube M7 is PMOS tube.

First end accesses the 8th switching tube M8 of power vd D by the 4th resistance, and the second end of the 8th switching tube M8 passes through Current source ground connection, the 8th switching tube M8 is PMOS tube.

The control terminal of the control terminal of 6th switching tube M6, the control terminal of the 7th switching tube M7 and the 8th switching tube M8 is connected.

9th switching tube M9 of first end ground connection, the second end of the 9th switching tube M9 connect the second of the 6th switching tube M6 End, the 9th switching tube M9 is NMOS tube.

Tenth switching tube M10 of first end ground connection, the second end of the tenth switching tube M10 connect the second of the 7th switching tube M7 End, the tenth switching tube M10 is NMOS tube.

The control terminal of 9th switching tube M9 is connected with the control terminal of the tenth switching tube M10.

The output end of second voltage comparator A2 accesses logic unit 404, second voltage comparator A2 by phase inverter 403 Non-inverting input terminal connect the 6th switching tube M6 second end and the 9th switching tube M9 second end common end, second voltage ratio Inverting input terminal compared with device A2 connects the common end of the second end of the 7th switching tube M7 and the second end of the tenth switching tube M10.

Wherein, the output end of second voltage comparator A2 exports the 4th level signal Q4.

Phase inverter 403, for receiving the 4th level signal of the generation of pull-up resistor comparing unit 402, output and the 4th electricity The 5th reversed level signal of ordinary mail number.

Logic unit 404 is for receiving the first level signal, second electrical level signal, third level signal, the 4th level letter Number and the 5th level signal, and according to the first level signal, second electrical level signal, third level signal, the 4th level signal and 5th level signal generates the second output signal OUT<0>of input buffer.

Optionally, referring to Fig. 7, in another embodiment of the application, a kind of embodiment of logic unit 404, comprising:

First NAND gate I1, the first NAND gate I1 input terminal access second electrical level signal Q2, third level signal Q3 and The output end of 4th level signal Q4, the first NAND gate I1 export the 6th level signal Q6.

The input terminal of second NAND gate I2, the second NAND gate I2 access the first level signal Q1, third level signal Q3 and The output end of 5th level signal Q5, the second NAND gate I2 export the 7th level signal Q7.

The input terminal of third NAND gate I3, third NAND gate I3 input the 6th level signal Q6 and the 7th level signal Q7, The second output signal OUT<0>of third NAND gate I3 output end output input buffer.

Control unit 203 is for receiving reversed the first enable signal and the second enable signal, according to the first enable signal The working condition of the second buffer cell is controlled with the high level or low level state of the second enable signal.

Specifically, the work of the second buffer cell of high level or low level control of the first enable signal and the second enable signal Make state, when input buffer does not have input signal, the second buffer cell is made by the low level of the first enable signal and second The high level control of energy signal, inside are flowed without quiescent current, and the second buffer cell is not at can working condition.When input is slow When rushing device has input signal, the second buffer cell is by the high level of the first enable signal and the low level control of the second enable signal System, internal stationary electric current flowing, the second buffer cell is in can working condition.

Optionally, referring to Fig. 8, in another embodiment of the application, a kind of embodiment of control unit 203, comprising:

First control subelement 801 and the second control subelement 802.Wherein:

First control subelement 801 is for receiving the first enable signal and the second enable signal, according to the first enable signal With the working condition of high level or low level state the control pull down resistor comparing unit 401 of the second enable signal.

Optionally, referring to Fig. 9, in another embodiment of the application, a kind of embodiment of the first control subelement 900, Include:

First end accesses the 17th switching tube M17 of power vd D, and the second end connection first of the 17th switching tube M17 is opened The control terminal of pipe M1 is closed, the control terminal of the 17th switching tube M17 receives the first enable signal EN, wherein the 17th switching tube M17 It is PMOS tube.

The eighteenmo of first end ground connection closes pipe M18, and eighteenmo closes the second end connection third switching tube M3's of pipe M18 Control terminal, the control terminal that eighteenmo closes pipe M18 receive the second enable signal ENN, and the tenth switching tube M18 is NMOS tube.

Specifically, when input buffer does not have input signal, power-on reset signal PORN is in low level referring to Figure 11 State, the first enable signal EN are controlled by power-on reset signal PORN, are in low level state.And the second enable signal ENN with First enable signal EN is reversed, is in high level state.

When input buffer has input signal, power-on reset signal PORN is in high level state, the first enable signal EN is controlled by power-on reset signal PORN, is in high level state, and the second enable signal ENN and the first enable signal EN are reversed, In low level state.

Specifically, when input buffer does not have input signal, referring to Fig. 9, since the 17th switching tube M17 is PMOS Pipe, the conducting of PMOS tube control terminal input low level, input high level cut-off, at this time the control terminal input of the 17th switching tube M17 The first enable signal EN be low level state, therefore the 17th switching tube M17 is connected.And the second of the 17th switching tube M17 The control terminal of end connection first switch tube M1 is also connected to the control terminal of second switch M2, therefore the high level letter of power vd D Number the control terminal of first switch tube M1 is applied to, in the control terminal of second switch M2 by the 17th switching tube M17 be connected. Since first switch tube M1 and second switch M2 are PMOS tube, when control terminal input high level, is in off state.

And it is NMOS tube that eighteenmo, which closes pipe M18, the conducting of NMOS tube control terminal input high level, input low level cut-off, The second enable signal ENN that eighteenmo closes the control terminal input of pipe M18 at this time is in high level state, therefore eighteenmo closes Pipe M18 conducting.And the control terminal of second end and third switching tube M3 because of eighteenmo pass pipe M18, the 4th switching tube M4's Control terminal, the control terminal of the 5th switching tube M5 are connected, therefore the control of the control terminal, the 4th switching tube M4 of third switching tube M3 It holds, the control terminal of the 5th switching tube M5 closes pipe M18 by eighteenmo and accessed low level, third switching tube M3, the 4th switch Pipe M4, the 5th switching tube M5 are NMOS tube, therefore all in off state.

When input buffer has input signal, at the first enable signal EN of the 17th switching tube M17 control terminal input In high level state, the 17th switching tube M17 ends at this time, the control of the control terminal, second switch M2 of first switch tube M1 End is not influenced by the 17th switching tube M17.

And eighteenmo closes pipe M18 control terminal and inputs the second enable signal ENN and is in low level state, eighteenmo at this time Pipe M18 cut-off is closed, the control terminal of third switching tube M3, the control terminal of the 4th switching tube M4, the control terminal of the 5th switching tube M5 are not Being closed pipe M18 by eighteenmo is influenced.

Therefore, when input buffer does not have input signal, even if power vd D and constant-current source are all located in pull down resistor unit In high level state, but the switching tube in pull down resistor unit 401 is in off state, and inside does not have quiescent current, drop-down Resistance comparing unit 401 does not have power consumption caused by quiescent current, and pull down resistor unit 401 at this time is not at working condition.When When input buffer has input signal, the 17th switching tube M17 and eighteenmo close pipe M18 and are turned off, and are now in high level The power vd D and constant-current source of state make have quiescent current to flow through inside pull down resistor comparing unit 401, and pull down resistor compares Unit 401 is in the transition that can be worked, and input signal can work normally when inputting pull down resistor comparing unit 401.

Second control subelement 802 is used for for receiving the first enable signal and the second enable signal, enabled according to first The working condition of signal and the high level or low level state of the second enable signal control pull-up resistor comparing unit 402.

Optionally, referring to Figure 10, in another embodiment of the application, a kind of embodiment party of the second control subelement 1000 Formula, comprising:

First end accesses the 19th switching tube M19 of power vd D, and the second end connection the 6th of the 19th switching tube M19 is opened The control terminal of pipe M6 is closed, the control terminal of the 19th switching tube M19 receives the first enable signal EN, and the 19th switching tube M19 is PMOS tube.

The second end of 20th switching tube M20 of first end ground connection, the 20th switching tube M20 connect the 9th switching tube M9's The control terminal of control terminal, the 20th switching tube M20 receives the second enable signal ENN, and the 20th switching tube M20 is NMOS tube.

Specifically, when input buffer does not have input signal, power-on reset signal PORN is in low level referring to Figure 11 State, the first enable signal EN are controlled by power-on reset signal PORN, be in low level state, and the second enable signal ENN with First enable signal EN is reversed, is in high level state.When input buffer has input signal, at power-on reset signal PORN In high level state, the first enable signal EN is controlled by power-on reset signal PORN, is in high level state, the second enable signal ENN and the first enable signal EN are reversed, are in low level state.

Specifically, when input buffer does not have input signal, referring to Figure 10, since the 19th switching tube M19 is PMOS Pipe, the first enable signal EN of the grid input of the 19th switching tube M19 is low level state at this time, therefore the 19th switching tube M19 conducting.And the second end of the 19th switching tube connect the control terminal of the 6th switching tube M6, the control terminal of the 7th switching tube M7, The control terminal of 8th switching tube M8.Therefore the high level signal of power vd D is applied to the by the 19th switching tube M19 of conducting The control terminal of six switching tube M6, the control terminal of the 7th switching tube M7, in the control terminal of the 8th switching tube M8.Due to the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8 are PMOS tube, and when control terminal input high level is in off state.

And the 20th switching tube M20 is NMOS tube, the second enable signal that the grid of the 20th switching tube M20 inputs at this time ENN is in high level state, therefore the 20th switching tube M20 is connected.Again because of the second end and the 9th of the 20th switching tube M20 The control terminal of switching tube M9, the control terminal of the tenth switching tube M10 are connected, therefore the control terminal of the 9th switching tube M9, the tenth open The control terminal for closing pipe M10 has accessed low level by the 20th switching tube M20, and the 9th switching tube M9, the tenth switching tube M10 are NMOS tube, therefore all in off state.

When input buffer has input signal, at the first enable signal EN of the 19th switching tube M19 control terminal input In high level state, the 19th switching tube M19 ends at this time, the control of the control terminal, the 7th switching tube M7 of the 6th switching tube M6 It holds, the control terminal of the 8th switching tube M8 is not influenced by the 19th switching tube M19.

And the 20th switching tube M20 control terminal inputs the second enable signal ENN and is in low level state, the 20th opens at this time Pipe M20 cut-off is closed, the control terminal of the 9th switching tube M9, the control terminal of the tenth switching tube M10 be not by the shadow of the 20th switching tube M20 It rings.

Therefore, when input buffer does not have input signal, even if power vd D and constant-current source in pull-up resistor unit 402 All in high level state, but the switching tube in pull-up resistor unit 402 is in off state, and inside does not have quiescent current, Pull-up resistor comparing unit 402 does not have power consumption caused by quiescent current, and pull-up resistor unit 402 at this time is not at work shape State.When input buffer has input signal, the 19th switching tube M19 and the 20th switching tube M20 are turned off, and are now in height The power vd D and constant-current source of level state make have quiescent current to flow through inside pull-up resistor comparing unit 402, pull-up resistor Comparing unit 402 is in the transition that can be worked, and input signal can work normally when inputting pull-up resistor comparing unit 402.

It can be seen from the above technical scheme that input buffer provided by the invention is defeated by the first buffer cell 201 First output signal OUT<1>out exports second output signal OUT<0>by the second buffer cell 202, also, two The input signal of buffer cell is inputted from the input pin of input buffer, i.e., single input pin can export four kinds of logics State saves the pin resource in integrated circuit.Meanwhile the work shape of the second buffer cell 202 is controlled by control unit State, when so that input buffer not having input signal, the second buffer cell 202 is not at working condition, and inside does not have Static Electro Stream, reduces the power consumption of input buffer.

Optionally, the embodiment of the present application discloses the circuit of another input buffer, referring to Figure 12, comprising: first is slow Rush unit 1201, pull down resistor comparing unit 1202, pull-up resistor comparing unit 1203, phase inverter 1204, logic unit 1205, First control subelement 1206, the second control subelement 1207, the first d type flip flop 1208, the second d type flip flop 1209.

First buffer cell 1201 is used to receive the input signal of input buffer, generates the first reversed level signal Q1 With second electrical level signal Q2, first output signal OUT<1>of the second electrical level signal Q2 as input buffer.

The first buffer cell 1201 is identical as the implementation procedure of the first buffer cell in Fig. 3 and principle herein, here It repeats no more.

Pull down resistor comparing unit 1202 is used to receive the input signal of input buffer, generates third level signal Q3.

The implementation procedure and principle phase of pull down resistor comparing unit in pull down resistor comparing unit 1202 and Fig. 5 herein Together, which is not described herein again.

Pull-up resistor comparing unit 1203 is connected with the input port of pull down resistor comparing unit 1202, for receiving input The input signal of buffer, generates the 4th level signal Q4, and the 4th level signal Q4 obtains the 5th level by phase inverter 1204 Signal Q5.

The implementation procedure and principle phase of pull-up resistor comparing unit in pull-up resistor comparing unit 1203 and Fig. 6 herein Together, which is not described herein again.

Phase inverter 1204 is identical as the implementation procedure of the phase inverter 403 in Fig. 4 and principle herein, and which is not described herein again.

Logic unit 1205 is for receiving the first level signal Q1, second electrical level signal Q2, third level signal Q3, the 4th Level signal Q4 and the 5th level signal Q5, and according to the first level signal Q1, second electrical level signal Q2, third level signal Q3, the 4th level signal Q4 and the 5th level signal Q5 generate the second output signal OUT<0>of input buffer.

Logic unit 1205 is identical as the implementation procedure of the logic unit in Fig. 7 and principle herein, and which is not described herein again.

First control subelement 1206 is for receiving the first enable signal and the second enable signal, according to the first enable signal With the working condition of high level or low level state the control pull down resistor comparing unit 1202 of the second enable signal.

The first control subelement 1206 is identical as the implementation procedure of the first control subelement in Fig. 9 and principle herein, Which is not described herein again.

Second control subelement 1207 is for receiving the first enable signal and the second enable signal, according to the first enable signal With the working condition of high level or low level state the control pull-up resistor comparing unit 1203 of the second enable signal.

The second control subelement 1207 is identical as the implementation procedure of the second control subelement in Figure 10 and principle herein, Which is not described herein again.

First d type flip flop 1208 is connected with the first buffer cell 1201, and the data input pin of the first d type flip flop receives first Position output signal OUT<1>, the clock input postpones signal PORN-DELAY of the first d type flip flop, the first d type flip flop First output terminals A DDR<1>deposits the logic state of first output signal OUT<1>.

Specifically, when input buffer has input signal, power-on reset signal PORN is got higher by low level referring to Figure 11 Level, postpones signal PORN-DELAY are obtained by power-on reset signal PORN delay time Td.In delay time Td, first is slow It rushes unit 1201 and completes multilevel iudge function, export first output signal OUT<1>, postpones signal PORN-DELAY is by low electricity Flat when becoming high level, it is inner that first output signal OUT<1>is deposited in ADDR<1>.

Second d type flip flop 1209 is connected with logic unit 1205, and the data input pin of the second d type flip flop 1209 receives second Position output signal OUT<0>, the clock input postpones signal PORN-DELAY of the second d type flip flop, the second d type flip flop First output terminals A DDR<0>is used to deposit the logic state of second output signal OUT<0>.

Specifically, when input buffer has input signal, power-on reset signal PORN is got higher by low level referring to Figure 11 Level, postpones signal PORN-DELAY are obtained by power-on reset signal PORN delay time Td.In delay time Td, drop-down electricity It hinders comparing unit 1202, pull-up resistor comparing unit 1203, phase inverter 1204, logic unit 1205 and completes multilevel iudge function, It exports second output signal OUT<0>, when postpones signal PORN-DELAY becomes high level by low level, second output letter It is inner that number OUT<0>is deposited in ADDR<0>.

Referring to Figure 12, following practical applications are realized.

P type metal oxide semiconductor (Positive channel-Metal-Oxide-Semiconductor, PMOS) When control termination low level, conducting；When high level, cut-off.

N-type metal-oxide semiconductor (MOS) (Negative channel-Metal-Oxide-Semiconductor, NMOS) When control termination low level, cut-off；When high level, conducting.

In pull down resistor comparing unit, the current value due to flowing through the 5th switching tube M5 is determined by current source IS1, and root According to the electric current calculation formula of transistor:

Therefore when the resistance value of the resistance value of the 4th resistance R4 and the 5th resistance R5 is equal, the switch of the 4th switching tube M4 and the 5th The ratio of the breadth length ratio of pipe M5 determines the electric current of the 4th switching tube M4, and flows through the electric current of second switch M2 and flow through the 4th and open The electric current for closing pipe M4 is equal, and the ratio of the breadth length ratio of first switch tube M1 and second switch M2, which determines, flows through first switch tube The current value of M1.

In order to enable the electric current for flowing through first switch tube M1 and second switch M2 is equal, it is therefore desirable to the 4th switch be arranged The breadth length ratio of pipe M4 and the 5th switching tube M5 are equal, and first resistor R1 and second resistance R2 resistance value are equal, and first switch is arranged The breadth length ratio of pipe M1 and second switch M2 are equal.

Pull-up resistor comparing unit is similar with pull down resistor comparing unit, and the 9th switching tube M9 and the tenth switching tube are flowed through in order The electric current of M10 is equal, and the 7th switching tube M7 of setting is equal with the 8th switching tube M8, and the 9th switching tube M9 and the tenth switching tube is arranged M10 is equal, and setting 3rd resistor R3 is equal with the 4th resistance R4.Setting in principle and pull down resistor comparing unit 1202 herein Principle is identical, and which is not described herein again.

It should be noted that in the present embodiment by the setting of above-mentioned parameter so that the electric current for flowing through transistor is equal, Flow through the electric current of different crystal pipe into 1:1, still, in other embodiments, it is also possible that the electric current of different crystal pipe at Other proportionate relationships, the corresponding ratio for changing first resistor R1 and second resistance R2.

The output of four kinds of logic states is realized by four kinds of variations of input signal referring to table 1.Wherein first output Signal OUT<1>is a high position, and second output signal OUT<0>is low level.

Table 1

Practical application one

When the input pin of input buffer ground connection:

The 11st switching tube M11, the 12nd switching tube M12, the 14th switching tube M14 in first buffer cell 1201 and The grid of 15th switching tube M15 is connected, the input pin as input buffer.Because the 11st switching tube M11, the 12nd are opened Closing pipe M12 is PMOS tube, conducting when grid connects low level.14th switching tube M14 and the 15th switching tube M15 is NMOS tube, Grid ends when accessing low level.11st switching tube M11 source electrode meets power vd D, and drain electrode connects the source of the 12nd switching tube M12 Pole, the 11st switching tube M11 and the 12nd switching tube M12 are connected when grid accesses low level, are equivalent to connection power supply VDD, so the drain electrode of the 12nd switching tube M12 is high level, correspondingly, the grid of the 13rd switching tube M13, sixteenmo close The grid of pipe M16 is connected with the drain electrode of the 12nd switching tube M12, belongs to same current potential, and therefore, which is high level.Again Via first output signal OUT < 1 of output after the first phase inverter INV1, the second phase inverter INV2, third phase inverter INV3 series connection >, first output signal OUT<1>is low level.And the first level signal Q1 and first exported via the second phase inverter INV2 Position output signal OUT<1>is high level reversely.

When the input signal for receiving input buffer is low level, first switch tube in pull down resistor comparing unit 1202 The source electrode of M1 meets power vd D, then is grounded by third switching tube M3, and the source electrode of second switch M2 meets power vd D, then by the 4th Switching tube M4 is grounded by first resistor R1, and since electric current passes through first resistor R1, there are voltages at the both ends first resistor R1, therefore The source voltage of 4th switching tube M4 is greater than 0, and the source electrode of third switching tube M3 is grounded, source voltage 0.Again because third is opened The grid for closing pipe M3 is connected with the grid of the 4th switching tube M4, is same current potential, therefore the gate source voltage of third switching tube M3 is poor Gate source voltage greater than the 4th switching tube M4 is poor.Again because flowing through the electric current of third switching tube M3, and the 4th switching tube M4 is flowed through Electric current be set as equal, therefore, according to formula (1) it is found that the drain-source voltage of the 4th switching tube M4 be greater than third switching tube The drain-source voltage of M3, to obtain, drain voltage VB of the drain voltage VA less than the 4th switching tube M4 of third switching tube M3, again Because the drain electrode of third switching tube M3 connects the in-phase end of first voltage comparator A1, the drain electrode of the 4th switching tube M4 connects first voltage The reverse side of comparator A1, therefore the third level signal Q3 of first voltage comparator A1 output is low level.

When the input pin ground connection of pull-up resistor comparing unit 1203, i.e. the source electrode ground connection of the 6th switching tube M6, so that the Six switching tube M6 are in off state, therefore the drain voltage of the 6th switching tube M6 is 0, and the source electrode of the 7th switching tube M7 passes through the Three resistance R3 meet power vd D, therefore, drain voltage of the drain voltage greater than the 6th switching tube M6 of the 7th switching tube M7, and because The in-phase end of second voltage comparator A2 is connect for the drain electrode of the 6th switching tube M6, the drain electrode of the 7th switching tube M7 connects second voltage ratio Compared with the reverse side of device A2, so the 4th level signal Q4 of second voltage comparator A2 output is low level.4th level signal Q4 is high level by the 5th level signal Q5 that phase inverter 1204 exports.

First NAND gate I1 of logic unit 1205 is received: second electrical level signal Q2 (being at this time low level), third level It is high level that signal Q3 (being at this time low level) and the 4th level signal Q4 (being at this time low level), which generates the 6th level signal Q6,.

Second NAND gate I2 of logic unit 1205 is received: the first level signal Q1 (being at this time high level), third level Signal Q3 (being at this time low level) and the 5th level signal Q5 (being at this time high level), generating the 7th level signal Q7 is high electricity It is flat.

The third NAND gate I3 of logic unit 1205 is received: the 6th level signal Q6 (being at this time high level), the 7th level Signal Q7 (being at this time high level), the second output signal OUT<0>of generation are low level.

First control subelement 1206, when input pin accesses input signal, the first enable signal EN is in height at this time Level state, the 17th switching tube M17 end, first switch tube M1, second switch in pull down resistor comparing unit 1202 The working condition of M2 is not influenced by the 17th switching tube M17.Second enable signal ENN is now in low level state, and the 18th Switching tube M18 ends, third switching tube M3, the 4th switching tube M4 and the 5th switching tube M5 in pull down resistor comparing unit 1202 Working condition not by eighteenmo close pipe M18 influenced.Pull down resistor comparing unit 1202 is in can working condition.

Second control subelement 1207, when input pin accesses input signal, the first enable signal EN is in height at this time Level state, the 19th switching tube M19 end, the 6th switching tube M6, the 7th switching tube in pull-up resistor comparing unit 1203 The working condition of M7 and the 8th switching tube M8 are not influenced by the 19th switching tube M19.Second enable signal ENN is now in low electricity Level state, the 20th switching tube M20 end, the 9th switching tube M9, the tenth switching tube M10 in pull-up resistor comparing unit 1203 Working condition do not influenced by the 20th switching tube M20.Pull-up resistor comparing unit 1203 is in can working condition.

First d type flip flop 1208, the first d type flip flop 1208 is connected with the first buffer cell 1201 at this time, the first d type flip flop Data input pin receive first output signal OUT<1>, the clock input postpones signal PORN- of the first d type flip flop DELAY, when postpones signal PORN-DELAY becomes high level from low level, first output terminals A DDR<1>of the first d type flip flop Deposit the logic state of first output signal OUT<1>.

Second d type flip flop 1209, the second d type flip flop 1209 is connected with logic unit 1205 at this time, the second d type flip flop 1209 Data input pin receive second output signal OUT<0>, the clock input postpones signal PORN- of the second d type flip flop DELAY, when postpones signal PORN-DELAY becomes high level from low level, the first output terminals A DDR<0>of the second d type flip flop Deposit the logic state of second output signal OUT<0>.

Therefore, when input buffer be grounded when, input buffer output the first logic state MODE0 be deposited in ADDR < 1:0 >, it is 00.

Actual application two

When the input pin of input buffer passes through resistance R (resistance value that the resistance value of resistance R is greater than first resistor R1) ground connection When:

The 11st switching tube M11, the 12nd switching tube M12, the 14th switching tube M14 in first buffer cell 1201 and The grid of 15th switching tube M15 is connected, and is the input pin of input buffer.Because of the 11st switching tube M11, the 12nd switch Pipe M12 is PMOS tube, and when grid input low level is connected.14th switching tube M14 and the 15th switching tube M15 is NMOS tube, End when grid input low level.11st switching tube M11 source electrode meets power vd D, and drain electrode connects the source of the 12nd switching tube M12 Pole, the 11st switching tube M11 and the 12nd switching tube M12 are connected under grid input low level, so the 12nd switching tube The drain electrode of M12 is high level, correspondingly, the grid of the 13rd switching tube M13, sixteenmo close the grid and the tenth of pipe M16 The drain electrode of two switching tube M12 belongs to same current potential, and therefore, which is high level.Again via the first phase inverter INV1, second First output signal OUT<1>, first output signal OUT<1>are exported after phase inverter INV2, third phase inverter INV3 series connection The first level signal Q1 for low level, and the second phase inverter INV2 output is high level.

The input pin of pull down resistor comparing unit 1202 is grounded by resistance R, in pull down resistor comparing unit 1202 The source electrode of one switching tube M1 meets power vd D, and the source electrode of second switch M2 meets power vd D, because of the resistance R ratio that input pin connects First resistor R1 is big, and because be provided with flow through third switching tube M3 with the electric current for flowing through the 4th switching tube M4 and be it is equal, Therefore the voltage at the both ends resistance R is greater than the voltage at the both ends first resistor R1, i.e. the source voltage of third switching tube M3 is greater than the 4th The source voltage of switching tube M4.Again because the grid of third switching tube M3 is connected with the grid of the 4th switching tube M4, current potential is equal, Therefore the gate source voltage of M3 is less than the gate source voltage of M4, according to formula (1) it is found that the drain-source voltage of third switching tube M3 is greater than the The drain-source voltage of four switching tube M4, to obtain, the drain voltage VA of third switching tube M3 is greater than the drain electrode of the 4th switching tube M4 Voltage VB, but because the drain electrode of third switching tube M3 connects the in-phase end of first voltage comparator A1, the drain electrode of the 4th switching tube M4 The reverse side of first voltage comparator A1 is connect, therefore first voltage comparator A1 output third level Q3 is high level.

The input pin of pull-up resistor comparing unit 1203 is grounded by resistance R, and the source electrode of the 6th switching tube M6 passes through electricity R ground connection is hindered, so that the 6th switching tube M6 is in off state, therefore the drain voltage of the 6th switching tube M6 is 0, the 7th switching tube The source electrode of M7 meets power vd D by 3rd resistor R3, and therefore, the drain voltage VD of the 7th switching tube M7 is greater than the 6th switching tube M6 Drain voltage VC, and because the drain electrode of the 6th switching tube M6 meets the in-phase end of second voltage comparator A2, the 7th switching tube M7 Drain electrode connect the reverse side of second voltage comparator A2.So the 4th level signal Q4 of second voltage comparator A2 output is low Level, fiveth level signal Q5 of the 4th level signal Q4 by the output of the 4th phase inverter 1204 is high level.

First NAND gate I1 of logic unit 1205 is received: second electrical level signal Q2 (low level), third level signal Q3 (high level) and the 4th level signal Q4 (low level), the 6th level signal Q6 of generation are high level.

Second NAND gate I2 of logic unit 1205 is received: the first level signal Q1 (high level), third level signal Q3 (high level) and the 5th level signal (high level), the 7th level signal Q7 of generation are low level.

The third NAND gate I3 of logic unit 1205 is received: the 6th level signal Q6 (high level) and the 7th level signal Q7 (low level)；Generating second output signal OUT<0>is high level.

First control subelement 1206, the implementation procedure of the first control subelement 1206 in actual application two and Principle is identical as the implementation procedure of the first control subelement 1206 in actual application one and principle, no longer superfluous here It states.

Second control subelement 1207, the implementation procedure of the second control subelement 1207 in actual application two and Principle is identical as the implementation procedure of the second control subelement 1207 in actual application one and principle, no longer superfluous here It states.

First d type flip flop 1208, the implementation procedure and principle of the first d type flip flop 1208 in actual application two with The implementation procedure and principle of the first d type flip flop 1208 in actual application one are identical, and which is not described herein again.

Second d type flip flop 1209, the implementation procedure and principle of the second d type flip flop 1209 in actual application two with The implementation procedure and principle of the second d type flip flop 1209 in actual application one are identical, and which is not described herein again.

Therefore, when input buffer is by resistance R (resistance value that the resistance value of resistance R is greater than resistance R1) ground connection, input is slow It rushes the second logic state MODE1 of device output to be deposited in ADDR<1:0>, is 01.

Actual application three

When the input pin of input buffer connects electricity by resistance R (resistance value that the resistance value of resistance R is greater than 3rd resistor R3) When the VDD of source:

The 11st switching tube M11, the 12nd switching tube M12, the 14th switching tube M14 in first buffer cell 1201 and The grid of 15th switching tube M15 connects, the input pin as input buffer.Because the 11st switching tube M11, the 12nd are opened Closing pipe M12 is PMOS tube, since grid has input high level cut-off.14th switching tube M14 and the 15th switching tube M15 are NMOS tube, grid have input high level conducting.Because the 14th switching tube M14 and the 15th switching tube M15 is NMOS transistor conduction, make The drain electrode for obtaining the 14th switching tube M14 is low level, and corresponding 13rd switching tube M13 and sixteenmo close the grid of pipe M16 Belong to same current potential with the 12nd switching tube M12 drain electrode, therefore, which is low level.Again by the first phase inverter INV1, First output signal OUT<1>, first output signal OUT<1 are exported after two phase inverter INV2, third phase inverter INV3 series connection > it is high level.First level signal Q1 of the second phase inverter INV2 output is low level.

1202 input pin of pull down resistor comparing unit meets power vd D by resistance R, in pull down resistor comparing unit 1202 The drain electrode of third switching tube M3 meets power vd D by resistance R, is greater than grid electricity so as to cause the source voltage of third switching tube M3 Pressure, third switching tube M3 are in off state.The drain voltage of first switch is equivalent to power supply vdd voltage at this time.And second opens The source electrode for closing pipe M2 meets power vd D, then is grounded by the 4th switching tube M4 by first resistor R1.Therefore the leakage of first switch tube M1 Pole tension VA is greater than the drain voltage VB of second switch M2, and because the drain electrode of first switch tube M1 connects first voltage comparator The in-phase end of A1, the drain electrode of second switch M2 meet the reverse side of first voltage comparator A1, therefore first voltage comparator A1 The third level signal Q3 of output is high level.

1203 input pin of pull-up resistor comparing unit meets power vd D by resistance R, and the source electrode of the 6th switching tube M6 passes through Resistance R meets power vd D, and the source electrode of the 7th switching tube M7 meets power vd D by 3rd resistor R3, and drain electrode passes through the tenth switching tube M10 ground connection.Since the electric current for flowing through resistance R is equal with the electric current for flowing through 3rd resistor R3, and the resistance value of resistance R is greater than third electricity R3, therefore source voltage of the source voltage of the 6th switching tube M6 less than the 7th switching tube M7 are hindered, at this point, the 6th switching tube M6 Gate source voltage difference is poor less than the gate source voltage of the 7th switching tube M7, and because flows through the electric current of the 6th switching tube M6 and flow through the 7th The electric current of switching tube M7 is equal, according to formula (1), it is known that the drain-source voltage difference of the 6th switching tube M6 is greater than the 7th switching tube M7's Drain-source voltage is poor, to obtain, drain voltage VD of the drain voltage VC less than the 7th switching tube M7 of the 6th switching tube M6.And because The in-phase end of second voltage comparator A2 is connect for the drain electrode of the 6th switching tube M6, the drain electrode of the 7th switching tube M7 connects second voltage ratio Compared with the reverse side of device A2, so the 4th level signal Q4 of second voltage comparator A2 output is low level, by phase inverter 5th level signal Q5 of 1204 outputs is high level.

First NAND gate I1 of logic unit 1205 receives second electrical level signal Q2 (high level), third level signal Q3 (high level) and the 4th level signal (low level), the 6th level signal Q6 of generation are high level.

Second NAND gate I2 of logic unit 1205 receives the first level signal Q1 (low level), third level signal Q3 (high level) and the 5th level signal Q5 (high level), the 7th level signal of generation are high level.

The third NAND gate I3 of logic unit 1205 receives the 6th level signal Q6 (high level), the 7th level signal Q7 (high level), generating second output signal OUT<0>is low level.

First control subelement 1206, the implementation procedure of the first control subelement 1206 in actual application three and Principle is identical as the implementation procedure of the first control subelement 1206 in actual application one and principle, no longer superfluous here It states.

Second control subelement 1207, the implementation procedure of the second control subelement 1207 in actual application three and Principle is identical as the implementation procedure of the second control subelement 1207 in actual application one and principle, no longer superfluous here It states.

First d type flip flop 1208, the implementation procedure and principle of the first d type flip flop 1208 in actual application three with The implementation procedure and principle of the first d type flip flop 1208 in actual application one are identical, and which is not described herein again.

Second d type flip flop 1209, the implementation procedure and principle of the second d type flip flop 1209 in actual application three with The implementation procedure and principle of the second d type flip flop 1209 in actual application one are identical, and which is not described herein again.

Therefore, when input buffer is by resistance R (resistance value that the resistance value of resistance R is greater than resistance R3) ground connection, input is slow It rushes device output third logic state MODE2 to be deposited in ADDR<1:0>, is 10.

Actual application four

When the input pin of input buffer meets power vd D:

The 11st switching tube M11, the 12nd switching tube M12, the 14th switching tube M14 in first buffer cell 1201 and The grid of 15th switching tube M15 connects, the input pin as input buffer.Because the 11st switching tube M11, the 12nd are opened Closing pipe M12 is PMOS tube, and grid accesses high level cut-off.14th switching tube M14 and the 15th switching tube M15 is NMOS tube, Grid accesses high level conducting.Because the 14th switching tube M14, the 15th switching tube M15 are connected, so that the 14th switching tube M14 Drain electrode be low level, correspondingly, the grid of the 13rd switching tube M13, sixteenmo close pipe M16 grid, the 12nd switch Pipe M12 drain electrode belongs to same current potential, and therefore, which is low level.Again by the first phase inverter INV1, the second phase inverter High level is exported after INV2, third phase inverter INV3 series connection, the level value of third phase inverter INV3 output is first output letter Number OUT<1>.First level signal Q1 of the second phase inverter INV2 output is low level.

When 1202 input pin of pull down resistor comparing unit meets power vd D, third is opened in pull down resistor comparing unit 1202 It closes pipe M3 source electrode and meets power vd D, be greater than grid voltage so as to cause the source voltage of third switching tube M3, be in off state. The drain voltage VA of first switch M1 is equivalent to supply voltage VDD at this time.The source electrode of second switch M2 meets power vd D, then by 4th switching tube M4 is grounded by the first pull down resistor.Therefore the drain voltage VA of first switch tube M1 is greater than second switch M2 Drain voltage VB, and because the drain electrode of first switch tube M1 meets the in-phase end of first voltage comparator A1, second switch M2 Drain electrode connect the reverse side of first voltage comparator A1, therefore the third level signal Q3 of first voltage comparator A1 output is height Level.

When 1203 input pin of pull-up resistor comparing unit meets power vd D, the source electrode of the 6th switching tube M6 meets power vd D, Therefore the drain voltage of the 6th switching tube M6 is to be equivalent to supply voltage VDD, and the source electrode of the 7th switching tube M7 passes through 3rd resistor R3 meets power vd D, and the both ends resistance R3 generate pressure drop, and therefore, the drain voltage VC of the 6th switching tube M6 is greater than the 7th switching tube M7 Drain voltage VC, and because the drain electrode of the 6th switching tube M6 meets the in-phase end of second voltage comparator A2, the 7th switching tube M7 Drain electrode connect the reverse side of second voltage comparator A2, so the 4th level signal Q4 of second voltage comparator A2 output is height Level.4th level signal Q4 is low level by the 5th level signal Q5 that the 4th phase inverter 1204 exports.

First NAND gate I1 of logic unit 1205 is received: second electrical level signal Q2 (high level), third level signal Q3 (high level) and the 4th level signal Q4 (high level), the 6th level signal Q6 of generation are low level.

Second NAND gate I2 of logic unit 1205 is received: the first level signal Q1 (low level), third level signal Q3 (high level) and the 5th level signal (low level), the 7th level signal Q7 of generation are high level.

The third NAND gate I3 of logic unit 1205 is received: the 6th level signal Q6 (low level), the 7th level signal Q7 (high level), generating second output signal OUT<0>is high level.

First control subelement 1206, the implementation procedure of the first control subelement 1206 in actual application four and Principle is identical as the implementation procedure of the first control subelement 1206 in actual application one and principle, no longer superfluous here It states.

Second control subelement 1207, the implementation procedure of the second control subelement 1207 in actual application four and Principle is identical as the implementation procedure of the second control subelement 1207 in actual application one and principle, no longer superfluous here It states.

First d type flip flop 1208, the implementation procedure and principle of the first d type flip flop 1208 in actual application four with The implementation procedure and principle of the first d type flip flop 1208 in actual application one are identical, and which is not described herein again.

Second d type flip flop 1209, the implementation procedure and principle of the second d type flip flop 1209 in actual application four with The implementation procedure and principle of the second d type flip flop 1209 in actual application one are identical, and which is not described herein again.

Therefore, when the input pin of input buffer meets power vd D, input buffer exports the second logic state MODE3 is deposited in ADDR<1:0>, is 11.

Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with it is other The difference of embodiment, same or similar part may refer to each other between each embodiment.

Professional technician can be realized or using the present invention.Profession of the various modifications to these embodiments to this field It will be apparent for technical staff, the general principles defined herein can not depart from spirit or model of the invention In the case where enclosing, realize in other embodiments.Therefore, the present invention will not be limited to the embodiments shown herein, And it is to fit to the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. a kind of input buffer characterized by comprising

First buffer cell, the second buffer cell and control unit, the input port of first buffer cell and described the The input port of two buffer cells is connected, input pin of the tie point as the input buffer；Described control unit and institute The second buffer cell is stated to be connected；

First buffer cell is used to receive the input signal of the input buffer, generate reversed the first level signal and Second electrical level signal, first output signal of the second electrical level signal as the input buffer；

Second buffer cell is used to receive the input signal of the input buffer, first level signal and described the Two level signals generate the second output signal of the input buffer；

Described control unit is for receiving reversed the first enable signal and the second enable signal, according to first enable signal The working condition of second buffer cell is controlled with the high level or low level state of second enable signal.

2. input buffer according to claim 1, which is characterized in that second buffer cell, comprising: pull down resistor Comparing unit, pull-up resistor comparing unit, phase inverter and logic unit；Wherein:

The pull down resistor comparing unit is used to receive the input signal of the input buffer, generates third level signal；

The pull-up resistor comparing unit is connected with the input port of the pull down resistor comparing unit；It is described defeated for receiving Enter the input signal of buffer, generate the 4th level signal, the 4th level signal obtains the 5th level by phase inverter and believes Number；

The logic unit is for receiving first level signal, the second electrical level signal, the third level signal, institute State the 4th level signal and the 5th level signal, and according to first level signal, the second electrical level signal, described Third level signal, the 4th level signal and the 5th level signal, the second for generating the input buffer are defeated Signal out.

3. input buffer according to claim 2, which is characterized in that described control unit, comprising:

First control subelement and the second control subelement；Wherein:

The first control subelement is for receiving first enable signal and second enable signal, according to described first The high level or low level state of enable signal and second enable signal control the work of the pull down resistor comparing unit State；

The second control subelement is for receiving first enable signal and second enable signal, according to described first The high level or low level state of enable signal and second enable signal are for controlling the pull-up resistor comparing unit Working condition.

4. input buffer according to claim 3, which is characterized in that the pull down resistor comparing unit, comprising:

First end is respectively connected to the first switch tube and second switch of power supply, the control terminal of the first switch tube and described the The control terminal of two switching tubes is connected；

Third switching tube of the first end as the input pin of the input buffer, the second end of the third switching tube and institute The second end for stating first switch tube is connected；

The 4th switching tube that first end is grounded by first resistor, the second end and the second switch of the 4th switching tube Second end be connected；

The second end of the 5th switching tube that first end is grounded by second resistance, the 5th switching tube accesses electricity by constant-current source Source；The control terminal of the control terminal of the third switching tube, the control terminal of the 4th switching tube and the 5th switching tube is connected；

Output end access logic unit first voltage comparator, the first voltage comparator non-inverting input terminal connection described in The common end of the second end of first switch tube and the second end of the third switching tube, the reverse phase of the first voltage comparator are defeated Enter the common end that end connects the second end of the second switch and the second end of the 4th switching tube.

5. input buffer according to claim 4, which is characterized in that the first control subelement, comprising:

First end accesses the 17th switching tube of power supply, and the second end of the 17th switching tube connects the first switch tube The common end of the control terminal of control terminal and the second switch, the control terminal of the 17th switching tube, which receives described first, to be made It can signal；

The eighteenmo of first end ground connection closes pipe, and the second end that the eighteenmo closes pipe connects the control of the third switching tube The common end at end and the control terminal of the 4th switching tube, the control terminal that the eighteenmo closes pipe receive the described second enabled letter Number.

6. input buffer according to claim 3, which is characterized in that the pull-up resistor comparing unit, comprising:

Sixth switching tube of the first end as the input pin of the input buffer；

First end accesses the 7th switching tube of power supply by 3rd resistor；

First end accesses the 8th switching tube of power supply by the 4th resistance, and the second end of the 8th switching tube is connect by current source Ground；

Control terminal, the control terminal of the 7th switching tube and the control terminal phase of the 8th switching tube of 6th switching tube Even；

9th switching tube of first end ground connection, the second end of the 9th switching tube connect the second end of the 6th switching tube；

Tenth switching tube of first end ground connection, the second end of the tenth switching tube connect the second end of the 7th switching tube；

The control terminal of 9th switching tube is connected with the control terminal of the tenth switching tube；

Output end accesses the second voltage comparator of the logic unit by the phase inverter, the second voltage comparator Non-inverting input terminal connects the common end of the second end of the 6th switching tube and the second end of the 9th switching tube, and described second The inverting input terminal of voltage comparator connects the public affairs of the second end of the 7th switching tube and the second end of the tenth switching tube End altogether.

7. input buffer according to claim 6, which is characterized in that the second control subelement, comprising:

First end accesses the 19th switching tube of power supply, and the second end of the 19th switching tube connects the 6th switching tube The common end of control terminal and the control terminal of the 7th switching tube, the control terminal of the 19th switching tube, which receives described first, to be made It can signal；

20th switching tube of first end ground connection, the second end of the 20th switching tube connect the control of the 9th switching tube The common end at end and the control terminal of the tenth switching tube, the control terminal of the 20th switching tube receive the described second enabled letter Number.

8. input buffer according to claim 3, which is characterized in that the logic unit, comprising:

First NAND gate, the input terminal of first NAND gate access the second electrical level signal, the third level signal and The output end of 4th level signal, first NAND gate exports the 6th level signal；

Second NAND gate, the input terminal of second NAND gate access first level signal, the third level signal and The output end of 5th level signal, second NAND gate exports the 7th level signal；

The input terminal of third NAND gate, the third NAND gate inputs the 6th level signal and the 7th level signal, The third NAND gate output end exports the second output signal of the input buffer.

9. input buffer according to claim 1, which is characterized in that first buffer cell includes:

First end accesses the 11st switching tube of power supply, the second end of the 11st switching tube and the first of the 12nd switching tube End is connected；

The 12nd switching tube that first end is connected with the second end of the 11st switching tube, the 12nd switching tube Second end is connected with the second end of the 14th switching tube；

First end connects the of the common end of the second end of the 11st switching tube and the first end of the 12nd switching tube 13 switching tubes, the second end ground connection of the 13rd switching tube, the control terminal connection the described tenth of the 13rd switching tube The common end of the second end of two switching tubes and the second end of the 14th switching tube；

The 14th switching tube that first end is connected with the second end of the 15th switching tube, the second of the 14th switching tube End is connected with the second end of the 12nd switching tube；

15th switching tube of first end ground connection, the second end of the 15th switching tube connect the of the 14th switching tube One end, the control of the 11st switching tube, the 12nd switching tube, the 14th switching tube and the 15th switching tube End processed is connected and the input pin as the input buffer；

First end connects the of the common end of the first end of the 14th switching tube and the second end of the 15th switching tube Sixteenmo closes pipe, and the sixteenmo closes the second termination power of pipe, and the sixteenmo closes the control terminal connection described the of pipe The control terminal of 13 switching tubes；

Input terminal connect the 13rd switching tube control terminal and the sixteenmo close pipe control terminal common end the One phase inverter；

The second phase inverter that input terminal is connected with the output end of first phase inverter, the second phase inverter output described first Level signal；

The third phase inverter that input terminal is connected with the output end of second phase inverter, the third phase inverter output described second Level signal.

10. input buffer according to any one of claims 1 to 9, which is characterized in that further include:

The first d type flip flop being connected with first buffer cell, the data input pin of first d type flip flop receive described the One output signal, the clock input postpones signal of first d type flip flop, first of first d type flip flop Output end is used to deposit the logic state of first output signal；

The second d type flip flop being connected with second buffer cell, the data input pin of second d type flip flop receive described the Two output signals, the clock input postpones signal of second d type flip flop, the first of second d type flip flop are defeated Outlet is used to deposit the logic state of the second output signal.