CN106059503A - Voltage buffer amplifier - Google Patents
Voltage buffer amplifier Download PDFInfo
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- CN106059503A CN106059503A CN201610373501.3A CN201610373501A CN106059503A CN 106059503 A CN106059503 A CN 106059503A CN 201610373501 A CN201610373501 A CN 201610373501A CN 106059503 A CN106059503 A CN 106059503A
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- nmos tube
- circuit
- electric current
- grid
- buffer amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a voltage buffer amplifier. The voltage buffer amplifier comprises a main amplification circuit and a self-adaption circuit. The size of the working current of the main amplification circuit is determined by a first current sink; the self-adaption circuit provides a mirror current to the first current sink and automatically adjusts the current size of the first current sink based on the working state of the main amplification circuit; when the voltages at the positive-phase and negative-phase input ends are equal, the self-adaption circuit enables the current of the first current sink to be as a first value; when the voltages at the positive-phase and negative-phase input ends are different, the self-adaption circuit enables the current of the first current sink to be as a second value; the first value is less than the second value; the power consumption of the voltage buffer amplifier is reduced through the relatively small first value; and the charging and discharging speed of the output end of the voltage buffer amplifier is increased through the relatively big second value, and the slew rate is accordingly increased. According to the voltage buffer amplifier, the slew rate and the building speed of the voltage buffer amplifier are increased, the stabilizing time of the voltage buffer amplifier can be reduced, and the power consumption also can be decreased.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of voltage buffer amplifier.
Background technology
Voltage buffer (voltage buffer) generally provides for the voltage needed for circuit operation, to strengthen its driving
Ability, avoids load effect to arrive the output voltage of voltage buffer the most simultaneously.
Voltage buffer can provide the common-mode voltage needed for sample phase in gradually-appoximant analog-digital converter, in conversion
Stage need not this common-mode voltage, can be closed by voltage buffer in the conversion stage to save power consumption.
Owing to voltage buffer is set up and stably needs the regular hour, this can limit the speed of analog-digital converter.Additionally
For making buffer when driving other modules, it is possible to quickly set up and settle out, the Slew Rate that buffer have to be sufficiently large
And bandwidth, this just forces buffer to need the biggest quiescent current, and this causes voltage buffer circuit to occupy whole modulus
The power consumption that transducer is the biggest.Therefore a quick response and stable low power consumption voltage buffer are to whole analog-digital converter
Design important in inhibiting.
Summary of the invention
The technical problem to be solved is to provide a kind of voltage buffer amplifier, can improve voltage buffer amplifier
Slew Rate, improve setting up speed, reducing stabilization time of voltage buffer amplifier of voltage buffer amplifier, can also reduce simultaneously
Power consumption.
For solving above-mentioned technical problem, the voltage buffer amplifier that the present invention provides includes: main body amplifying circuit and adaptive
Answer circuit.
The operating current size of described main body amplifying circuit is determined by the first electric current is heavy.
Described adaptive circuit sinks for described first electric current provides image current the work according to described main body amplifying circuit
It is automatically adjusted the size of current that described first electric current is heavy as state.
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are equal, described adaptive circuit
The electric current making described first electric current heavy is the first value.
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are unequal, described self adaptation electricity
Road makes described first electric current, and heavy electric current is the second value.
Described first value, less than described second value, reduces the merit of described voltage buffer amplifier by the first less value
Consumption；Improve the outfan charge-discharge velocity of described voltage buffer amplifier by bigger described second value thus improve pendulum
Rate.
Further improving is that described adaptive circuit includes the first differential amplifier circuit and the second differential amplifier circuit.
The normal phase input end of described first differential amplifier circuit, the normal phase input end of described second differential amplifier circuit and institute
The normal phase input end stating main body amplifying circuit is connected, the inverting input of described first differential amplifier circuit, described second difference
The inverting input of amplifying circuit is connected with the inverting input of described main body amplifying circuit.
First difference inverted path of described first differential amplifier circuit and the second of described second differential amplifier circuit poor
The bottom dividing positive phase path is all connected to the second electric current and sinks.
The first positive phase path of difference of described first differential amplifier circuit and the second of described second differential amplifier circuit poor
The bottom of point inverted path is all connected to the 3rd electric current and sinks.
The top of the described second positive phase path of difference and described second difference inverted path all connects same first active
Load circuit.
The electric current of described first active pull-up circuit is mirrored to described first electric current by the first mirror image circuit and sinks.
Described second electric current is heavy and described 3rd electric current heavy mirror image and size of current are all the 3rd value each other.
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are equal, described first difference is anti-
The electric current of phase path is N times of the electric current of the described second positive phase path of difference, and the electric current of the described first positive phase path of difference is institute
Stating N times of electric current of the second difference inverted path, N is more than 1, and the size of current of described first active pull-up circuit is the described 3rd
Value is multiplied by 2/ (N+1), and described first active pull-up circuit is that described first electric current sinks mirror image and goes out the electric current that size is the first value.
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are unequal, described first difference
Positive phase path and described first difference inverted path there is the 3rd value described in an electric current convergence 0, another electric current convergence, described
The second positive phase path of difference and described second difference inverted path have described in an electric current convergence 0, another electric current convergence
Three are worth, and the 3rd value described in the size of current convergence of described first active pull-up circuit, described first active pull-up circuit is described
First electric current sinks mirror image and goes out the electric current that size is the second value.
Further improving is that described first difference inverted path is made up of the first NMOS tube, described first difference positive
Path is made up of the second NMOS tube, and described second difference inverted path is made up of the 3rd NMOS tube, described second difference positive road
Footpath is made up of the 4th NMOS tube；Described first NMOS tube and described second NMOS tube equal sized, described 3rd NMOS tube and
Described 4th NMOS tube equal sized, the breadth length ratio of the raceway groove of described first NMOS tube is the raceway groove of described 3rd NMOS tube
N times of breadth length ratio.
The grid of described first NMOS tube is the inverting input of described first differential amplifier circuit, described second NMOS tube
The normal phase input end that grid is described first differential amplifier circuit, the grid of described 3rd NMOS tube is that described second difference is put
The inverting input of big circuit, the normal phase input end that grid is described second differential amplifier circuit of described 4th NMOS tube.
Further improving and be, described second electric current is heavy to be made up of the 5th NMOS tube, and described 3rd electric current is heavy by the 6th
NMOS tube forms.
The source electrode of described 5th NMOS tube and source electrode all ground connection of described 6th NMOS tube.
The drain electrode of described 5th NMOS tube connects source electrode and the source electrode of described 4th NMOS tube of described first NMOS tube.
The drain electrode of described 6th NMOS tube connects source electrode and the source electrode of described 3rd NMOS tube of described second NMOS tube.
The grid of described 5th NMOS tube and the grid of described 6th NMOS tube are all connected to the second mirror image circuit, and described
Two electric currents are heavy and described 3rd electric current is heavy is all obtained by described second mirror image circuit mirror image.
Further improving and be, described second mirror image circuit includes the 7th NMOS tube, the grid of described 7th NMOS tube and
The grid of source electrode described 5th NMOS tube of connection and the grid of described 6th NMOS tube, the source ground of described 7th NMOS tube,
First current source is connected to the source electrode of described 7th NMOS tube and provides electric current for described second mirror image circuit.
Further improving is that described first current source is connected to the source of described 7th NMOS tube by the 8th NMOS tube
Pole, the drain electrode of the 9th NMOS tube connects the grid of described 7th NMOS tube, the source ground of described 9th NMOS tube；Described 8th
The grid of NMOS tube connects the first control signal, and the grid of described 9th NMOS tube connects the second control signal, described first control
Signal processed is high level and described voltage buffer amplifier work time described second control signal is low level, described first control
Signal processed is low level and described voltage buffer amplifier quits work time described second control signal is high level.
Further improving is that described first active pull-up circuit is made up of the tenth PMOS, described tenth PMOS
Source electrode connects supply voltage, the grid of described tenth PMOS and drain electrode and all connects the drain electrode of described 3rd NMOS tube.
Further improving is that described first mirror image circuit is made up of the 11st PMOS and the 12nd NMOS tube, described
First electric current is heavy to be made up of the 13rd NMOS tube.
The grid of described 11st PMOS connects the grid of described tenth PMOS, the source electrode of described 11st PMOS
Connecting supply voltage, the drain electrode of described 11st PMOS connects the drain and gate and described the of described 12nd NMOS tube
The grid of 13 NMOS tube, the source electrode of described 12nd NMOS tube and source electrode all ground connection of described 13rd NMOS tube.
Further improving and be, the source electrode of the 14th PMOS connects supply voltage, drain electrode connects described tenth PMOS
Grid, the grid of described 14th PMOS connects the first control signal.
The drain electrode of the 15th NMOS tube connects the grid of described 13rd NMOS tube, and the source electrode of described 15th NMOS tube connects
Ground, the grid of described 15th NMOS tube connects the second control signal.
Described first control signal is high level and described voltage buffer is put time described second control signal is low level
Big device work, described first control signal is low level and described voltage buffer is put time described second control signal is high level
Big device quits work.
Further improving and be, the first resistance is connected between drain electrode and the supply voltage of described first NMOS tube as institute
Stating the load of the first NMOS tube, the second resistance is connected between drain electrode and the supply voltage of described second NMOS tube as described
The load of two NMOS tube.
Further improving is that described main body amplifying circuit includes by the 16th NMOS tube and the 17th NMOS tube, described
The source electrode of the 16th NMOS tube and the source electrode of described 17th NMOS tube all connect described first electric current and sink.
The drain electrode of described 16th NMOS tube is connected to supply voltage by the second active pull-up circuit；Described 17th
The drain electrode of NMOS tube is connected to supply voltage by the 3rd active pull-up circuit.
The grid of described 16th NMOS tube is normal phase input end, and the grid of described 17th NMOS tube is anti-phase input
End；The drain electrode of described 17th NMOS tube is as the outfan of voltage buffer amplifier.
Further improving is that described second active pull-up circuit is made up of the 18th PMOS, described 3rd active negative
Carry circuit to be made up of the 19th PMOS.
The source electrode of described 18th PMOS and the source electrode of described 19th PMOS all connect supply voltage.
The grid of described 18th PMOS and drain electrode connect the grid and the described 16th of described 19th PMOS
The drain electrode of NMOS tube.
The drain electrode of described 19th PMOS connects the drain electrode of described 17th NMOS tube.
Further improving and be, the source electrode of the 20th PMOS connects supply voltage, drain electrode connects described 18th PMOS
The grid of pipe, the grid of described 20th PMOS connects the first control signal.
Voltage buffer amplifier of the present invention is by arranging adaptive circuit, it is possible to the working condition automatically according to circuit is adaptive
Size that first electric current of the control main body amplifying circuit answered is heavy and thus control the operating current size of main body amplifying circuit, electricity
Pressure buffer amplifier voltage of the positive inverting input of main body amplifying circuit before stable can not wait, and adaptive circuit can be
First electric current sinks the bigger electric current of mirror image, it is thus possible to improve the Slew Rate of voltage buffer amplifier, improve voltage buffer amplifier
Set up speed, the stabilization time of minimizing voltage buffer amplifier.After voltage buffer amplifier is stably, adaptive circuit can
It is that the first electric current sinks the relatively low electric current of mirror image, it is thus possible to reduce circuit power consumption；Improve so this invention removes in prior art
Circuit sets up speed needs larger current to reduce circuit power consumption and need the contradiction between smaller current, it is thus possible to realize carrying simultaneously
Height is set up speed and reduces power consumption.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the circuit diagram of first embodiment of the invention；
Fig. 2 is the current diagram that first of circuit shown in Fig. 1 sets up process；
Fig. 3 is the current diagram that second of circuit shown in Fig. 1 sets up process；
Fig. 4 is the circuit diagram of second embodiment of the invention；
Fig. 5 is the application drawing of second embodiment of the invention.
Detailed description of the invention
As it is shown in figure 1, be the circuit diagram of first embodiment of the invention, first embodiment of the invention voltage buffer amplifier
101 include: main body amplifying circuit 102 and adaptive circuit 103.
The operating current size of described main body amplifying circuit 102 is determined by the first electric current is heavy.
Described adaptive circuit 103 provides image current and according to described main body amplifying circuit for described first electric current is heavy
The duty of 102 is automatically adjusted the size of current that described first electric current is heavy.
When the normal phase input end of described main body amplifying circuit 102 and the voltage of inverting input are equal, described self adaptation
Circuit 103 makes described first electric current, and heavy electric current is the first value.
When the normal phase input end of described main body amplifying circuit 102 and the voltage of inverting input are unequal, described adaptive
Heavy electric current is the second value to answer circuit 103 to make described first electric current.
Described first value, less than described second value, reduces the merit of described voltage buffer amplifier by the first less value
Consumption；Improve the outfan charge-discharge velocity of described voltage buffer amplifier by bigger described second value thus improve pendulum
Rate.
In first embodiment of the invention, described adaptive circuit 103 includes that the first differential amplifier circuit and the second difference are put
Big circuit.
The normal phase input end of described first differential amplifier circuit, the normal phase input end of described second differential amplifier circuit and institute
The normal phase input end stating main body amplifying circuit 102 is connected and meets positive phase input signal VIP, described first differential amplifier circuit anti-
Phase input, the inverting input of described second differential amplifier circuit and the inverting input phase of described main body amplifying circuit 102
Connect and meet rp input signal VIN.
First difference inverted path of described first differential amplifier circuit and the second of described second differential amplifier circuit poor
The bottom dividing positive phase path is all connected to the second electric current and sinks.
The first positive phase path of difference of described first differential amplifier circuit and the second of described second differential amplifier circuit poor
The bottom of point inverted path is all connected to the 3rd electric current and sinks.
The top of the described second positive phase path of difference and described second difference inverted path all connects same first active
Load circuit.
The electric current of described first active pull-up circuit is mirrored to described first electric current by the first mirror image circuit and sinks.
Described second electric current is heavy and described 3rd electric current heavy mirror image and size of current are all the 3rd value each other.
When the normal phase input end of described main body amplifying circuit 102 and the voltage of inverting input are equal, described first poor
N times of the electric current that electric current is the described second positive phase path of difference of point inverted path, the electric current of the described first positive phase path of difference
For N times of the electric current of described second difference inverted path, N is more than 1, and the size of current of described first active pull-up circuit is described
3rd value is multiplied by 2/ (N+1), and described first active pull-up circuit is that described first electric current sinks mirror image and goes out the electricity that size is the first value
Stream.
When the normal phase input end of described main body amplifying circuit 102 and the voltage of inverting input are unequal, described first
The positive phase path of difference and described first difference inverted path there is the 3rd value described in an electric current convergence 0, another electric current convergence,
The described second positive phase path of difference and described second difference inverted path have an electric current convergence 0, another electric current convergence institute
Stating the 3rd value, the 3rd value described in the size of current convergence of described first active pull-up circuit, described first active pull-up circuit is
Described first electric current sinks mirror image and goes out the electric current that size is the second value.
Preferably, described first difference inverted path is made up of the first NMOS tube M1, the described first positive phase path of difference by
Second NMOS tube M2 composition, described second difference inverted path is made up of the 3rd NMOS tube M3, the described second positive phase path of difference
It is made up of the 4th NMOS tube M4；Described first NMOS tube M1 and described second NMOS tube M2 equal sized, described 3rd NMOS
Pipe M3 and described 4th NMOS tube M4 equal sized, the breadth length ratio of the raceway groove of described first NMOS tube M1 is described 3rd NMOS
N times of the breadth length ratio of the raceway groove of pipe M3.
The grid of described first NMOS tube M1 is the inverting input of described first differential amplifier circuit, described 2nd NMOS
The grid of pipe M2 is the normal phase input end of described first differential amplifier circuit, and the grid of described 3rd NMOS tube M3 is described second
The inverting input of differential amplifier circuit, the positive that grid is described second differential amplifier circuit of described 4th NMOS tube M4 is defeated
Enter end.
Described second electric current is heavy to be made up of the 5th NMOS tube M5, and described 3rd electric current is heavy to be made up of the 6th NMOS tube M6.
The source electrode of described 5th NMOS tube M5 and source electrode all ground connection GND of described 6th NMOS tube M6.
The drain electrode of described 5th NMOS tube M5 connects the source electrode of described first NMOS tube M1 and described 4th NMOS tube M4
Source electrode.
The drain electrode of described 6th NMOS tube M6 connects the source electrode of described second NMOS tube M2 and described 3rd NMOS tube M3
Source electrode.
The grid of described 5th NMOS tube M5 and the grid of described 6th NMOS tube M6 are all connected to the second mirror image circuit, institute
State heavy the sinking with described 3rd electric current of the second electric current all to be obtained by described second mirror image circuit mirror image.
It is described that described second mirror image circuit includes that the 7th NMOS tube M7, the grid of described 7th NMOS tube M7 and source electrode connect
The grid of the 5th NMOS tube M5 and the grid of described 6th NMOS tube M6, the source ground GND of described 7th NMOS tube M7, first
Current source IDC is connected to the source electrode of described 7th NMOS tube M7 and provides electric current for described second mirror image circuit.
Described first active pull-up circuit is made up of the tenth PMOS M10, and the source electrode of described tenth PMOS M10 connects electricity
Source voltage VDD, the grid of described tenth PMOS M10 and drain electrode all connect the drain electrode of described 3rd NMOS tube M3.
State the first mirror image circuit to be made up of the 11st PMOS M11 and the 12nd NMOS tube M12, described first electric current heavy by
13rd NMOS tube M13 composition.
The grid of described 11st PMOS M11 connects the grid of described tenth PMOS M10, described 11st PMOS
The source electrode of M11 connects supply voltage VDD, and the drain electrode of described 11st PMOS M11 connects the leakage of described 12nd NMOS tube M12
Pole and grid and the grid of described 13rd NMOS tube M13, the source electrode and the described 13rd of described 12nd NMOS tube M12
The source electrode of NMOS tube M13 all ground connection GND.
First resistance R1 is connected between drain electrode and the supply voltage VDD of described first NMOS tube M1 as described first
The load of NMOS tube M1, the second resistance R2 is connected between drain electrode and the supply voltage VDD of described second NMOS tube M2 as institute
State the load of the second NMOS tube M2.
Described main body amplifying circuit 102 includes by the 16th NMOS tube M16 and the 17th NMOS tube M17, the described 16th
The source electrode of NMOS tube M16 and the source electrode of described 17th NMOS tube M17 all connect the heavy i.e. connection the 13rd of described first electric current
The drain electrode of NMOS tube M13.
The drain electrode of described 16th NMOS tube M16 is connected to supply voltage VDD by the second active pull-up circuit；Described
The drain electrode of 17 NMOS tube M17 is connected to supply voltage VDD by the 3rd active pull-up circuit.
The grid of described 16th NMOS tube M16 is normal phase input end, and the grid of described 17th NMOS tube M17 is anti-phase
Input；The drain electrode of described 17th NMOS tube M17 is as the outfan of voltage buffer amplifier.
Described second active pull-up circuit is made up of the 18th PMOS M18, and described 3rd active pull-up circuit is by the tenth
Nine PMOS M19 compositions.
The source electrode of described 18th PMOS M18 and the source electrode of described 19th PMOS M19 all connect supply voltage
VDD。
The grid of described 18th PMOS M18 and drain electrode connect the grid of described 19th PMOS M19 and described
The drain electrode of the 16th NMOS tube M16.
The drain electrode of described 19th PMOS M19 connects the drain electrode of described 17th NMOS tube M17.
Understanding as shown in Figure 1, when the voltage buffer amplifier steady operation of first embodiment of the invention, now positive is defeated
Enter signal VIP and rp input signal VIN equal in magnitude, the electricity of described first the most described first NMOS tube M1 of difference inverted path
N times of the electric current that stream is described second the most described 4th NMOS tube M4 of the positive phase path of difference, the described first positive phase path of difference is i.e.
The electric current of the second NMOS tube M2 is N times of the electric current of described second the most described 3rd NMOS tube M3 of difference inverted path, described
The size of current of one active pull-up circuit that is the tenth NMOS tube M10 is to have described 4th NMOS tube M4 and the institute of small current value
Stating the superposition of the electric current of the 3rd NMOS tube M3, be multiplied by 2/ (N+1) for described 3rd value, described first active pull-up circuit is described
First electric current sinks mirror image and goes out the electric current that size is the first value, so now the first electric current sinks and has less electric current, this electric current is put down
Separately flowing into the 16th NMOS tube M16 and the 17th NMOS tube M17 the most afterwards, this can reduce power consumption when circuit stability.
During voltage buffer amplifier instability, this has two kinds of situations:
As in figure 2 it is shown, be first of circuit shown in Fig. 1 current diagram of setting up process；The first situation is that positive is defeated
Entering the value value more than rp input signal VIN of signal VIP, now the second NMOS tube M2 and the 4th NMOS tube M4 have bigger electricity
Stream, the electric current of the first NMOS tube M1 and the 3rd NMOS tube M3 levels off to 0, and the electric current of the 6th NMOS tube M6 is flowed into second substantially
In NMOS tube M2, the electric current of the 5th NMOS tube M5 is substantially flowed in the 4th NMOS tube M4 and and then is flowed into the tenth PMOS
In M10, and being mirrored in the 13rd NMOS tube M13 by the 11st NMOS tube M11 and the 12nd NMOS tube M12；16th
16th NMOS tube M16 conducting in NMOS tube M16 and the 17th NMOS tube M17, and the electric current of the 17th NMOS tube M17 is close to 0,
The electric current of the 13rd NMOS tube M13 flows through the 16th NMOS tube M16 and the 18th NMOS tube M18 and is mirrored to the 19th NMOS tube
Realize after M19 inverting input is charged, so that rp input signal VINN fast approaching positive phase input signal VIP, thus
Output signal VOUT fast and stable can be made, improve Slew Rate, reduce and set up the time.
As it is shown on figure 3, be second of circuit shown in Fig. 1 current diagram of setting up process；The first situation is that positive is defeated
Enter the value value less than rp input signal VIN of signal VIP, now the second NMOS tube M2 and the electric current convergence of the 4th NMOS tube M4
In 0, the first NMOS tube M1 and the 3rd NMOS tube M3 have larger current, and the electric current of the 5th NMOS tube M5 is flowed into first substantially
In NMOS tube M1, the electric current of the 6th NMOS tube M6 is substantially flowed in the 3rd NMOS tube M3 and and then is flowed into the tenth PMOS
In M10, and being mirrored in the 13rd NMOS tube M13 by the 11st NMOS tube M11 and the 12nd NMOS tube M12；16th
In NMOS tube M16 and the 17th NMOS tube M17, the electric current of the 16th NMOS tube M16 is close to 0, and the 17th NMOS tube M17 conducting,
The electric current of the 13rd NMOS tube M13 realizes after flowing through the 17th NMOS tube M17 discharging inverting input, so that anti-phase input
Signal VINN fast approaching positive phase input signal VIP, it is thus possible to make output signal VOUT fast and stable, improves Slew Rate, and reduction is built
Between immediately.
As shown in Figure 4, being the circuit diagram of second embodiment of the invention voltage buffer amplifier 101a, the present invention second implements
Example voltage buffer amplifier 101a is to do to obtain further, specifically on the basis of first embodiment voltage buffer amplifier 101
For, second embodiment of the invention also includes:
Described first current source IDC is connected to the source electrode of described 7th NMOS tube M7 by the 8th NMOS tube M8, and the 9th
The drain electrode of NMOS tube connects the grid of described 7th NMOS tube M7, the source ground GND of described 9th NMOS tube M9；Described 8th
The grid of NMOS tube M8 connects the first control signal PU, and the grid of described 9th NMOS tube M9 connects the second control signal PD.
The source electrode of the 14th PMOS M14 connects supply voltage VDD, the grid of drain electrode described tenth PMOS M10 of connection,
The grid of described 14th PMOS M14 connects the first control signal PU.
The drain electrode of the 15th NMOS tube M15 connects the grid of described 13rd NMOS tube M13, described 15th NMOS tube
The source ground GND of M15, the grid of described 15th NMOS tube M15 connects the second control signal PD.
The source electrode of the 20th PMOS M20 connects supply voltage VDD, the grid of drain electrode described 18th PMOS M18 of connection
Pole, the grid of described 20th PMOS M20 connects the first control signal PU.
Described first control signal PU is high level and described voltage delays time described second control signal PD is low level
Rushing amplifier operation, described first control signal PU is low level and described electricity time described second control signal PD is high level
Pressure buffer amplifier quits work.
If Fig. 5 is the application drawing of second embodiment of the invention, resistance R3 and R4 carries out dividing potential drop to supply voltage VDD and obtains defeated
Enter voltage VCM be input to the normal phase input end of voltage buffer amplifier 101a i.e.+end, the source and drain of PMOS M21 is connected to resistance
For controlling top and the connection of supply voltage VDD of resistance R3 between top and the supply voltage VDD of R3；PMOS M22 is even
It is connected between the bottom of resistance R4 and ground GND the bottom for controlling resistance R4 and the connection of ground GND, the grid of PMOS M21
Connecting the second control signal PD, the grid of PMOS M22 connects described first control signal PU.Voltage buffer amplifier 101a's
Outfan be connected to inverting input i.e.-end namely output signal VOUT connect rp input signal VIN.Output signal VOUT is even
Receive load circuit 102.Voltage buffer amplifier 101a is connected into unit gain form, when described first control signal PU is high electricity
Flat, when the second control signal PD is low level, voltage buffer amplifier 101a starts working, and makes output voltage VO UT follow input
Voltage VCM.
When the first control signal PU is low level, and the second control signal PD is high level, voltage buffer amplifier 101a
Quit work.Now load circuit 102 may change the magnitude of voltage i.e. value of output voltage VO UT of outfan.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, and these also should
It is considered as protection scope of the present invention.
Claims (13)
1. a voltage buffer amplifier, it is characterised in that including: main body amplifying circuit and adaptive circuit；
The operating current size of described main body amplifying circuit is determined by the first electric current is heavy；
Described adaptive circuit sinks for described first electric current provides image current the work shape according to described main body amplifying circuit
State is automatically adjusted the size of current that described first electric current is heavy；
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are equal, described adaptive circuit makes institute
The electric current stating the first electric current heavy is the first value；
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are unequal, described adaptive circuit makes
The electric current that described first electric current is heavy is the second value；
Described first value, less than described second value, reduces the power consumption of described voltage buffer amplifier by the first less value；
Improve the outfan charge-discharge velocity of described voltage buffer amplifier by bigger described second value thus improve Slew Rate.
2. voltage buffer amplifier as claimed in claim 1, it is characterised in that: described adaptive circuit includes the first differential amplification
Circuit and the second differential amplifier circuit；
The normal phase input end of described first differential amplifier circuit, the normal phase input end of described second differential amplifier circuit and described master
The normal phase input end of body amplifying circuit is connected, the inverting input of described first differential amplifier circuit, described second differential amplification
The inverting input of circuit is connected with the inverting input of described main body amplifying circuit；
First difference inverted path of described first differential amplifier circuit and the second difference of described second differential amplifier circuit are just
The bottom of phase path is all connected to the second electric current and sinks；
The first positive phase path of difference of described first differential amplifier circuit and the second difference of described second differential amplifier circuit are anti-
The bottom of phase path is all connected to the 3rd electric current and sinks；
The top of the described second positive phase path of difference and described second difference inverted path all connects same first active load
Circuit；
The electric current of described first active pull-up circuit is mirrored to described first electric current by the first mirror image circuit and sinks；
Described second electric current is heavy and described 3rd electric current heavy mirror image and size of current are all the 3rd value each other；
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are equal, the described first anti-phase road of difference
The electric current in footpath is N times of the electric current of the described second positive phase path of difference, and the electric current of the described first positive phase path of difference is described
N times of the electric current of two difference inverted path, N is more than 1, and the size of current of described first active pull-up circuit is that described 3rd value is taken advantage of
With 2/ (N+1), described first active pull-up circuit is that described first electric current sinks mirror image and goes out the electric current that size is the first value；
When the normal phase input end of described main body amplifying circuit and the voltage of inverting input are unequal, described first difference positive
Path and described first difference inverted path have the 3rd value described in an electric current convergence 0, another electric current convergence, described second
The positive phase path of difference and described second difference inverted path there is the 3rd value described in an electric current convergence 0, another electric current convergence,
3rd value described in the size of current convergence of described first active pull-up circuit, described first active pull-up circuit is described first electricity
The heavy mirror image of stream goes out the electric current that size is the second value.
3. voltage buffer amplifier as claimed in claim 2, it is characterised in that:
Described first difference inverted path is made up of the first NMOS tube, and the described first positive phase path of difference is by the second NMOS tube group
Becoming, described second difference inverted path is made up of the 3rd NMOS tube, and the described second positive phase path of difference is made up of the 4th NMOS tube；
Described first NMOS tube and described second NMOS tube equal sized, described 3rd NMOS tube and the size of described 4th NMOS tube
Equal, the breadth length ratio of the raceway groove of described first NMOS tube is N times of the breadth length ratio of the raceway groove of described 3rd NMOS tube；
The grid of described first NMOS tube is the inverting input of described first differential amplifier circuit, the grid of described second NMOS tube
The normal phase input end of the most described first differential amplifier circuit, the grid of described 3rd NMOS tube is described second differential amplification electricity
The inverting input on road, the normal phase input end that grid is described second differential amplifier circuit of described 4th NMOS tube.
4. voltage buffer amplifier as claimed in claim 3, it is characterised in that: described second electric current is heavy by the 5th NMOS tube group
Becoming, described 3rd electric current is heavy to be made up of the 6th NMOS tube；
The source electrode of described 5th NMOS tube and source electrode all ground connection of described 6th NMOS tube；
The drain electrode of described 5th NMOS tube connects source electrode and the source electrode of described 4th NMOS tube of described first NMOS tube；
The drain electrode of described 6th NMOS tube connects source electrode and the source electrode of described 3rd NMOS tube of described second NMOS tube；
The grid of described 5th NMOS tube and the grid of described 6th NMOS tube are all connected to the second mirror image circuit, described second electricity
Stream is heavy and described 3rd electric current is heavy is all obtained by described second mirror image circuit mirror image.
5. voltage buffer amplifier as claimed in claim 4, it is characterised in that: described second mirror image circuit includes the 7th NMOS
Pipe, the grid of described 7th NMOS tube and source electrode connect grid and the grid of described 6th NMOS tube of described 5th NMOS tube,
The source ground of described 7th NMOS tube, the first current source is connected to the source electrode of described 7th NMOS tube and is described second mirror image
Circuit provides electric current.
6. voltage buffer amplifier as claimed in claim 5, it is characterised in that: described first current source is by the 8th NMOS tube even
Receive the source electrode of described 7th NMOS tube, the 9th NMOS tube drain electrode connect the grid of described 7th NMOS tube, the described 9th
The source ground of NMOS tube；The grid of described 8th NMOS tube connects the first control signal, and the grid of described 9th NMOS tube is even
Connecing the second control signal, described first control signal is high level and described voltage time described second control signal is low level
Buffer amplifier works, and described first control signal is low level and described voltage time described second control signal is high level
Buffer amplifier quits work.
7. voltage buffer amplifier as claimed in claim 3, it is characterised in that: described first active pull-up circuit is by the tenth PMOS
Pipe forms, and the source electrode of described tenth PMOS connects supply voltage, the grid of described tenth PMOS and drain electrode and all connects described
The drain electrode of the 3rd NMOS tube.
8. voltage buffer amplifier as claimed in claim 7, it is characterised in that: described first mirror image circuit is by the 11st PMOS
With the 12nd NMOS tube composition, described first electric current is heavy to be made up of the 13rd NMOS tube；
The grid of described 11st PMOS connects the grid of described tenth PMOS, and the source electrode of described 11st PMOS connects
Supply voltage, the drain electrode of described 11st PMOS connects the drain and gate and the described 13rd of described 12nd NMOS tube
The grid of NMOS tube, the source electrode of described 12nd NMOS tube and source electrode all ground connection of described 13rd NMOS tube.
9. voltage buffer amplifier as claimed in claim 8, it is characterised in that: the source electrode of the 14th PMOS connects power supply electricity
Pressure, drain electrode connect the grid of described tenth PMOS, and the grid of described 14th PMOS connects the first control signal；
The grid of drain electrode described 13rd NMOS tube of connection of the 15th NMOS tube, the source ground of described 15th NMOS tube,
The grid of described 15th NMOS tube connects the second control signal；
Described first control signal is high level and described voltage buffer amplifier time described second control signal is low level
Work, described first control signal is low level and described voltage buffer amplifier time described second control signal is high level
Quit work.
10. voltage buffer amplifier as claimed in claim 3, it is characterised in that: the first resistance is connected to described first NMOS tube
Drain electrode and supply voltage between as the load of described first NMOS tube, the second resistance is connected to the leakage of described second NMOS tube
As the load of described second NMOS tube between pole and supply voltage.
11. as described in any claim in claim 1-10 voltage buffer amplifier, it is characterised in that: described main body amplify
Circuit includes by the 16th NMOS tube and the 17th NMOS tube, the source electrode of described 16th NMOS tube and described 17th NMOS tube
Source electrode all connect described first electric current sink；
The drain electrode of described 16th NMOS tube is connected to supply voltage by the second active pull-up circuit；Described 17th NMOS tube
Drain electrode be connected to supply voltage by the 3rd active pull-up circuit；
The grid of described 16th NMOS tube is normal phase input end, and the grid of described 17th NMOS tube is inverting input；Institute
State the drain electrode outfan as voltage buffer amplifier of the 17th NMOS tube.
12. voltage buffer amplifier as claimed in claim 11, it is characterised in that: described second active pull-up circuit is by the 18th
PMOS forms, and described 3rd active pull-up circuit is made up of the 19th PMOS；
The source electrode of described 18th PMOS and the source electrode of described 19th PMOS all connect supply voltage；
The grid of described 18th PMOS and drain electrode connect the grid of described 19th PMOS and described 16th NMOS
The drain electrode of pipe；
The drain electrode of described 19th PMOS connects the drain electrode of described 17th NMOS tube.
13. voltage buffer amplifier as claimed in claim 12, it is characterised in that:
The source electrode of the 20th PMOS connects supply voltage, draining connects the grid of described 18th PMOS, and the described 20th
The grid of PMOS connects the first control signal.
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| CN201610373501.3A CN106059503B (en) | 2016-05-31 | 2016-05-31 | Voltage buffer amplifier |
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| CN201610373501.3A CN106059503B (en) | 2016-05-31 | 2016-05-31 | Voltage buffer amplifier |
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| CN106059503B CN106059503B (en) | 2019-06-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109302173A (en) * | 2018-12-10 | 2019-02-01 | 上海艾为电子技术股份有限公司 | Input buffer |
| CN112737564A (en) * | 2020-12-25 | 2021-04-30 | 中国科学院微电子研究所 | Constant slew rate signal driving system |
| WO2022134042A1 (en) * | 2020-12-25 | 2022-06-30 | 中国科学院微电子研究所 | Signal driving system with constant slew rate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645658A (en) * | 2009-05-27 | 2010-02-10 | 北京中星微电子有限公司 | Flyback power converter and loop control method thereof |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN103259492A (en) * | 2013-05-28 | 2013-08-21 | 上海贝岭股份有限公司 | Video driver output amplifier circuit |
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2016
- 2016-05-31 CN CN201610373501.3A patent/CN106059503B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645658A (en) * | 2009-05-27 | 2010-02-10 | 北京中星微电子有限公司 | Flyback power converter and loop control method thereof |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN103259492A (en) * | 2013-05-28 | 2013-08-21 | 上海贝岭股份有限公司 | Video driver output amplifier circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109302173A (en) * | 2018-12-10 | 2019-02-01 | 上海艾为电子技术股份有限公司 | Input buffer |
| CN112737564A (en) * | 2020-12-25 | 2021-04-30 | 中国科学院微电子研究所 | Constant slew rate signal driving system |
| WO2022134042A1 (en) * | 2020-12-25 | 2022-06-30 | 中国科学院微电子研究所 | Signal driving system with constant slew rate |
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| CN106059503B (en) | 2019-06-11 |
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