CN208539883U - Input buffer and chip with it - Google Patents
Input buffer and chip with it Download PDFInfo
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- CN208539883U CN208539883U CN201821193871.XU CN201821193871U CN208539883U CN 208539883 U CN208539883 U CN 208539883U CN 201821193871 U CN201821193871 U CN 201821193871U CN 208539883 U CN208539883 U CN 208539883U
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Abstract
The utility model embodiment provides a kind of input buffer and the chip with it.Input buffer includes: the first buffer module, and the first buffer module is connect with input pin, and exports the first digital signal according to the voltage value and preset first voltage threshold value of input pin input；Second buffer module, the second buffer module are connect with input pin, and export the second digital signal and third digital signal according to the voltage value of input pin, preset second voltage threshold value, preset tertiary voltage threshold value；First buffer module and/or the second buffer module are according to the first digital signal, the second digital signal and third digital signal, determine the value of the first code bit and the second code bit in output state code, wherein, first voltage threshold value is between second voltage threshold value and tertiary voltage threshold value.The input buffer can export four kinds of logic states in the case where an input pin inputs.
Description
Technical field
The utility model embodiment is related to technical field of electricity more particularly to a kind of input buffer and the core with it
Piece.
Background technique
Input buffer is widely used in audio-frequency power amplifier, turns as basic module indispensable in integrated circuit
In parallel operation, radio frequency, sensor and power management chip.As shown in Figure 1, I2C address choice input buffer in the prior art,
When incoming level is higher than threshold voltage, output logic level becomes high from low；When incoming level is lower than threshold voltage, output
Logic level becomes low from height；The input buffer can only export two kinds of Different Logic states.
But as IC complexity increases, the input pin number needed is sharply increased, but with manufacturing process and
Encapsulation advanced optimizes, so that chip area reduces, for WLCSP (wafer chip level chip-scale package, Wafer Level
Chip Scale Packaging) etc. encapsulation for, provide total number of pins reducing instead so that the chip produced
Number of pin it is insufficient, input pin number deficiency.
By taking audio frequency power amplifier chip as an example, audio frequency power amplifier chip needs to be arranged a variety of different I2C register address, with control
Multiple chips realize the application scenarios of multichannel.This just needs multiple input pins to realize, because single pin can only obtain
Two kinds of logic states.And since pin resource is at full stretch, multiple pins can not be distributed as input pin, so that existing sound
Frequency power amplifier chips cannot satisfy the use demand.
Utility model content
In view of this, one of the technical issues of the utility model embodiment is solved be to provide a kind of input buffer and
With its chip, to overcome the logic state exported when input buffer only has an input pin in the prior art insufficient
The problem of.
The utility model embodiment provides a kind of input buffer comprising: the first buffer module, the first buffer module with
Input pin connection, and the first digital signal is exported according to the voltage value and preset first voltage threshold value of input pin input；
Second buffer module, the second buffer module are connect with input pin, and according to the voltage value of input pin, preset second voltage
Threshold value, preset tertiary voltage threshold value export the second digital signal and third digital signal；First buffer module and/or second slow
Die block according to the first digital signal, the second digital signal and third digital signal, determine in output state code the first code bit and
The value of second code bit, wherein first voltage threshold value is between second voltage threshold value and tertiary voltage threshold value.
Optionally, the first buffer module determines the value of the first code bit in output state code according to the first digital signal, second
Buffer module determines the second code bit in output state code according to the first digital signal, the second digital signal and third digital signal
Value.
Optionally, when the voltage value of the first digital signal instruction input pin is greater than first voltage threshold value, the first code bit
Value be first state value；When the voltage value of the first digital signal instruction input pin is less than first voltage threshold value, first yard
The value of position is the second state value.
Optionally, tertiary voltage threshold value is greater than second voltage threshold value, if the voltage of third digital signal instruction input pin
Value is greater than tertiary voltage threshold value, then the value of the second code bit is first state value；If the electricity of third digital signal instruction input pin
Pressure value is less than tertiary voltage threshold value and the voltage value of the first digital signal instruction input pin is greater than first voltage threshold value, then and the
The value of two code bits is the second state value；If the first digital signal indicate input pin voltage value be less than first voltage threshold value and
Second digital signal indicates that the voltage value of input pin is greater than second voltage threshold value, then the value of the second code bit is first state value；
If the second digital signal indicates that the voltage value of input pin is less than second voltage threshold value, the value of the second code bit is the second state
Value.
Optionally, the second buffer module includes comparing unit, and comparing unit is connect with input pin, is used for input pin
Voltage value respectively with second voltage threshold value and tertiary voltage threshold value comparison, and according to comparison result export the second digital signal and
Third digital signal.
Optionally, comparing unit includes the first comparing subunit, and the first comparing subunit is used to compare the electricity of input pin
Pressure value and second voltage threshold value export the second digital signal according to comparison result.
Optionally, the first comparing subunit includes the first NMOS tube and first voltage comparison circuit, the source of the first NMOS tube
Pole is connect with input pin, and grid is connect with first voltage comparison circuit, and drain electrode is for exporting the second digital signal.
Optionally, the first comparison circuit includes: the first current source and the second current source, the first current source and the second current source
It is arranged in parallel；Second NMOS tube, the drain and gate of the second NMOS tube are connect with the first current source and the second current source, and the
Two current sources are connect by the first control switch with the second NMOS tube, and the source electrode of the second NMOS tube is grounded by first resistor.
Optionally, comparing unit includes the second comparing subunit, and the second comparing subunit is used to compare the electricity of input pin
Pressure value and tertiary voltage threshold value export third digital signal according to comparison result.
Optionally, the second comparing subunit includes the first PMOS tube and second voltage comparison circuit, the source of the first PMOS tube
Pole is connect with input pin, and grid is connect with second voltage comparison circuit, is drained for exporting third digital signal.
Optionally, second voltage comparison circuit includes: third current source and the 4th current source, third current source and the 4th electricity
Stream source is arranged in parallel；Second PMOS tube, the drain and gate of the second PMOS tube are connect with third current source and the 4th current source,
And the 4th current source connect with the second PMOS tube by the second control switch, the source electrode of the second PMOS tube by 3rd resistor with it is electric
Source connection.
Optionally, the second buffer module further includes Logical processing unit, and Logical processing unit is used to be believed according to the first number
Number, the second digital signal and third digital signal, determine the value of the second code bit.
Optionally, Logical processing unit includes: the first NAND gate, and the first NAND gate is according to the first digital signal, the second number
Word signal and third digital signal output the first processing signal；Second NAND gate, the second NAND gate is according to the first digital signal
The inversion signal of inversion signal, the second digital signal and third digital signal exports second processing signal；Third NAND gate, third
NAND gate determines the value of the second code bit according to the first processing signal and second processing signal.
Another aspect according to the present utility model provides a kind of chip comprising above-mentioned input buffer.
By above technical scheme as it can be seen that the input pin of the utility model embodiment input buffer is buffered with first respectively
Module is connected with the second buffer module, and the first buffer module is according to the voltage value and first voltage threshold value of input pin output first
Whether digital signal, the voltage value which is used to indicate input pin are greater than first voltage threshold value, thus according to
First digital signal determines the value of the first code bit in output state code.Second buffer module according to the voltage value of input pin,
Second voltage threshold value and tertiary voltage threshold value export the second digital signal and third digital signal, and second digital signal is for referring to
Show whether the voltage value of input pin is greater than second voltage threshold value, the voltage value that third digital signal is used to indicate input pin is
It is no to be greater than tertiary voltage threshold value.Output shape can be determined according to the first digital signal, the second digital signal and third digital signal
Second code bit in state code passes through an input pin to export four kinds of states in conjunction with the first code bit and the second code bit to realize
Four kinds of states are exported, to save pin, and are satisfied the use demand.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is that some embodiments recorded in the utility model embodiment for those of ordinary skill in the art can also be according to this
A little attached drawings obtain other attached drawings.
Fig. 1 is the structural schematic diagram of the input buffer of the utility model embodiment；
Fig. 2 is that the chip of the utility model embodiment powers on the level change signal of rear VDD, PORN and PORN_DELAY
Figure.
Specific embodiment
Certainly, any technical solution for implementing the utility model embodiment must be not necessarily required to that reaching above simultaneously owns
Advantage.
In order to make those skilled in the art more fully understand the technical scheme in the embodiment of the utility model, below in conjunction with this
Attached drawing in utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, shows
So, described embodiment is only the utility model embodiment a part of the embodiment, instead of all the embodiments.Based on this reality
With the embodiment in new embodiment, this is all should belong in those of ordinary skill in the art's every other embodiment obtained
The range of utility model embodiment protection.
Further illustrate that the utility model embodiment implements below with reference to the utility model embodiment attached drawing.
As shown in Figure 1, embodiment according to the present utility model, input buffer includes that the first buffer module 10 and second is slow
Die block 20, the first buffer module 10 are connect with input pin, and the voltage value and preset first inputted according to input pin
Voltage threshold exports the first digital signal；Second buffer module 20 is connect with input pin, and according to the voltage value of input pin,
Preset second voltage threshold value, preset tertiary voltage threshold value export the second digital signal and third digital signal；First buffering
Module 10 and/or the second buffer module 20 determine output according to the first digital signal, the second digital signal and third digital signal
The value of the first code bit and the second code bit in status code, wherein first voltage threshold value is between second voltage threshold value and tertiary voltage threshold
Between value.
The input pin (AD pin shown in Fig. 1) of the input buffer is buffered with the first buffer module 10 and second respectively
Module 20 connects, and the first buffer module 10 exports the first digital signal according to the voltage value and first voltage threshold value of input pin,
Whether the voltage value that first digital signal is used to indicate input pin is greater than first voltage threshold value, to be believed according to the first number
Number determine output state code in the first code bit value.Voltage value of second buffer module 20 according to input pin, second voltage
Threshold value and tertiary voltage threshold value export the second digital signal and third digital signal, second digital signal are used to indicate input and draw
Whether the voltage value of foot is greater than second voltage threshold value, and whether the voltage value that third digital signal is used to indicate input pin is greater than
Three voltage thresholds.It can be determined in output state code according to the first digital signal, the second digital signal and third digital signal
Two code bits export four kinds by an input pin to realize to export four kinds of states in conjunction with the first code bit and the second code bit
The purpose of state to save pin, and satisfies the use demand.
It should be noted that when the input signal of the input pin of input buffer from high level becomes low level and by low
When level becomes high level, the value of first voltage threshold value, second voltage threshold value and tertiary voltage threshold value can have any different, to guarantee
Signal stabilization.By taking the first buffer module 10 as an example, when the input voltage value of input pin is lower by height, first voltage threshold value
1/2VDD can be slightly below, conversely, first voltage threshold value can be slightly above 1/ when the input voltage value of input pin is by low get higher
2VDD.Similarly, in order to guarantee that signal stabilization, second voltage threshold value and tertiary voltage threshold value can be in voltage environment difference
It is different value, is also possible to identical value.
In the present embodiment, the first buffer cell determines the first code bit in output state code according to the first digital signal
Value, the second buffer cell determine in output state code the according to the first digital signal, the second digital signal and third digital signal
The value of two code bits.Circuit structure can so more simplified, logical process is rapider, and fault-tolerance is more preferable.
Certainly, in other embodiments, the first code bit and can be determined by the first buffer cell according to different requirements,
The value of two code bits perhaps by the second buffer cell determines the value of the first code bit and the second code bit or by its of input buffer
The value of his structure determination the first code bit and the second code bit, the present embodiment are not construed as limiting this.
About the value of the first code bit, in the present embodiment, when the voltage value of the first digital signal instruction input pin is greater than
When first voltage threshold value (first voltage threshold value can be the value higher than 1/2VDD), the value of the first code bit is first state value, example
Such as 1.In other words, in such cases, the first code bit is high level state.
When the voltage value of the first digital signal instruction input pin is less than first voltage threshold value, (first voltage threshold value can be
Value lower than 1/2VDD) when, the value of the first code bit is the second state value, such as 0.In other words, in such cases, the first code bit
For low level state.
About the value of the second code bit, in the present embodiment, carried out so that tertiary voltage threshold value is greater than second voltage threshold value as an example
Explanation.Certainly, in other embodiments, second voltage threshold value can be greater than tertiary voltage threshold value.
If third digital signal indicates the voltage value of input pin and is greater than tertiary voltage threshold value, the value of the second code bit is the
One state value, such as 1.In other words, in such cases, the second code bit is high level state.
If third digital signal indicates that the voltage value of input pin is less than tertiary voltage threshold value and the first digital signal indicates
The voltage value of input pin is greater than first voltage threshold value, then the value of the second code bit is the second state value, such as 0.In other words, this
In the case of kind, the second code bit is low level state.
If the first digital signal indicates that the voltage value of input pin is less than first voltage threshold value and the second digital signal indicates
The voltage value of input pin is greater than second voltage threshold value, then the value of the second code bit is first state value such as 1.In other words, this
In the case of kind, the second code bit is high level state.
If the second digital signal indicates the voltage value of input pin and is less than second voltage threshold value, the value of the second code bit is the
Two-state value, such as 0.In other words, in such cases, the second code bit is low high level state.
As shown in Figure 1, in the present embodiment, the first buffer module 10 includes NMOS tube MN1, NMOS tube MN2, NMOS tube
MN3, PMOS tube MP1, PMOS tube MP2, PMOS tube MP3, phase inverter INV1, phase inverter INV2, the lock of phase inverter INV3 and first
Storage.
It certainly, is only the structure for illustrating a kind of feasible first buffer module 10 in the present embodiment, in other embodiments
In, the first buffer module 10 can be other structures appropriate, as long as it can ensure that according to the voltage value of input pin and first
Voltage threshold exports the first digital signal.
The first buffer module 10 is described in detail below:
NMOS tube MN1, NMOS tube MN2, PMOS tube MP1 and PMOS tube MP2 grid connect with input pin.PMOS tube
The source electrode of MP1 connects to power supply, and drain electrode is connect with the source electrode of PMOS tube MP2.The drain electrode of PMOS tube MP2 and the leakage of NMOS tube MN2
Pole connection.The source electrode of NMOS tube MN2 is connect with the drain electrode of NMOS tube MN1, and NMOS tube MN1 is source electrode ground connection.
In addition, the source electrode of PMOS tube MP3 is connected between the drain electrode of PMOS tube MP1 and the source electrode of PMOS tube MP2, PMOS tube
The grounded drain of MP3, the grid of PMOS tube MP3 are connected between the drain electrode of PMOS tube MP2 and the drain electrode of NMOS tube MN2.
The source electrode of NMOS tube MN3 is connected between the drain electrode of source electrode and NMOS tube MN1 of NMOS tube MN2, NMOS tube MN3's
Drain electrode connects power supply, and the grid of NMOS tube MN3 is connected between the drain electrode of PMOS tube MP2 and the drain electrode of NMOS tube MN2.
Phase inverter INV1, phase inverter INV2 and phase inverter INV3 are sequentially connected, and the input terminal of phase inverter INV1 is connected to
Between the drain electrode of PMOS tube MP2 and the drain electrode of NMOS tube MN2, the output end of phase inverter INV3 is used to export the first digital signal,
And it is connect with the end D of the first latch.The end clk of first latch connects first control signal PORN_DELAY.First latches
Device is used to carry out signal latch according to the control of first control signal.
When the voltage value of input pin is greater than first voltage threshold value, PMOS tube MP1 and PMOS tube MP2 conducting, NMOS tube
MN1 and NOMS pipe MN2 is turned off, and is exported low level in Fig. 1 at Vo, is exported high level, the first digital signal out at phase inverter INV2
<1>output at is high level, exports high level at the ADDR exported after the first latches<1>.
When the voltage value of input pin is less than first voltage threshold value, PMOS tube MP1 and PMOS tube MP2 shutdown conducting,
NMOS tube MN1 and NOMS pipe MN2 is connected, and exports high level in Fig. 1 at Vo, and low level, the first number are exported at phase inverter INV2
Output at signal out<1>is low level, exports low level at the ADDR exported after the first latches<1>.
PMOS tube MP3 and NMOS tube MN3 makes it slightly larger than 1/2VDD or is slightly less than 1/ for controlling first voltage threshold value
2VDD avoids signal recurrent fluctuations to maintain signal stabilization.
The second buffer module 20 is described in detail below:
In the present embodiment, the second buffer module 20 includes comparing unit, and comparing unit is connect with input pin, and being used for will
The voltage value of input pin respectively with second voltage threshold value and tertiary voltage threshold value comparison, and according to comparison result output second number
Word signal and third digital signal, thus the value of the second code bit of control.
In the present embodiment, comparing unit includes the first comparing subunit 21, and the first comparing unit 21 is for comparing input
The voltage value and second voltage threshold value of pin export the second digital signal according to comparison result.
It should be noted that the first comparing subunit 21 can be any suitable structure, draw as long as input can be compared
The voltage value and second voltage threshold value of foot.
In a kind of feasible pattern, the first comparing subunit 21 includes the first NMOS tube (M3 is denoted as in figure) and the first electricity
Comparison circuit is pressed, the source electrode of the first NMOS tube M3 is connect with input pin, and grid is connect with first voltage comparison circuit, and drain electrode is used
In exporting the second digital signal.
Optionally, the drain electrode of the first NMOS tube M3 can be connect with the input of first comparator P1, so that first comparator
P1 compares the drain voltage and second voltage threshold value of the first NMOS tube M3, thus the second digital signal of output.
First voltage comparison circuit may include the first current source IP1, the second current source IP2 and the second NMOS tube (figure
In be denoted as M5) etc..In the present embodiment, first voltage comparison circuit further includes NMOS tube M4, PMOS tube M1 and PMOS tube M2
Deng.
In the present embodiment, the first current source IP1 and the second current source IP2 are arranged in parallel.Second current source IP2 output
The ratio of electric current and the electric current of the first current source IP1 output is 10:1.
The drain and gate of second NMOS tube M5 is connect with the first current source IP1 and the second current source IP2, and the second electricity
Stream source IP 2 is connect by the first control switch with the second NMOS tube M5, and the source electrode of the second NMOS tube M5 is connect by first resistor R1
Ground.
By the way that the first control switch is arranged, it can control whether the second current source IP2 connect with the second NMOS tube M5, in turn
The second current source IP2 is closed, when not needed to save the energy.
As shown in Figure 1, in the present embodiment, the first control switch is PMOS tube, the source electrode of the PMOS tube and the second electric current
Source IP 2 connects, and the drain electrode of the PMOS tube is connect with the drain electrode of the second NMOS tube M5, grid connection the first control letter of the PMOS tube
Number PORN_DELAY.It can control the on-off of the first control switch by the variation of first control signal, thus the second electricity of control
Whether stream source IP 2 works.
The grid of the NMOS tube M4 of the first voltage comparison circuit is connect with the grid of the second NMOS tube M5.NMOS tube M4's
Source electrode by second resistance with meeting R2.The grid of the drain electrode of NMOS tube M4 and the grid of PMOS tube M2 and drain electrode and PMOS tube M1
Pole connection.The source electrode of PMOS tube M2 connects to power supply.The drain electrode of PMOS tube M1 is connect with the drain electrode of the first NMOS tube M3.PMOS tube
The source electrode of M1 connects power supply.
Comparing unit includes the second comparing subunit 22, and the second comparing subunit 22 is used to compare the voltage value of input pin
And tertiary voltage threshold value, third digital signal is exported according to comparison result.
In the present embodiment, the second comparing subunit 22 include the first PMOS tube M6 and second voltage comparison circuit, first
The source electrode of PMOS tube M6 is connect with input pin AD, and grid is connect with second voltage comparison circuit, is drained for exporting third number
Word signal.
It should be noted that the structure of second voltage comparison circuit can be any suitable structure, as long as can compare
The voltage value and third digital signal of input pin.
In the present embodiment, second voltage comparison circuit includes third current source IN1, the 4th current source IN2, the 2nd PMOS
Pipe M8, PMOS tube M7, NMOS tube M9 and NMOS tube M10, the second amplifier P2 and phase inverter INV4 etc..
Wherein, third current source IN1 and the 4th current source IN2 are arranged in parallel.The drain and gate of second PMOS tube M8 is equal
It is connect with third current source IN1 and the 4th current source IN2, and the 4th current source IN2 passes through the second control switch and the 2nd PMOS
Pipe M8 connection, the source electrode of the second PMOS tube M8 are connected to power supply by 3rd resistor R3.
The effect of second control switch is similar with the effect of the first control switch, and the second control switch for controlling when needed
The 4th current source IN2 conducting is made, is turned it off when not needed, to save the energy.In the present embodiment, the second control switch is
NMOS tube switch.The grid of second control switch meets second control signal POR_DELAY, and second control signal is believed with the first control
Number reverse phase.The source electrode of second control switch meets the 4th current source IN2, and drain electrode is connect with the drain electrode of the second PMOS tube M8.
In the present embodiment, the grid of PMOS tube M7 is connect with the grid of the second PMOS tube M8, and the source electrode of PMOS tube M7
It is connected to power supply by the 4th resistance R4, grid, the leakage of the drain electrode of PMOS tube M7 and the grid of NMOS tube M9 and NMOS tube M10
Pole connection.
The source electrode of NMOS tube M9 is grounded, and drain electrode is connect with the drain electrode of the first PMOS tube M6.The source electrode of NMOS tube M10 is grounded.
The input of second comparator P2 is connect with the drain electrode of the first PMOS tube M6, and compares the drain electrode electricity of the first PMOS tube M6
Pressure and tertiary voltage threshold value export third digital signal according to comparison result.In addition, the output of the second comparator P2 is also and reverse phase
The input of device INV4 connects.
In the present embodiment, the second buffer module 20 further includes Logical processing unit 23, and Logical processing unit 23 is used for root
According to the first digital signal, the second digital signal and third digital signal, the value of the second code bit is determined.
Optionally, Logical processing unit 23 include the first NAND gate I1, the second NAND gate I2 and third NAND gate I3 and
Second latch.
Wherein, the first NAND gate I is exported at first according to the first digital signal, the second digital signal and third digital signal
Manage signal.
Second NAND gate I2 is anti-according to the inversion signal of the first digital signal, the second digital signal and third digital signal
Phase signals export second processing signal.
Third NAND gate I3 determines the value of the second code bit according to the first processing signal and second processing signal.
For connecting with the output of third NAND gate I3, the port clk connects first control signal for the port D of second latch,
To latch as needed to signal, guarantee the stability of output signal.
Four kinds of states of input buffer output are described in detail below as follows:
When input pin AD is directly grounded, if the first voltage threshold value of the first buffer cell be 1/2VDD (here for
Convenient for illustrating to be illustrated with it for 1/2VDD, in actual work according to level jump difference, PMOS tube MP3 and NMOS tube MN3
Can be adjusted to automatically slightly above 1/2VDD or slightly below 1/2VDD), then the voltage value of input pin is less than first voltage threshold
Value, the first digital signal out<1>are low level, i.e. the first code bit value is the second state value 0, and the output of phase inverter INV2 is denoted as
INV2 is high level.Since the first NMOS tube M3 is connect with input pin, so the source electrode of the first NMOS tube M3 is equivalent to ground connection.
Under the control of first control signal PORN_DELAY, the first current source IP1 and the second current source IP2 are both turned on.At this point, second
NMOS tube M5, NMOS tube M4, PMOS tube M1 and PMOS tube M2 are both turned on.In addition, in order to enable flowing through PMOS tube M1 and PMOS tube
The electric current of M2 is equal, and the breadth length ratio provided with NMOS tube M4 and the second NMOS tube M5 is equal, first resistor R1 and second resistance R2
Resistance value is equal, and has that the breadth length ratio of PMOS tube M1 and PMOS tube M2 are equal, according to the following calculation formula of the electric current of transistor:
I=1/2*u*Cox*W/L* (VGS-VTH)^2*(1+TVDS) --- formula 1
In formula:
U indicates the mobility of carrier in channel, and Cox indicates that the gate oxide capacitance of unit area, T indicate channel length
Modulation factor, VGS indicate grid voltage, VTHIndicate that the voltage threshold of on or off, VDS indicate that drain voltage, W/L indicate brilliant
The breadth length ratio of body pipe.
Since the grid voltage of the first NMOS tube M3 and NMOS tube M4 is identical with the current value flowed through, reference above-mentioned formula 1,
The electric current I for flowing through the first NMOS tube M3 is equal with the I for flowing through NMOS tube M4.Simultaneously as the source electrode of the first NMOS tube M3 is straight
Ground connection, so that the source voltage of the first NMOS tube M3 is equal to 0.And the source electrode of NMOS tube M4 is grounded by second resistance R2, institute
With the source voltage of NMOS tube M4 is greater than 0.So that the drain voltage of the first NMOS tube M3 is lower, less than first comparator P1's
Threshold voltage (i.e. second voltage threshold value), therefore, the first comparator P1 of first voltage comparison circuit exports the first digital signal
COMP1 is low level.
Since input pin AD is grounded, so the source electrode of the first PMOS tube M6 is directly grounded, the first PMOS tube M6 and NPMOS
Pipe M9 shutdown, and PMOS tube M7, the second PMOS tube M8, MMOS pipe M10 are connected, therefore, the COMP2 of the second comparator P2 output is
Low level, it is high level that the output of phase inverter INV4, which is denoted as the inversion signal that INV4 is COMP2,.
Therefore, the input of the first NAND gate I1 is respectively as follows: that out<1>is low level, COMP1 is low level and COMP2 is high
Level, then the output of the first NAND gate I1 is high level.
The input of second NAND gate I2 is respectively as follows: that COMP1 is low level, INV2 is high level, INV4 is low level, then and
The output of two NAND gate I2 is high level.
The output of third NAND gate I3 is low level, i.e. out<0>is low level.
Output state code ADDR<1>and ADDR<0>are as follows: 00.
Being arranged so that flowing through the electric current phase of the first NMOS tube M3 and NMOS tube M4 by above-mentioned parameter in the present embodiment
Deng, i.e. electric current likens to 1:1, still, in other embodiments, and it is also possible that the electric current of different metal-oxide-semiconductor is at other proportionate relationships,
It is gone to determine the level height that the first comparing subunit exports according to the proportionate relationship.
Similarly, when input pin is grounded by resistance R0, and the resistance value of resistance R0 is greater than second resistance R2.If first is slow
The first voltage threshold value of die block 10 is set as the half of power vd D, and PMOS tube MP1, PMOS tube MP2, PMOS tube MP3 are led at this time
Logical, Vo is high level, and therefore, after phase inverter INV1, phase inverter INV2 and phase inverter INV3 processing, out<1>is low electricity
Flat, INV2 is high level.
At this point, since resistance R0 is greater than second resistance R2, and due to the electricity of the first NMOS tube M3 and NMOS tube M4 flowed through
Flow valuve is identical, and the source voltage of the first NMOS tube M3 is greater than the source voltage of NMOS tube M4, so that the drain electrode of the first NMOS tube M3
Voltage becomes larger, and therefore, the first comparator P1 output COMP1 of the first comparing subunit 21 is high level.
And at this point, for the second comparing subunit 22, the first PMOS tube M6 and NMOS tube M9 cut-off, and PMOS tube
M7, the second PMOS tube M8, NMOS tube M10 conducting, therefore, the output COMP2 of the second comparing subunit are low level, and INV4 is height
Level.
Therefore, the input of the first NAND gate I1 are as follows: out<1>low level, COMP1 high level and COMP2 low level, output
For high level.The input of second NAND gate I2 is COMP1 high level, INV2 high level and INV4 high level, is exported as low level,
Further, the output of third NAND gate I3 is high level, i.e. out<0>is high level.
Output state code are as follows: 01.
Similarly, when input pin AD connects power supply by resistance R0, and the resistance value of resistance R0 is greater than second resistance R2, NMOS
Pipe MN1, NMOS tube MN2 conducting, Vo output are low level, and out<1>is high level, and INV2 is low level.
At this point, the first NMOS tube M3 source electrode is greater than it since the resistance value of resistance R0 is greater than the resistance value of second resistance R2
Grid voltage, since it is NMOS tube, so that the first NMOS tube M3 ends, and PMOS tube M1 is connected, so first comparator P1
Input voltage be greater than threshold voltage, therefore, the output COMP1 of the first comparing subunit is high level.
And at this point, for the second comparing subunit, since resistance R0 is greater than resistance R4, and the electric current flowed through is equal,
So that the value of the gate source voltage difference VGS of the first PMOS tube M6 is less than the value of the gate source voltage difference VGS on PMOS tube M7, so that conducting
NMOS tube M9 by the voltage pull-down of the input terminal of the second comparator P2, therefore, the output COMP2 of the second comparing subunit 22 is
Low level, INV4 are high level.
Therefore, the output of the first NAND gate I1 is high level, and the output of the second NAND gate I2 is high level, further, the
The output of three NAND gate I3 is low level, i.e. out<0>is low level.
Output state code are as follows: 10.
Similarly, when input pin directly connects power supply, NMOS tube MN1, NMOS tube MN2, PMOS tube MP3 conducting, Vo, which is exported, is
Low level, out<1>are high level.
Since input pin AD connects power supply, the source voltage of the first NMOS tube M3 is greater than grid voltage, the first NMOS tube M3
Cut-off, and PMOS tube M1 is connected, at this point, the output COMP1 of the first comparing subunit 21 is high level.
The source voltage of first PMOS tube M6 is supply voltage, and the value of the gate source voltage difference of the first PMOS tube M6 is greater than PMOS
The value of the gate source voltage difference of pipe M7 so that being high level at the link position of NMOS tube M9 and the first PMOS tube M6, and then makes the
The output COMP2 of two comparing subunits 22 is high level.
The output of first NAND gate device I1 is low level, and the output of the second NAND gate device I2 is high level, therefore, third with
The output of non-gate device I3 is high level, i.e. out<0>is high level.
Output state code are as follows: 11.
It can be seen that the output state code of the input buffer in the case of above-mentioned four kinds is table 1
| ADDR<1:0> | ||
| Input pin ground connection | 00 | MODE0 |
| Input pin passes through resistance eutral grounding | 01 | MODE1 |
| Input pin connects power supply by resistance | 10 | MODE2 |
| Input pin connects power supply | 11 | MODE3 |
Table 1
Different mode MODE can be set in different logic states.It should be noted that in table 1, the resistance value of resistance R0
It is the relationship that the breadth length ratio based on above-mentioned metal-oxide-semiconductor is 1:1 greater than second resistance R2, and when the breadth length ratio of above-mentioned metal-oxide-semiconductor is not 1:
When 1 relationship, resistance value is not greater than R1/ or R2 in above-mentioned table one, and in specific implementation, basic principle is can be according to upper
State the relationship of breadth length ratio relationship the adjustment resistance value and R1/ or R2 of metal-oxide-semiconductor.
The course of work of the input buffer are as follows: as shown in Fig. 2, after chip powers on, Power on reset signal
PORN becomes high level from low level, and after Td postpones, PORN_DELAY becomes high level.In Td delayed phase, the first electricity
Stream source IP 1, the second current source IP2, third current source IN1 and the 4th current source IN2 electric current are both turned on.The wherein electricity of IP2 and IP1
Stream ratio is that the current ratio of 10:1, IN2 and IN1 are 10:1.
When the level of input pin AD is lower than first voltage threshold value, it is low level that the first buffer module, which exports OUT<1>,.
Second buffer module will compare the connected resistance value of input pin AD, not according to resistance value on input pin to ground access
Together, the second buffer module output OUT<0>is the different level of height.
Similarly, when the level of input pin is higher than first voltage threshold value, it is high electricity that the first buffer module, which exports OUT<1>,
It is flat.Second buffer module will compare the connected resistance value of input pin AD, according to resistance value on input pin to power path
Difference, it is the different level of height that the second buffer module, which exports OUT<0>,.
When PORN_DELAY becomes high level, OUT<1:0>is latched by d type flip flop respectively, to obtain ADDR
<1:0>, I2C module can configure the different addresses I2C according to the logic level of ADDR<1:0>.Meanwhile passing through PORN_DELAY
Signal turns off current source IP2 and IN2, reduces module dissipation.
For example, after PORN is got higher, I2C address selection module is opened when input pin AD connects the resistance greater than threshold value to ground
Beginning work, OUT<1>is low level at this time, and OUT<0>is high level.After PORN_DELAY is got higher, ADDR<1:0>is equal to 01.
Another aspect according to the present utility model provides a kind of chip, including above-mentioned input buffer.
The input buffer of the I2C address choice can reliably export four kinds of I2C address selection logics, can save pin money
Source, to save the costs such as encapsulation and chip area.
Those of ordinary skill in the art may be aware that mould described in conjunction with the examples disclosed in the embodiments of the present disclosure
Block and method and step can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The range of the utility model embodiment.
Embodiment of above is merely to illustrate the utility model embodiment, and not to the limit of the utility model embodiment
System, those of ordinary skill in related technical field, in the case where not departing from the spirit and scope of the utility model embodiment, also
It can make a variety of changes and modification, therefore all equivalent technical solutions also belong to the scope of the utility model embodiment, this
The scope of patent protection of utility model embodiment should be defined by the claims.
Claims (14)
1. a kind of input buffer characterized by comprising
First buffer module (10), first buffer module (10) connect with input pin, and defeated according to the input pin
The voltage value entered and preset first voltage threshold value export the first digital signal；
Second buffer module (20), second buffer module (20) connect with the input pin, and are drawn according to the input
The voltage value of foot, preset second voltage threshold value, preset tertiary voltage threshold value export the second digital signal and third number letter
Number；
First buffer module (10) and/or second buffer module (20) are according to first digital signal, the second number
Word signal and third digital signal, determine the value of the first code bit and the second code bit in output state code, wherein the first voltage
Threshold value is between the second voltage threshold value and the tertiary voltage threshold value.
2. input buffer according to claim 1, which is characterized in that first buffer module (10) is according to described
One digital signal determines the value of the first code bit described in the output state code, and second buffer module (20) is according to described
One digital signal, the second digital signal and third digital signal, determine the value of the second code bit in output state code.
3. input buffer according to claim 2, which is characterized in that
When first digital signal indicates the voltage value of the input pin greater than the first voltage threshold value, described first
The value of code bit is first state value；
When first digital signal indicates the voltage value of the input pin less than the first voltage threshold value, described first
The value of code bit is the second state value.
4. input buffer according to claim 3, which is characterized in that the tertiary voltage threshold value is greater than second electricity
Threshold value is pressed,
If the third digital signal indicate the input pin voltage value be greater than the tertiary voltage threshold value, described second
The value of code bit is first state value；
If the third digital signal indicates that the voltage value of the input pin is less than the tertiary voltage threshold value and described first
Digital signal indicates that the voltage value of the input pin is greater than the first voltage threshold value, then the value of second code bit is second
State value；
If first digital signal indicates that the voltage value of the input pin is less than the first voltage threshold value and described second
Digital signal indicates that the voltage value of the input pin is greater than the second voltage threshold value, then the value of second code bit is first
State value；
If second digital signal indicate the input pin voltage value be less than the second voltage threshold value, described second
The value of code bit is the second state value.
5. input buffer according to claim 2, which is characterized in that second buffer module (20) includes relatively more single
Member, the comparing unit are connect with the input pin, for by the voltage value of the input pin respectively with second voltage threshold
Value and tertiary voltage threshold value comparison, and second digital signal and third digital signal are exported according to comparison result.
6. input buffer according to claim 5, which is characterized in that the comparing unit includes the first comparing subunit
(21), voltage value and the second voltage threshold value of first comparing subunit (21) for the input pin,
Second digital signal is exported according to comparison result.
7. input buffer according to claim 6, which is characterized in that first comparing subunit (21) includes first
The source electrode of NMOS tube and first voltage comparison circuit, first NMOS tube is connect with the input pin, grid and described the
The connection of one voltage comparator circuit, drains for exporting second digital signal.
8. input buffer according to claim 7, which is characterized in that first comparison circuit includes:
First current source and the second current source, first current source and the second current source are arranged in parallel；
Second NMOS tube, the drain and gate of second NMOS tube connect with first current source and second current source
It connects, and second current source is connect by the first control switch with second NMOS tube, the source electrode of second NMOS tube
It is grounded by first resistor.
9. input buffer according to claim 5, which is characterized in that the comparing unit includes the second comparing subunit
(22), second comparing subunit (22) is used to compare the voltage value and tertiary voltage threshold value of input pin, according to comparing
As a result the third digital signal is exported.
10. input buffer according to claim 9, which is characterized in that second comparing subunit (22) includes the
The source electrode of one PMOS tube and second voltage comparison circuit, first PMOS tube is connect with the input pin, grid with it is described
The connection of second voltage comparison circuit, drains for exporting the third digital signal.
11. input buffer according to claim 10, which is characterized in that the second voltage comparison circuit includes:
Third current source and the 4th current source, the third current source and the 4th current source are arranged in parallel；
Second PMOS tube, the drain and gate of second PMOS tube connect with the third current source and the 4th current source
It connects, and the 4th current source is connect by the second control switch with second PMOS tube, the source electrode of second PMOS tube
It is connected to power supply by 3rd resistor.
12. input buffer according to claim 2, which is characterized in that second buffer module (20) further includes patrolling
It collects processing unit (23), the Logical processing unit (23) is used for according to first digital signal, second digital signal
With the third digital signal, the value of second code bit is determined.
13. input buffer according to claim 12, which is characterized in that the Logical processing unit (23) includes:
First NAND gate, first NAND gate are exported according to the first digital signal, the second digital signal and third digital signal
First processing signal；
Second NAND gate, second NAND gate is according to the inversion signal of the first digital signal, the second digital signal and third number
The inversion signal of word signal exports second processing signal；
Third NAND gate, the third NAND gate determine described the according to the first processing signal and the second processing signal
The value of two code bits.
14. a kind of chip, which is characterized in that including input buffer of any of claims 1-13.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112349332A (en) * | 2020-10-23 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Input buffer circuit and memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112349332A (en) * | 2020-10-23 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Input buffer circuit and memory |
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Address after: Room 1201, No.2, Lane 908, Xiuwen Road, Minhang District, Shanghai, 201199 Patentee after: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region after: China Address before: Room 303-39, building 33, 680 Guiping Road, Xuhui District, Shanghai 200233 Patentee before: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region before: China |