CN115291667B - Wireless communication device and adaptive bias voltage adjustment circuit - Google Patents

Wireless communication device and adaptive bias voltage adjustment circuit Download PDF

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Publication number
CN115291667B
CN115291667B CN202111582515.3A CN202111582515A CN115291667B CN 115291667 B CN115291667 B CN 115291667B CN 202111582515 A CN202111582515 A CN 202111582515A CN 115291667 B CN115291667 B CN 115291667B
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circuit
coupled
power amplifier
nmos tube
current
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CN115291667A (en
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刘树钰
徐汉儒
杨丰林
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Xiaxin Microelectronics Shanghai Co ltd
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Xiaxin Microelectronics Shanghai Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

A wireless communication device and an adaptive bias voltage adjustment circuit, the adaptive bias voltage adjustment circuit comprising: the bias voltage generating circuit comprises a proportional attenuation circuit, a difference feedback circuit and a bias voltage generating circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and the difference feedback circuit is used for obtaining the difference between the input signal of the power amplifier and the output signal of the proportional attenuation circuit and obtaining difference feedback; and the bias voltage generating circuit is used for generating bias voltage according to the input signal of the power amplifier and the difference feedback. According to the scheme, the high linearity can be kept when the power amplifier is in a high-power output working state, the emission efficiency can be improved when the power amplifier is in a low-power output working state, and the bias voltage can be accurately adjusted.

Description

Wireless communication device and adaptive bias voltage adjustment circuit
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a wireless communication device and an adaptive bias voltage adjusting circuit.
Background
Wireless communication devices have been widely used in people's daily lives, and radio frequency power amplifiers are a vital module in wireless communication devices. The Power Amplifier (PA) can amplify the Power of the radio frequency signal generated by the modulation oscillation circuit to reach the preset radio frequency output Power, so as to increase the coverage of the transmitting signal.
In the prior art, for power amplifiers, it is often necessary to use a control strategy for the bias voltage to optimize the output of the power amplifier, thereby enabling the wireless communication device to reduce the power consumption of the distortion of the signal output.
However, the existing bias voltage control strategy has poor linearity when the power amplifier is in a high-power output working state, and has low emission efficiency and cannot accurately adjust the bias voltage when the power amplifier is in a low-power output working state.
Disclosure of Invention
The technical problems solved by the embodiment of the invention are as follows: the existing bias voltage control strategy has poor linearity when the power amplifier is in a high-power output working state, and has low emission efficiency and cannot accurately adjust bias voltage when the power amplifier is in a low-power output working state.
To solve the above technical problem, an embodiment of the present invention provides a wireless communication device, including: the signal generation module is used for generating a signal to be transmitted; the power amplifier is used for amplifying the power of the signal to be transmitted; the signal output module is used for receiving the signal to be transmitted after the power amplification and transmitting the signal; an adaptive bias voltage adjustment circuit for providing a bias voltage to the power amplifier, the adaptive bias voltage adjustment circuit comprising: the bias voltage generating circuit comprises a proportional attenuation circuit, a difference feedback circuit and a bias voltage generating circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation multiple of the proportional attenuation circuit is equal to the amplification multiple of the power amplifier; the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, and the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and is used for obtaining a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit to obtain difference feedback; the bias voltage generating circuit has a first input end coupled with the input end of the power amplifier, a second input end coupled with the output end of the difference value feedback circuit, and an output end coupled with the control end of the power amplifier, and is used for generating bias voltage according to the input end signal of the power amplifier and the difference value feedback and outputting the bias voltage to the control end of the power amplifier.
Optionally, the input signal of the power amplifier includes a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein: the first input end of the square circuit inputs the first differential signal and the difference feedback, and the second input end of the square circuit inputs the second differential signal and the difference feedback; the input end of the current mirror circuit is coupled with the output end of the square circuit; and the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
Optionally, the current mirror circuit includes: the first PMOS tube and the current amplifying unit; wherein: the grid electrode of the first PMOS tube is coupled with the input end of the current amplifying unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage; and the output end of the current amplifying unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
Optionally, the current mirror circuit further includes: and the register is coupled with the control end of the current amplifying unit and is used for inputting the set current amplification factor to the current amplifying unit.
Optionally, the squaring circuit includes: the first NMOS tube, second NMOS tube, wherein: the grid electrode of the first NMOS tube is coupled with the first input end of the square circuit, the drain electrode of the first NMOS tube is coupled with the output end of the square circuit, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
Optionally, the current-voltage conversion circuit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, third resistance, fourth resistance, wherein: the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with low potential; the drain electrode of the fifth NMOS tube is connected with a preset power supply voltage, the grid electrode of the fifth NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the fifth NMOS tube is coupled with the first end of the third resistor; the drain electrode of the sixth NMOS tube is connected with a preset power supply voltage, the grid electrode of the sixth NMOS tube is coupled with the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is coupled with the first end of the fourth resistor and the grid electrode of the fourth NMOS tube; the second end of the third resistor and the second end of the fourth resistor are both connected with low potential.
Optionally, the bias voltage generating circuit further includes: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier, the buffer circuit is used for driving and amplifying the bias voltage, and the input voltage of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
Optionally, the difference feedback circuit includes a comparison amplifying circuit.
Optionally, the input end of the power amplifier is coupled with a pre-power amplifier; and the input end of the front power amplifier is input with a target signal and is used for amplifying the target signal to obtain the input signal of the power amplifier.
In order to solve the above technical problem, an embodiment of the present invention further provides an adaptive bias voltage adjusting circuit, configured to output a bias voltage to a power amplifier, including: the bias voltage generating circuit comprises a proportional attenuation circuit, a difference feedback circuit and a bias voltage generating circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation multiple of the proportional attenuation circuit is equal to the amplification multiple of the power amplifier; the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, and the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and is used for obtaining a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit to obtain difference feedback; the bias voltage generating circuit has a first input end coupled with the input end of the power amplifier, a second input end coupled with the output end of the difference value feedback circuit, and an output end coupled with the control end of the power amplifier, and is used for generating bias voltage according to the input end signal of the power amplifier and the difference value feedback and outputting the bias voltage to the control end of the power amplifier.
Optionally, the input signal of the power amplifier includes a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein: the first input end of the square circuit inputs the first differential signal and the difference feedback, and the second input end of the square circuit inputs the second differential signal and the difference feedback; the input end of the current mirror circuit is coupled with the output end of the square circuit; and the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
Optionally, the current mirror circuit includes: the first PMOS tube and the current amplifying unit; wherein: the grid electrode of the first PMOS tube is coupled with the input end of the current amplifying unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage; and the output end of the current amplifying unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
Optionally, the current mirror circuit further includes: and the register is coupled with the control end of the current amplifying unit and is used for inputting the set current amplification factor to the current amplifying unit.
Optionally, the squaring circuit includes: the first NMOS tube, second NMOS tube, wherein: the grid electrode of the first NMOS tube is coupled with the first input end of the square circuit, the drain electrode of the first NMOS tube is coupled with the output end of the square circuit, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
Optionally, the current-voltage conversion circuit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, third resistance, fourth resistance, wherein: the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with low potential; the drain electrode of the fifth NMOS tube is connected with a preset power supply voltage, the grid electrode of the fifth NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the fifth NMOS tube is coupled with the first end of the third resistor; the drain electrode of the sixth NMOS tube is connected with a preset power supply voltage, the grid electrode of the sixth NMOS tube is coupled with the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is coupled with the first end of the fourth resistor and the grid electrode of the fourth NMOS tube; the second end of the third resistor and the second end of the fourth resistor are both connected with low potential.
Optionally, the bias voltage generating circuit further includes: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier, the buffer circuit is used for driving and amplifying the bias voltage, and the input voltage of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
Optionally, the difference feedback circuit includes a comparison amplifying circuit.
Optionally, the input end of the power amplifier is coupled with a pre-power amplifier; and the input end of the front power amplifier is input with a target signal and is used for amplifying the target signal to obtain the input signal of the power amplifier.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the power consumption of the wireless communication equipment is reduced by adaptively adjusting the generated bias voltage through the amplitude of the input signal of the power amplifier and the feedback of the difference value between the input signal of the power amplifier and the output signal of the proportional attenuation circuit, so that the output signal and the input signal of the power amplifier are in linear relation when the power amplifier outputs high power, and the emission efficiency is higher when the power amplifier outputs low power and the accurate bias voltage can be maintained.
Drawings
Fig. 1 is a schematic diagram of a wireless communication device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an adaptive bias voltage adjustment circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a bias voltage generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a current-voltage conversion circuit according to an embodiment of the present invention.
Detailed Description
As described above, the conventional bias voltage control strategy has poor linearity when the power amplifier is in the high power output operation state, and cannot accurately adjust the bias voltage when the power amplifier is in the low power output operation state.
In the embodiment of the invention, the generated bias voltage is adaptively adjusted through the amplitude of the input signal of the power amplifier and the feedback of the difference value between the input signal of the power amplifier and the output signal of the proportional attenuation circuit, so that the output signal and the input signal of the power amplifier are in a linear relation when the power amplifier outputs high power, and the emission efficiency is higher and the accurate bias voltage can be kept when the power amplifier outputs low power so as to reduce the power consumption.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, a radio communication device in an embodiment of the present invention is presented. In an embodiment of the present invention, the wireless communication device includes a signal generating module 11, a power amplifier 10, a signal output module 12, and an adaptive bias voltage adjusting circuit 13, wherein:
a signal generating module 11, configured to generate a signal to be transmitted;
a power amplifier 10, configured to power amplify the signal to be sent;
a signal output module 12, configured to receive the signal to be transmitted after power amplification and transmit the signal;
an adaptive bias voltage adjustment circuit 13 for providing a bias voltage to the power amplifier.
In specific implementation, the specific working principles and structures of the signal generating module 11, the power amplifier 10 and the signal output module 12 may refer to the prior art, and the embodiments of the present invention are not described in detail.
The adaptive bias voltage adjusting circuit 13 provided in the above-described embodiment of the present invention will be described in detail.
Referring to fig. 2, a schematic diagram of a structure of an adaptive bias voltage adjusting circuit according to an embodiment of the present invention is shown.
In an embodiment of the present invention, the adaptive bias voltage adjusting circuit may include: a proportional decay circuit 20, a difference feedback circuit 30, and a bias voltage generation circuit 40.
In implementations, an input of the proportional attenuation circuit 20 may be coupled to an output of the power amplifier 10, and an output of the proportional attenuation circuit 20 may be coupled to a first input of the difference feedback circuit 30. The output signal of the power amplifier 10 can be attenuated by a corresponding attenuation factor by the proportional attenuation circuit 20.
In an embodiment of the present invention, the attenuation factor of the proportional attenuation circuit 20 may be equal to the amplification factor of the power amplifier 10. The amplification factor of the power amplifier 10 means: the power amplifier 10 amplifies the signal inputted thereto by N times; the amplification factor of the proportional attenuation circuit 20 means: the proportional attenuation circuit 20 attenuates the signal input thereto by N times, that is, the amplitude of the signal output from the proportional attenuation circuit 20 is 1/N of the amplitude of the signal input thereto.
The attenuation factor in the embodiment of the invention is theoretical attenuation factor, and the amplification factor is theoretical amplification factor unless otherwise specified.
Therefore, if the power amplifier 10 is in the linear amplification state, the input signal of the power amplifier 10 is approximately equal to the output signal of the proportional attenuation circuit 20. If the power amplifier 10 is in the saturated state, the input signal of the power amplifier 10 and the output signal of the proportional attenuator are greatly different because the saturated state is a nonlinear amplifying state.
In an embodiment of the present invention, a first input terminal of the differential feedback circuit 30 may be coupled to an input terminal of the power amplifier 10, a second input terminal of the differential feedback circuit 30 may be coupled to an output terminal of the proportional attenuation circuit 20, and an output terminal of the differential feedback circuit 30 may be coupled to a first input terminal of the bias voltage generating circuit 40. The difference value between the input signal of the power amplifier 10 and the output signal of the proportional attenuation circuit 20 can be obtained through the difference value feedback circuit 30, and the difference value is correspondingly amplified to obtain the difference value feedback.
In the embodiment of the present invention, a first input terminal of the bias voltage generating circuit 40 is coupled to the input terminal of the power amplifier 10, a second input terminal of the bias voltage generating circuit 40 is coupled to the output terminal of the differential feedback circuit 30, and an output terminal of the bias voltage generating circuit 40 is coupled to the control terminal of the power amplifier 10. The bias voltage generating circuit 40 can generate a corresponding bias voltage according to the input signal of the power amplifier 10 and the amplitude corresponding to the difference feedback, and output the bias voltage to the control end of the power amplifier 10, so as to adjust the bias voltage of the power amplifier 10 in real time.
In the embodiment of the present invention, the input signal of the power amplifier 10 may be a differential signal, which is a first differential signal and a second differential signal respectively. Referring to fig. 3, a schematic diagram of a bias voltage generating circuit 40 in an embodiment of the present invention is shown.
In an implementation, the bias voltage generating circuit 40 may include a squaring circuit, a current mirror circuit, and a current-to-voltage conversion circuit, where:
the first input end of the square circuit can input a first differential signal and difference feedback, and the second input end of the square circuit can input a second differential signal and difference feedback;
an input of the current mirror circuit may be coupled to an output of the squaring circuit;
an input of the current-to-voltage conversion circuit may be coupled to an output of the current mirror circuit, and an output of the current-to-voltage conversion circuit may output a bias voltage to the power amplifier 10.
In the embodiment of the present invention, the current mirror circuit may include a first PMOS transistor MP1 and a current amplifying unit, where:
the grid electrode of the first PMOS tube MP1 can be coupled with the input end of the current amplifying unit, the drain electrode of the first PMOS tube can be coupled with the input end of the current mirror circuit and the grid electrode of the first PMOS tube MP1, and the source electrode of the first PMOS tube is connected with a preset power supply voltage VDD.
The input end of the current amplifying unit is coupled with the grid electrode of the first PMOS tube MP1, and the output end of the current amplifying unit can be coupled with the output end of the current mirror circuit. And the current output by the square circuit is correspondingly amplified by the current amplifying unit and is output to the current-voltage conversion circuit.
In a specific implementation, the amplification factor of the current amplifying unit may be preset, and the amplification factor is input to the current amplifying unit. The current amplifying unit can correspondingly amplify the current input by the input end according to the set amplification factor. The amplification factor of the current amplification unit can be set according to the actual application scene.
In an embodiment of the present invention, the current mirror circuit may further include a register circuit. The output of the register circuit may be coupled to the control terminal of the current amplifying unit. The register unit may be in communication with the current amplifying unit, and the value stored in the register unit may be the amplification factor of the current amplifying unit. The current amplification factor of the current amplification unit can be correspondingly adjusted by setting the numerical value stored in the register unit.
For example, the register is a 4-bit register in which a 4-bit binary value is stored. When the binary value stored in the register is 1000, this means that the current amplification factor of the current amplification unit is 8 times. When the binary value stored in the register is 1010, this means that the current amplification factor of the current amplification unit is 10 times.
In a specific application, the values in the registers may be set according to a specific application scenario, and are not limited to the above examples.
In the embodiment of the present invention, the squaring circuit may include a first NMOS transistor MN1 and a second NMOS transistor MN2, where:
the gate of the first NMOS transistor MN1 may be coupled to the first input terminal of the squaring circuit, the drain of the first NMOS transistor MN1 may be coupled to the output terminal of the squaring circuit, and the source of the first NMOS transistor MN1 may be grounded;
the gate of the second NMOS transistor MN2 may be coupled to the second input terminal of the square circuit, the drain of the second NMOS transistor MN2 may be coupled to the drain of the first NMOS transistor MN1, and the source of the second NMOS transistor MN2 may be grounded.
In an implementation, the squaring circuit may further include a first resistor R1 and a second resistor R2, a first capacitor C1, and a second capacitor C2.
In the embodiment of the present invention, a first end of the first resistor R1 may be coupled to the gate of the first NMOS MN1, and a second end of the first resistor R1 may be coupled to the output end of the differential feedback circuit 30, for inputting differential feedback; the first end of the second resistor R2 may be coupled to the gate of the second NMOS MN2, and the second end of the second resistor R2 may also be coupled to the output end of the differential feedback circuit 30 for inputting the differential feedback.
A first differential signal is input to a first end of a first capacitor C1, and a second end of the first capacitor C1 is coupled with a grid electrode of a first NMOS tube MN1 and a first end of a first resistor R1; the first end of the second capacitor C2 inputs the second differential signal, and the second end of the second capacitor C2 is coupled to the gate of the second NMOS transistor MN2 and the first end of the second resistor R2.
In implementations, the input of the power amplifier 10 may be coupled with a pre-power amplifier 50. The input of the pre-power amplifier 50 inputs the target signal. The target signal is amplified by the pre-power amplifier 50, and the output signal of the pre-power amplifier 50 is the input signal of the power amplifier 10. An input of the pre-power amplifier 50 may be coupled to an output of the signal generation module 11.
Referring to fig. 4, a schematic diagram of a current-voltage conversion circuit according to an embodiment of the present invention is shown.
In an embodiment of the present invention, the current-voltage conversion circuit may include: the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the third resistor R3 and the fourth resistor R4, wherein:
the drain electrode of the third NMOS tube MN3 can be coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube MN3 can be coupled with the drain electrode of the fourth NMOS tube MN 4;
the grid electrode of the fourth NMOS tube MN4 is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube MN4 is connected with the low potential VSS;
the grid electrode of the fifth NMOS tube MN5 is coupled with the input end of the current-voltage conversion circuit, the drain electrode of the fifth NMOS tube MN5 is connected with a preset power supply voltage VDD, and the source electrode of the fifth NMOS tube MN5 is connected with the first end of the third resistor R3;
the drain electrode of the sixth NMOS tube MN6 is connected with a preset power supply voltage VDD, the grid electrode of the sixth NMOS tube MN6 is coupled with the drain electrode of the fifth NMOS tube MN5, and the source electrode of the sixth NMOS tube MN6 is coupled with the first end of the fourth resistor R4;
the second end of the third resistor R3 and the second end of the fourth resistor R4 are both connected to the low potential VSS.
In an implementation, bias voltage generating circuit 40 may also include a buffer circuit. An input of the buffer circuit may be coupled to the current-to-voltage conversion circuit, and an output of the buffer circuit may be coupled to an output of the power amplifier 10. The input voltage of the input end of the buffer circuit is related to the output voltage of the output end of the current-voltage conversion circuit. In the embodiment of the invention, the input voltage of the buffer circuit may be equal to the output voltage of the current-voltage conversion circuit.
The bias voltage output from the current-voltage conversion circuit is drive-amplified by the buffer circuit and output to the control terminal of the power amplifier 10. That is, the bias voltage inputted to the control terminal of the power amplifier 10 may be obtained after the buffer driving amplification.
Referring to fig. 4, the buffer circuit may include a seventh NMOS transistor MN7, and the seventh NMOS transistor MN7 may be formed of a plurality of NMOS transistors connected in parallel, thereby enhancing driving capability of the buffer circuit.
In the embodiment of the present invention, the current-voltage conversion circuit may further include an eighth NMOS transistor MN8. The drain of the eighth NMOS transistor MN8 is coupled to the drain of the third NMOS transistor MN3 and the gate of the fifth NMOS transistor MN5, and the source of the eighth NMOS transistor MN8 is connected to the low potential VSS.
In the embodiment of the present invention, the current-voltage conversion circuit may further include a ninth NMOS transistor MN9. The drain of the ninth NMOS transistor MN9 is coupled to the gate of the fourth NMOS transistor MN4, and the source of the ninth NMOS transistor MN9 is connected to the low potential VSS. The working state of the current-voltage conversion unit can be controlled through the eighth NMOS tube MN8 and the ninth NMOS tube MN9.
The following describes the operation principle of the adaptive bias voltage adjusting circuit provided in the above embodiment of the present invention.
The target signal PAin is input to the pre-power amplifier 50, and the target signal PAin is a differential signal. The pre-power amplifier 50 amplifies and outputs the target signal PAin, and sets the output signal of the pre-power amplifier 50 to pa_in, that is, the input signal of the power amplifier 10 to pa_in, and the corresponding amplitude to pa_in. As can be seen from the above embodiments of the present invention, the input signal of the power amplifier 10 includes a first differential signal vpa_in+ and a second differential signal vpa_in-.
The voltage corresponding to the difference feedback output by the difference feedback circuit 30 is Vb. The magnitude of Vb is related to the difference between the output signal of proportional attenuation circuit 20 and the input signal of power amplifier 10.
The output of the difference feedback circuit 30 is coupled to a first input of the squaring circuit, which inputs vpa_in+ and Vb, and to a second input of the squaring circuit, which inputs vpa_in-and Vb.
Vb+vpa_in (vpa_in includes vpa_in+ and vpa_in-) is converted into a corresponding drain current Id by a squaring circuit and output to a current mirror circuit.
The current mirror circuit amplifies the input current Id. The current mirror circuit amplifies the current Id by k, and the current output by the current mirror circuit is k Id. The current output by the current mirror circuit forms a bias voltage V on the gate of the fourth NMOS transistor MN4 via the current-voltage conversion circuit pa_bias And output to the power amplifier 10.
Bias voltage V pa_bias Is in linear relation with the amplitude of the first differential signal Vpa_in+, and V PA_bias Through VbThe size is adjusted. Setting the amplitude of the first differential signal Vpa_in+ to A/2, V pa_bias The relation with amplitude A/2 is:
；
wherein beta is in =1/2μ n C ox *(W/L) in ，β out =1/2μ n C ox *(W/L) out ，μ n For electron mobility of NMOS tube, C ox Capacitance of gate oxide layer per unit area, (W/L) in The width-to-length ratio (W/L) of the first NMOS transistor MN1 or the second NMOS transistor MN2 out Is the width-to-length ratio of the fourth NMOS transistor MN4, V TH Setting the default values of Vb and V for the threshold voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 TH Close.
In the current-voltage conversion circuit, the conversion relationship of the current and the voltage can be expressed as:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,phase angles of Vpa_in+ and Vth-Vb +.>Is an input signal.
In summary, in the embodiment of the present invention, the generated bias voltage is adaptively adjusted by the amplitude of the input signal of the power amplifier 10 and the feedback of the difference between the input signal of the power amplifier 10 and the output signal of the proportional attenuation circuit 20, so that the output signal and the input signal of the power amplifier 10 are in a linear relationship during high power output, and the accurate bias voltage is maintained during low power output to reduce the power consumption.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A wireless communication device, comprising:
the signal generation module is used for generating a signal to be transmitted;
the power amplifier is used for amplifying the power of the signal to be transmitted;
the signal output module is used for receiving the signal to be transmitted after the power amplification and transmitting the signal;
an adaptive bias voltage adjustment circuit for providing a bias voltage to the power amplifier, the adaptive bias voltage adjustment circuit comprising:
the bias voltage generating circuit comprises a proportional attenuation circuit, a difference feedback circuit and a bias voltage generating circuit, wherein:
the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation multiple of the proportional attenuation circuit is equal to the amplification multiple of the power amplifier;
the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, and the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and is used for obtaining a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit to obtain difference feedback;
the bias voltage generating circuit has a first input end coupled with the input end of the power amplifier, a second input end coupled with the output end of the difference value feedback circuit, and an output end coupled with the control end of the power amplifier, and is used for generating bias voltage according to the input signal of the power amplifier and the difference value feedback and outputting the bias voltage to the control end of the power amplifier.
2. The wireless communication device of claim 1, wherein the input signal of the power amplifier comprises a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein:
the first input end of the square circuit inputs the first differential signal and the difference feedback, and the second input end of the square circuit inputs the second differential signal and the difference feedback;
the input end of the current mirror circuit is coupled with the output end of the square circuit;
and the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
3. The wireless communication device of claim 2, wherein the current mirror circuit comprises: the first PMOS tube and the current amplifying unit; wherein:
the grid electrode of the first PMOS tube is coupled with the input end of the current amplifying unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage;
and the output end of the current amplifying unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
4. The wireless communication device of claim 3, wherein the current mirror circuit further comprises: and the register is coupled with the control end of the current amplifying unit and is used for inputting the set current amplification factor to the current amplifying unit.
5. The wireless communication device of claim 2, wherein the squaring circuit comprises: the first NMOS tube, second NMOS tube, wherein:
the grid electrode of the first NMOS tube is coupled with the first input end of the square circuit, the drain electrode of the first NMOS tube is coupled with the output end of the square circuit, and the source electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
6. The wireless communication device of claim 2, wherein the current-to-voltage conversion circuit comprises: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, third resistance, fourth resistance, wherein:
the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with low potential;
the drain electrode of the fifth NMOS tube is connected with a preset power supply voltage, the grid electrode of the fifth NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the fifth NMOS tube is coupled with the first end of the third resistor;
the drain electrode of the sixth NMOS tube is connected with a preset power supply voltage, the grid electrode of the sixth NMOS tube is coupled with the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is coupled with the first end of the fourth resistor and the grid electrode of the fourth NMOS tube;
the second end of the third resistor and the second end of the fourth resistor are both connected with low potential.
7. The wireless communication device of claim 2, wherein the bias voltage generating circuit further comprises: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier, the buffer circuit is used for driving and amplifying the bias voltage, and the input voltage of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
8. The wireless communication device of claim 1, wherein the difference feedback circuit comprises a comparison amplification circuit.
9. The wireless communication device of claim 1, wherein an input of the power amplifier is coupled with a pre-power amplifier; and the input end of the front power amplifier is input with a target signal and is used for amplifying the target signal to obtain the input signal of the power amplifier.
10. An adaptive bias voltage adjustment circuit for outputting a bias voltage to a power amplifier, comprising: the bias voltage generating circuit comprises a proportional attenuation circuit, a difference feedback circuit and a bias voltage generating circuit, wherein:
the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation multiple of the proportional attenuation circuit is equal to the amplification multiple of the power amplifier;
the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, and the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and is used for obtaining a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit to obtain difference feedback;
the bias voltage generating circuit has a first input end coupled with the input end of the power amplifier, a second input end coupled with the output end of the difference value feedback circuit, and an output end coupled with the control end of the power amplifier, and is used for generating bias voltage according to the input signal of the power amplifier and the difference value feedback and outputting the bias voltage to the control end of the power amplifier.
11. The adaptive bias voltage adjustment circuit of claim 10, wherein the input signal of the power amplifier comprises a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein:
the first input end of the square circuit inputs the first differential signal and the difference feedback, and the second input end of the square circuit inputs the second differential signal and the difference feedback;
the input end of the current mirror circuit is coupled with the output end of the square circuit;
and the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
12. The adaptive bias voltage adjustment circuit of claim 11, wherein the current mirror circuit comprises: the first PMOS tube and the current amplifying unit; wherein:
the grid electrode of the first PMOS tube is coupled with the input end of the current amplifying unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage;
and the output end of the current amplifying unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
13. The adaptive bias voltage adjustment circuit of claim 12, wherein the current mirror circuit further comprises: and the register is coupled with the control end of the current amplifying unit and is used for inputting the set current amplification factor to the current amplifying unit.
14. The adaptive bias voltage adjustment circuit of claim 11, wherein the squaring circuit comprises: the first NMOS tube, second NMOS tube, wherein:
the grid electrode of the first NMOS tube is coupled with the first input end of the square circuit, the drain electrode of the first NMOS tube is coupled with the output end of the square circuit, and the source electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
15. The adaptive bias voltage adjustment circuit of claim 11, wherein the current-to-voltage conversion circuit comprises: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe, third resistance, fourth resistance, wherein:
the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with low potential;
the drain electrode of the fifth NMOS tube is connected with a preset power supply voltage, the grid electrode of the fifth NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the fifth NMOS tube is coupled with the first end of the third resistor;
the drain electrode of the sixth NMOS tube is connected with a preset power supply voltage, the grid electrode of the sixth NMOS tube is coupled with the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is coupled with the first end of the fourth resistor and the grid electrode of the fourth NMOS tube;
the second end of the third resistor and the second end of the fourth resistor are both connected with low potential.
16. The adaptive bias voltage adjustment circuit of claim 11, wherein the bias voltage generation circuit further comprises: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier, the buffer circuit is used for driving and amplifying the bias voltage, and the input voltage of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
17. The adaptive bias voltage adjustment circuit of claim 10, wherein the difference feedback circuit comprises a comparison amplifier circuit.
18. The adaptive bias voltage adjustment circuit of claim 10, wherein an input of the power amplifier is coupled to a pre-power amplifier; and the input end of the front power amplifier is input with a target signal and is used for amplifying the target signal to obtain the input signal of the power amplifier.
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