JP2005110327A - Electronic component for high-frequency power amplifier, and high-frequency power amplification system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency power amplifier circuit having a good output linearity, capable of transmission in an open loop system having a good efficiency at low output. <P>SOLUTION: The high-frequency power amplifier circuit of the open loop system enables a signal output having a level corresponding to a required output level, by controlling a supply voltage of an output power FET based on an output-level control signal. A bias voltage generator circuit (222) is provided for generating a gate bias voltage of the output power FET, according to the output voltage of a power supply control circuit (221) for controlling the supply voltage of the output power FET based on the output-level control signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technology that is effective when applied to a high-frequency power amplifier circuit and a wireless communication device such as a mobile phone incorporating the high-frequency power amplifier circuit. In particular, the present invention controls the power supply voltage of an output power FET constituting the high-frequency power amplifier circuit. The present invention relates to a technology for increasing the speed and improving the efficiency at low output in an open-loop high-frequency power amplifier circuit that can control output power.

  A high-frequency power amplifier circuit (generally a multi-stage) using a semiconductor amplifier element such as a MOSFET (field effect transistor) or a GaAs-MESFET in a transmission side output unit of a wireless communication device (mobile communication device) such as an automobile phone or a mobile phone And a module (referred to as an RF power module) in which the bias circuit is integrated.

By the way, in general, a mobile phone makes a call by changing the output (transmission power) so as to adapt to the surrounding environment according to the power level instruction information from the base station according to the use environment, and causes interference with other mobile phones. The system is configured so that it does not occur.
For example, the RF power module at the transmitter output stage in cellular systems such as the North American 900 MHz standard system and the European GSM (Global System for Mobile Communication) system detects the DC level of the output and outputs the output power required for a call. An APC (Automatic Power Control) circuit that applies feedback to a gate bias circuit that generates a gate bias voltage of an output power element is provided (for example, Patent Document 1). Such a control method is generally called a closed loop method.
JP 2000-151310 A

  However, the output power control method using the APC circuit has a problem that the circuit scale increases and the mounting density decreases. Therefore, by controlling the power supply voltage of the output power FET based on the output level designation signal corresponding to the required output level, a signal corresponding to the required output level is output from the high frequency power amplifier circuit. There is. This method is called an open loop method and has an advantage that the circuit scale can be reduced as compared with the closed loop method.

  However, the conventional open-loop high-frequency power amplifier circuit has a problem in that the output linearity is good but the efficiency at low output is poor. Further, it has been found that there is a problem that the response speed to the signal specifying the output level is slow. In particular, voice signal communication is performed by a GMSK (Gaussian filtered Minimum Shift Keying) modulation method in which the phase of a carrier wave is phase-shifted according to transmission data, and data communication is performed by adding EDGE (Enhanced) to the phase shift of GMSK modulation. Data Rates for GMS Evolution) In a high-frequency power amplifier circuit used in a communication device that uses the modulation method, if you try to apply amplitude control by changing the power supply voltage of the output power FET based on the amplitude information of the transmission signal, It became clear that the response speed of the circuit was not sufficient.

An object of the present invention is to provide a high-frequency power amplifier circuit capable of open-loop transmission with good output linearity and high efficiency at low output.
Another object of the present invention is to provide a high-frequency power amplifier circuit that is excellent in responsiveness to a control signal when the output level is controlled by controlling the power supply voltage of the output power FET.
Another object of the present invention is to perform amplitude control by changing the power supply voltage of the output power FET based on the amplitude information of the transmission signal in addition to the GMSK modulation method in which the phase of the carrier wave is phase-shifted according to the transmission data. An object of the present invention is to provide a multifunctional high-frequency power amplifier circuit capable of transmission by a modulation method.
Still another object of the present invention is to provide a high frequency power amplifier circuit capable of extending the talk time and battery life of a wireless communication device.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
That is, in an open-loop high-frequency power amplifier circuit configured to output a signal of a level corresponding to the required output level by controlling the power supply voltage of the output power FET based on a signal specifying the output level, A bias voltage generation circuit that generates a gate bias voltage of the output power FET according to the output voltage of the power supply control circuit that controls the power supply voltage of the output power FET based on a signal specifying the level is provided.
According to the above-described means, it is possible to obtain a high-frequency power amplifier circuit capable of improving efficiency at the time of low output while guaranteeing output linearity. In addition, this improves the efficiency at a relatively frequently used low output, thereby reducing the total current consumption. In a radio communication device such as a mobile phone using this high frequency power amplifier circuit, the communication time and Battery life can be extended.

Preferably, as a power supply control circuit for controlling the power supply voltage of the output power FET based on a signal for designating an output level, an operational amplifier circuit for amplifying the signal for designating the output level and a gate based on the output of the operational amplifier circuit And a circuit configured to generate a desired power supply voltage by feeding back the drain voltage of the MOSFET to the operational amplifier circuit. A buffer circuit having a bipolar transistor as an active element is provided between the operational amplifier circuit and the gate terminal of the MOSFET that outputs the power supply voltage of the output power FET. As a result, the responsiveness to the control signal is improved, and a high-frequency power amplifier circuit capable of transmission by the EDGE modulation method in which the amplitude control is performed by changing the power supply voltage of the output power FET based on the amplitude information of the transmission signal is obtained.
More preferably, a phase compensation circuit including a CR circuit having a capacitor and a resistor connected in parallel is provided between the operational amplifier circuit and the gate terminal of the MOSFET that outputs the power supply voltage of the output power FET. As a result, a phase margin is generated in the power supply control circuit, and output distortion can be reduced.

  In addition, bias voltage switching means is provided that enables a bias voltage corresponding to a required output level to be supplied to the high-frequency power amplifier circuit instead of the bias voltage output from the bias voltage generation circuit. Thus, when the signal modulated in phase by the EDGE modulation method is input to the high frequency power amplifier circuit, and the output amplitude control information signal is input to the power supply control circuit instead of the signal specifying the output level, Instead of the bias voltage output from the bias voltage generation circuit, a bias voltage corresponding to a required output level is supplied to the high-frequency power amplifier circuit, so that a system capable of transmission by the EDGE modulation method can be configured. In such transmission, a bias voltage corresponding to the output level can be supplied to the high-frequency power amplifier circuit for operation.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, it is possible to realize a high-frequency power amplifier circuit capable of open-loop transmission with good output linearity and high efficiency at low output. In addition, the responsiveness to the control voltage in the case of controlling the output level by controlling the power supply voltage of the output power FET can be improved, whereby the phase of the carrier wave is phase-shifted according to the transmission data. In addition, it is possible to realize a multifunctional high-frequency power amplifier circuit capable of transmission by the EDGE modulation method in which the amplitude control is performed by changing the power supply voltage of the output power FET based on the amplitude information of the transmission signal. As a result, in the mobile phone using the high frequency power amplifier circuit of the present invention, there is an effect that the call time and the battery life become long.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments of the present invention.
FIG. 1 shows a schematic configuration of an embodiment of a high-frequency power amplifier circuit according to the present invention. In FIG. 1, reference numeral 210 denotes a high frequency power amplifier circuit, and 220 denotes an operating voltage control circuit that generates an applied voltage of the high frequency power amplifier circuit 210. The high-frequency power amplifier circuit 210 includes three amplifier stages 211, 212, and 213 and a bias circuit 214 that applies bias voltages Vg1, Vg2, and Vg3 to these amplifier stages. In addition, the operating voltage control circuit 220 includes a power supply control circuit 221 that generates a power supply voltage Vdd1 applied to the drain terminal of the output power FET of each amplification stage that constitutes the high frequency power amplifier circuit 210, and a control voltage for the bias circuit 214. It comprises a bias voltage generation circuit 222 that generates Vabc.

  In this embodiment, the power supply control circuit 221 supplies a power supply voltage to be applied to the drain terminal of the output power FET of the high frequency power amplifier circuit 210 based on an output level designation signal VPL that designates an output level supplied from a baseband circuit (not shown). Vdd1 is generated. The bias voltage generation circuit 222 is configured to generate the bias voltage Vabc based on the power supply voltage Vdd1 generated by the power supply control circuit 221. The baseband circuit generates an output level designation signal VPL based on, for example, an output level determined according to the distance from the base station, that is, the strength of the radio wave.

Further, in this embodiment, in order to enable transmission using the EDGE modulation method in addition to transmission using the GMSK modulation method, a signal corresponding to the amplitude information of the transmission data supplied from the comparator 431 instead of the output level designation signal VPL. A changeover switch SW1 for inputting the LDO to the power supply control circuit 221 is provided.
The switch SW1 is provided in a modulation / demodulation circuit (not shown), and is switched by a mode signal MODE instructing a modulation method, for example. The comparator 431 detects the amplitude information signal Vin from the phase amplitude separation circuit 432 that separates the transmission signal IN into the phase information signal Pin and the amplitude information signal Vin, and the output level detection provided on the output side of the high frequency power amplifier circuit 210. The detection signal Vdt from the coupler 240 is compared and a signal corresponding to the potential difference is output. Thus, feedback control is performed so that the output level of the high-frequency power amplifier circuit 210 matches the level of the amplitude information signal Vin. The output of the coupler 240 is frequency-converted by the mixer MIX and supplied to the comparator 431 as the detection signal Vdt through the filter FLT and the amplifier AMP.

  In the EDGE modulation mode, since the output level designation signal VPL is not input to the power supply control circuit 221, the bias voltage generation circuit 222 performs a bias corresponding to the required output level based on the voltage Vdd1 from the power supply control circuit 221. The voltage Vabc cannot be generated. Therefore, a changeover switch SW2 that supplies the bias control circuit 214 with the output level control voltage Vapc supplied from the baseband circuit or the modulation / demodulation circuit instead of the voltage from the bias voltage generation circuit 222 is provided. This change-over switch SW2 is changed over by a mode signal MODE instructing the modulation method.

FIG. 2 shows a circuit configuration example of the high-frequency power amplifier circuit 210.
The high-frequency power amplifier circuit 210 of this embodiment has a structure in which a plurality of field effect transistors are sequentially connected as active elements in a multi-stage configuration. In other words, the first stage transistor Q1 has a three-stage configuration in which the drain terminal of the middle stage transistor Q2 is connected to the gate terminal of the middle stage transistor Q2, and the drain terminal of the middle stage transistor Q2 is connected to the gate terminal of the last stage transistor Q3.

In the high frequency power amplifier circuit 210 of FIG. 2, the high frequency signal Pin is input to the gate terminal of the first stage transistor Q1 via the capacitive element C1, and the drain terminal of the final stage transistor Q3 is connected to the output terminal Pout via the capacitive element C4. The DC component of the high-frequency input signal Pin is cut and the AC component is amplified and output. The output level at this time is controlled by the power supply voltage Vdd1 from the bias circuit 214 and the power supply control circuit 221. The power supply voltage Vdd1 is connected to the drain terminals of the power amplification transistors 211, 212, and 213. In addition, there are other combinations such as 212 and 213 only, 211 and 213 only, or 213 only. An optimal control method for each application is also possible. In this case, the transistor not connected to Vdd1 is connected to a constant voltage power source.
The bias circuit 214 includes resistors R1, R2, and R3. The control voltage Vabc from the bias voltage generation circuit 222 or the output level control voltage Vapc supplied through the switch SW2 is the resistors R1, R2, and R2, respectively. The voltage is supplied to the gates of the transistors Q1, Q2, and Q3 through R3, and bias voltages Vg1, Vg2, and Vg3 are applied. These resistors R 1, R 2, and R 3 function to prevent a high frequency input signal from leaking to the bias voltage generation circuit 222.

  In FIG. 2, reference numerals MS1 to MS6 are microstrip lines that function as inductance elements for matching impedances between stages, and MS7 to MS9 are microstrip lines that match impedances with the power supply control circuit 221. It is. Capacitors C1, C2, C3 and C4 connected in series with the microstrip lines MS1 to MS6 have a function of cutting off the DC voltage of the power supply voltage Vdd1 and the gate bias voltage (Vg1, Vg2, Vg3).

  Although not particularly limited, in the present embodiment, the high-frequency power amplifier circuit 210 is configured such that the final-stage transistor Q3 is composed of discrete components (such as output power MOSFET), and the first-stage and middle-stage transistors Q1 and Q2 and the gate bias voltage. The bias circuit 214 for generating Vg1, Vg2, and Vg3 is configured as a semiconductor integrated circuit on one semiconductor chip.

  The semiconductor integrated circuit and elements such as capacitors C1, C2, C3, and C4 are mounted on a common ceramic substrate to constitute a module. The microstrip lines MS1 to MS9 are formed to have a desired inductance value on a ceramic substrate on which semiconductor chips on which resistors R1 to R3 constituting the transistors Q1 and Q2 and the bias circuit 214 are formed are mounted, for example. It is composed of a conductive layer pattern such as copper.

  In FIG. 2, the bias circuit 214 having the simplest configuration including only the resistors R1 to R3 is shown as an example, but other than this, for example, due to variations in circuits and elements that generate a temperature-compensated bias voltage. A bias circuit including a circuit for correcting a deviation of the bias voltage may be used.

FIG. 3 shows a specific circuit configuration example of the power supply control circuit 221 and the bias voltage generation circuit 222.
In FIG. 3, Vramp is the output level designation signal VPL supplied from the baseband circuit via the switch SW1 or the amplitude information signal LDO supplied from the comparator 431. The power supply control circuit 221 includes an operational amplifier (operational amplifier circuit) OP1 having Vramp as an input, a P-channel MOSFET Q11 controlled by an output of the operational amplifier OP1 and an output voltage Vdd1 taken out from a drain terminal, and the MOSFET Q11. A feedback circuit 223 including a CR circuit that feeds feedback from the drain terminal to the non-inverting input terminal of the operational amplifier OP1, a buffer circuit 224 and a phase compensation circuit 225 provided between the operational amplifier OP1 and the gate terminal of the MOSFET Q11, It comprises a smoothing capacitor C10 that stabilizes the output.

  The output voltage Vdd1 is fed back to the non-inverting input terminal of the operational amplifier OP1 via the CR circuit 223, so that the power supply control circuit 221 of this embodiment outputs a voltage Vdd1 that changes almost linearly with respect to the input voltage Vramp. It is configured. The reason why the P-channel type is used as the output MOSFET Q11 is that the output power supply voltage Vdd1 can be raised close to the power supply voltage Vdd as compared with the N-channel type MOSFET. Thereby, the power loss can be reduced.

The buffer circuit 224 includes a pnp bipolar transistor Q21 having a base terminal connected to the output terminal of the operational amplifier OP1, and a constant current source CI connected to the emitter side of the transistor Q21, and operates as an emitter follower. To do. Since the output MOSFET Q11 is designed to have a large element size so that a large current can flow through the output power FETs Q1 to Q3, the capacitance Cs parasitic on the gate thereof is relatively large. The constant current source CI shown in the figure represents the current supplied from the operational amplifier OP1 to the emitter of the transistor Q21 as a current source.
Therefore, if the buffer circuit 224 is not provided, the operational amplifier OP1 must drive the gate parasitic capacitance Cs. Therefore, when operating in the EDGE modulation mode, the amplitude information signal LDO is input as the input voltage Vramp and changes. The response time is slow. On the other hand, the power supply control circuit 221 of the embodiment includes a buffer circuit 224. When the gate voltage is increased, a current is forcibly supplied from the constant current source CI to the gate parasitic capacitance Cs of the output MOSFET Q11. Is reduced, the current can be drawn from the gate parasitic capacitance Cs by the collector current of the transistor Q21. As a result, high-speed operation is possible.

  The phase compensation circuit 225 includes a capacitor C21 and a resistor R21 connected in parallel between the emitter terminal of the transistor Q21 and the gate terminal of the output MOSFET Q11. Since the phase compensation circuit 225 provides a phase margin to the power supply control circuit 221, the cutoff frequency is improved and the gain, that is, the input amplitude and the output amplitude are increased to a desired frequency when operating in the EDGE modulation mode. The ratio can be made constant.

FIG. 5 shows a simulation of the power supply control circuit 221 of the embodiment having the buffer circuit 224 and the phase compensation circuit 225 by connecting an equivalent resistor (3Ω) instead of the output power FETs Q1 to Q3 to the output terminal of the control voltage Vdd1. The frequency characteristic obtained by the operation is indicated by a chain line A, and the frequency characteristic in the circuit in the case where only the buffer circuit 224 is excluded from the power supply control circuit 221 of the embodiment is indicated by a broken line B. Further, the power supply control of the embodiment is performed. A solid line C represents frequency characteristics in a circuit obtained by removing the phase compensation circuit 225 and the buffer circuit 224 from the circuit 221. From FIG. 5, it can be seen that the cutoff frequency extends to the higher side by inserting the buffer circuit 224 and the phase compensation circuit 225.
In this embodiment, in the EDGE modulation mode, the transmission signal is separated into a phase and an amplitude, the phase is shifted by a PLL circuit (not shown), and the amplitude is controlled by the power control circuit 221 based on the amplitude information signal LDO. Therefore, if the phase is greatly shifted during the amplitude control, the phase shift amount cannot be distinguished from the phase modulation. Therefore, the phase margin is given to the power control circuit 221 as described above. desirable.

  When a P-channel MOSFET is used as the MOSFET Q11 as in the above embodiment, it is desirable to use a pnp type as the bipolar transistor Q21 constituting the buffer circuit 224. This is because if the pnp type is used as the transistor Q21, the gate voltage of the MOSFET Q11 can be increased to a voltage lower than the power supply voltage Vdd by a voltage drop caused by the internal resistance Re of the constant current source CI. If the buffer circuit configured as shown in FIG. 4 using the npn type is used, even if the output of the operational amplifier OP1 swings to the power supply voltage Vdd, the gate voltage of the MOSFET Q11 is higher than the power supply voltage Vdd. This is because the voltage can be raised only to a voltage lower by the emitter-to-emitter voltage Vbe (about 0.7 V), and the output power supply voltage Vdd1 is also lowered accordingly.

  Next, the bias voltage generation circuit 222 shown in FIG. 3 will be described. The bias voltage generation circuit 222 of this embodiment includes an operational amplifier OP2 that is input to the output node n0 of the power supply control circuit 221 via a resistor R31, a non-inverting input terminal of the operational amplifier OP2, and the power supply voltage Vdd. A resistor R32 connected between them, a feedback resistor R33 connected between the output terminal and the inverting input terminal of the operational amplifier OP2, and a constant voltage source connected to each input terminal of the operational amplifier OP2 via resistors R34 and R35. And CV. The constant voltage source CV is configured to give a constant voltage of, for example, 2.2V. Thereby, the bias voltage generation circuit 222 operates as a voltage follower having an offset, and outputs a voltage Vabc proportional to the input voltage Vdd1 according to a proportional constant determined by the resistance ratio of the resistors R31 to R35.

FIG. 6 shows input / output characteristics of the operating voltage control circuit 220 of the embodiment. In the figure, the horizontal axis represents the input voltage Vramp to the power supply control circuit 221, and the vertical axis represents the output voltage Vabc of the bias voltage generation circuit 222. This figure shows the relationship between the input voltage Vramp and the output voltage Vabc when the power supply voltage Vdd is 4.7V, 3.5V, and 2.9V. In FIG. 6, black triangles indicate the relationship between the input voltage Vramp and the output voltage Vabc when the power supply voltage Vdd is 4.7 V, and ◆ marks indicate the input voltage Vramp and the output voltage Vabc when the power supply voltage Vdd is 3.5 V. The symbol ▪ indicates the relationship between the input voltage Vramp and the output voltage Vabc when the power supply voltage Vdd is 2.9V.
In the figure, the initial output voltage (about 1.4 V) when the input voltage Vramp is 0 V is determined by the ratio between the constant voltage of the constant voltage source CV and the resistors R32 to R35. In this way, by applying the initial voltage when the input voltage Vramp is 0 V and changing the bias voltage Vabc output from this voltage, the input voltage Vramp is applied to the input voltage Vramp while providing a desired output level even in a region where the input voltage Vramp is low. The output level can be changed linearly in proportion.

  Note that the change in the output voltage Vdd1 of the power supply control circuit 221 with respect to the input voltage Vramp is substantially the same as in FIG. 6 except that the slope of the straight line is larger than that in FIG. Further, the constant voltage Vapc1 and the resistors R32 to R32 are set so that the output voltage Vabc of the operating voltage control circuit 220 is clamped at a point Q corresponding to the intersection of the input / output temperature characteristic curve at high temperature and the input / output temperature characteristic curve at low temperature. By appropriately setting the ratio of R35, it is possible to generate a bias voltage Vabc that does not change the input / output characteristics of the output power FETs Q1 to Q3 due to temperature compensation, that is, temperature change.

In FIG. 6, the input / output characteristics of the operating voltage control circuit 220 when the bias voltage Vabc is clamped by the voltage at the point Q (for example, 1.6 V) are indicated by a broken line D. Note that the voltage at the point Q varies depending on the circuit configuration, the process used, and the like, and is not limited to 1.6 V as shown in FIG. When the bias voltage Vabc is clamped at the Q point, a stable operation can be ensured with respect to a temperature change. However, the output level is slightly lower and the efficiency is slightly lower in a region where the output level is desired to be larger than when the bias voltage is not clamped. Therefore, it is only necessary to decide whether or not to clamp depending on which characteristic is desired to be prioritized.
By supplying the power supply voltage Vdd1 and the bias voltage Vabc to the high-frequency power amplifier circuit 210 as described above, the output Vout of the high-frequency power amplifier circuit 210 is substantially linear as shown in FIG. 7 with respect to the change in the input voltage Vramp. Change. Further, by supplying the bias voltage Vabc as described above to the bias circuit 214, the efficiency of the high-frequency power amplifier circuit 210 becomes as shown by a solid line a in FIG. On the other hand, when a fixed voltage is applied to the bias circuit 214 instead of the bias voltage Vabc having the characteristic as shown in FIG. 6, the efficiency of the high-frequency power amplifier circuit 210 is as shown by a broken line b in FIG. A comparison between the solid line a and the broken line b shows that the use of the bias voltage generation circuit 222 of this embodiment increases the efficiency of the high-frequency power amplification circuit 210 in the low output region.

  Thus, the efficiency is improved when the fixed bias voltage is applied, and the gate-drain voltage of the output power FETs Q1 to Q3 when the input voltage Vramp is reduced and the power supply voltage Vdd1 is lowered. And the amplification factor of the FET becomes extremely small. On the other hand, when the power supply voltage Vdd1 is lowered as in the embodiment, if the gate bias voltage Vabc is lowered accordingly, the power supply voltage Vdd1 is low. In the region, the gate-drain voltage of the output MOSFETs Q1 to Q3 is kept larger than that in the case of the fixed bias, so that it is considered that the amplification factor of the FET can be prevented from becoming extremely small.

  As can be seen from FIG. 8, by applying the embodiment, the efficiency in the region where the power supply voltage Vdd1 is high is slightly lower than in the case of the fixed bias. However, since mobile phones are often used at low output rather than being used at high output, the efficiency in the low output area is improved as in the embodiment, thereby reducing the total power consumption. The effect of suppressing can be expected.

  FIG. 13 shows another embodiment of the power supply control circuit 221 that generates the power supply voltage Vdd1 applied to the drain terminal of the output power FET in the above embodiment. The power supply control circuit 221 of this embodiment uses a P-channel MOSFET instead of the N-channel MOSFET as the output MOSFET Q11 in the power supply control circuit 221 of the embodiment of FIG. 3, and also uses the emitter terminal of the transistor Q21 and the output MOSFET Q11. Instead of the phase compensation circuit 225 composed of the capacitor C21 and the resistor R21 connected in parallel between the gate terminal of the output MOSFET Q11, the capacitor C23 and the resistor R23 are connected in series between the source terminal of the output MOSFET Q11 and the base terminal of the transistor Q21. The phase compensation circuit 226 connected to is provided.

  In the power supply control circuit 221 of this embodiment, the ratio of the resistance R20 between the non-inverting input terminal of the operational amplifier OP1 and the ground point and the feedback resistance R23 between the non-inverting input terminal of the operational amplifier OP1 and the output node n0. Thus, the gain is determined. Further, the phase compensation circuit 226 is for preventing oscillation of the feedback loop of the entire circuit, and the point A and the output node n0 are in opposite phases, and the capacitor C23 and the resistor are connected from the output node n0 to the base of the transistor Q21. By feeding back an antiphase signal via R23, loop oscillation can be prevented. When the impedance of the capacitor C23 and the resistor R23 is Z0, and the parallel impedance of the output impedance of the operational amplifier OP1 and the input impedance of the buffer PNP transistor Q21 viewed from the phase compensation circuit is Zin, the feedback amount is expressed by Zin / (Zin + Z0). It is. By changing this constant, the frequency characteristics of the circuit can be varied.

FIG. 9 shows an embodiment in which the operating voltage control circuit 220 and the high frequency power amplifier circuit 210 of the above embodiment are mounted on a single ceramic substrate and configured as an RF power module.
In FIG. 9, reference numerals 210a and 210b denote first and middle output power transistors Q1 and Q2 and a bias circuit 214 in the high-frequency power amplifier circuit 210 shown in FIG. 213a and 213b are composed of a discrete component (output power MOSFET), one (upper) for DCS (Digital Cellular System), and the other. (Lower) is for GSM. Reference numeral 220 denotes an operating voltage control circuit having a configuration as shown in FIG. 3 and formed as a semiconductor integrated circuit. In this embodiment, 220 is provided as a common circuit for the DCS power amplifier circuit and the GSM power amplifier circuit. ing.

  Further, in FIG. 9, SW2 inputs an output level control voltage Vapc supplied from a baseband circuit (not shown) or a modulation / demodulation circuit to the operation voltage control circuit 220 instead of the power supply voltage Vdd1 generated by the operation voltage control circuit 220. This is a change-over switch. This change-over switch SW2 is changed over by a mode signal MODE instructing the modulation method supplied from the baseband circuit. As described above, the RF power module of this embodiment is configured to be able to perform GMSK modulation transmission and EDGE modulation transmission in two bands of GSM and DCS, respectively.

Therefore, in the module of this embodiment, the output terminals of the output power MOSFETs Q3a and Q3b are connected to the module output terminals OUTa and OUTb via the capacitors Ca and Cb, and this connection is made on the ceramic substrate. Conductive elements formed by the formed microstrip lines MSa and MSb each having a conductive layer pattern, and formed in the middle of the microstrip lines MSa and MSb as output lines so as to face each other with a dielectric layer interposed therebetween. Couplers 240a and 240b made of body layers are provided.
Of these, 240a is a coupler used in the EDGE modulation mode of the DCS band, and 240b is a coupler used in the EDGE modulation mode of the GSM band. The couplers 240a and 240b can be configured separately from the RF power module. However, as described above, by providing the couplers 240a and 240b on the ceramic substrate on which the high-frequency power amplifier circuit 210 is mounted, the components The number of points can be reduced, and the mobile phone using the module can be downsized.

  Further, in the module of this embodiment, in order to enable transmission of the GMSK modulation method in each of the two bands of GSM and DCS, the initial bias voltage in the transmission of the GSM method and the transmission time in the DCS method are used. Resistors R11 and R12 for switching the initial bias voltage and a changeover switch SW3 are provided. The changeover switch SW3 is controlled to be switched by a band changeover signal BAND between GSM and DCS.

  Reference numeral 250 denotes a power switch circuit for operating or not operating the operating voltage control circuit 220. Txon is a terminal to which a signal for controlling the power switch circuit 250 is input, and Vreg is the power switch. A power supply terminal to which an operating voltage supplied to the operating voltage control circuit 220 through the circuit 250 is applied. When the operating voltage (Vreg) to the operating voltage control circuit 220 is cut off by the power switch circuit 250, the operating voltage control is performed. The operation of the circuit 220 is stopped. In such a state, the power amplifier ICs 210a and 210b and the power MOSFETs Q3a and Q3b are provided with a power supply terminal Vctl so as to operate with a voltage directly supplied from the outside.

FIG. 10 shows a device structure of the RF power module 200 of the embodiment. Note that FIG. 10 does not accurately represent the structure of the RF power module of the embodiment, but is represented as a structural diagram in which some components and wirings are omitted so that the outline thereof can be understood.
As shown in FIG. 10, the main body 10 of the module of the present embodiment has a structure in which a plurality of dielectric plates 11 made of ceramic plates such as alumina are laminated and integrated. On the front or back surface of each dielectric plate 11, a conductor layer 12 made of a conductor such as copper having a predetermined pattern and gold-plated on the surface is provided. Reference numeral 12 a denotes a wiring pattern made of the conductor layer 12. The aforementioned microstrip wirings MSa, MSb, etc. are constituted by this wiring pattern. The couplers 240a and 240b are constituted by, for example, a wiring pattern 12a on the surface of the substrate and a conductor layer 12 inside the substrate disposed in parallel with the dielectric plate 11 in between. Further, in order to connect the conductor layers 12 on the front and back of each dielectric plate 11 or wiring patterns, each dielectric plate 11 is provided with a hole 13 called a through hole, and the hole is filled with a conductor. ing.

  In the module of the embodiment of FIG. 10, six dielectric plates 11 are laminated, and the conductor layer 12 is formed almost entirely on the back side of the first layer, the third layer, and the sixth layer from the top. Each is formed as a ground layer for supplying a ground potential GND. The conductor layers 12 on the front and back surfaces of the remaining dielectric plates 11 are used to configure a transmission line and the like. By appropriately setting the width of the conductor layer 12 and the thickness of the dielectric plate 11, the transmission line is formed so that the impedance is 50Ω.

The first to third dielectric plates 11 are provided with rectangular holes for installing the DCS power amplifier IC 210a and the GSM power amplifier IC 210b. Is inserted and fixed to the bottom of the hole by a bonding material 14, and the fourth-layer dielectric plate 11 corresponding to the bottom of the hole and the dielectric plates 11 below it are called via holes. A hole 15 is provided, and the hole is also filled with a conductor. The conductor in the via hole plays a role of improving the heat radiation efficiency by transferring the heat generated in the IC 210a and IC 210b to the lowermost conductor layer.
The electrodes on the upper surfaces of the ICs 210 a and 210 b and the predetermined conductor layer 12 are electrically connected by bonding wires 31. A plurality of chip-type electronic components 32 such as a capacitance element, a resistance element, a diode element, and a transistor element for configuring the matching circuit, the power switch circuit 250, and the like are provided on the surface of the first dielectric plate 11. It is installed. Of these elements, the capacitive element can be formed inside the substrate by using the conductor layers on the front and back surfaces of the dielectric plate 11 without using electronic components.

As shown in FIG. 11, the external terminals for mounting the module of the embodiment on the printed circuit board for electrical connection are electrode pads 41 made of a conductor layer formed in a predetermined shape on the back surface of the module body 10. Printed by interposing a solder ball or the like between this electrode pad and a corresponding part (a part of the wiring or a conductive layer connected to the wiring) provided on the printed circuit board of the system It is comprised so that it can mount on a board | substrate.
Note that the arrangement and shape of the electrode pads 41 shown in FIG. 11 are merely examples, and the present invention is not limited thereto. In FIG. 11, the conductor layer 12 serving as the ground layer for supplying the ground potential is formed almost entirely on the portion other than the electrode pad 41 as described above.

FIG. 12 shows an embodiment of a dual-band mobile phone system using the RF power module of the above embodiment and capable of transmission / reception by two methods of GSM and DCS.
In FIG. 12, ANT is an antenna for transmitting and receiving signal radio waves, 100 is a front end module, 200 is an RF power module of the above embodiment, and 300 is a device that converts an audio signal into a baseband signal or a received signal into an audio signal. A baseband circuit 400 that generates a modulation method switching signal and a band switching signal, and a modulation / demodulation LSI 400 that downconverts and demodulates a received signal to generate a baseband signal and modulate a transmission signal, FLT1, FLT2 Is a filter that removes noise and interference from the received signal.
Of these, for example, the filter FLT1 is a GSM circuit, and the filter FLT2 is a DCS circuit. The baseband circuit 300 can be composed of a plurality of LSIs and ICs such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory.

  The front-end module 100 is connected to a transmission output terminal of the RF power module 200, impedance matching circuits 121 and 122 for impedance matching, low-pass filters 131 and 132 for attenuating harmonics, and a transmission / reception switching switch circuit 141. 142, capacitors 151 and 152 for cutting a direct current component from a received signal, a demultiplexer 160 for demultiplexing a 900 MHz band GSM signal and a 1.8 GHz band DCS signal, and the like. And the element is mounted on one ceramic substrate, and is comprised as a module. The switching signals CNT1 and CNT2 of the transmission / reception switching switch circuits 141 and 142 are supplied from the baseband circuit 300.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment, three output transistors are connected, but a two-stage configuration or four or more stages may be used. In the above embodiment, it has been described that the output transistor Q3 in the final stage is constituted by another chip. However, like the other output transistors Q1 and Q2, it is formed on the same chip as the bias circuit. Also good.

  Furthermore, in the above-described embodiment, the high-frequency power amplifier circuit capable of two types of communication, the GSM method and the DCS method, has been described. In addition to the above two methods, for example, a 1850 to 1915 MHz band PCS (Personal Communication System). It can be applied to a triple band type high frequency power amplifier circuit that can handle the above signals. In this case, since DCS and PCS have relatively close frequency bands, input / output terminals INa and OUTa and high-frequency power amplifier circuits 210a and 213a in FIG. 9 are used for input and output of DCS and PCS signals and signal amplification. It may be configured to be shared.

It is a block diagram which shows schematic structure of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the specific example of the amplifier circuit part of the high frequency power amplifier circuit of an Example. It is a circuit block diagram which shows the specific example of the operating voltage control circuit of the high frequency power amplifier circuit of an Example. It is a circuit diagram which shows the example of the power supply control circuit examined in this invention. It is a graph which shows the frequency characteristic of the operating voltage control circuit of the high frequency power amplifier circuit of an Example. It is a graph which shows the input-output characteristic of the operating voltage control circuit of an Example. It is a graph which shows the input-output characteristic of the high frequency power amplifier circuit of an Example. It is a graph which shows the relationship between the input voltage and efficiency of the high frequency power amplifier circuit of an Example. It is a block diagram which shows the structural example of RF power module using the high frequency power amplifier circuit of an Example. It is a partial cross section perspective view which shows an example of the device structure of RF power module shown by FIG. It is a bottom view which shows the structural example of the back surface of the module of an Example. It is a block diagram which shows the whole structure of the mobile telephone using the RF power module of an Example. It is a circuit diagram which shows the other Example of a power supply control circuit.

Explanation of symbols

210 High Frequency Power Amplifier 211-213 Output Power FET
214 Bias circuit 220 Operating voltage control circuit 221 Power supply control circuit 222 Bias voltage generation circuit 224 Buffer circuit 225 Phase compensation circuit

Claims (22)

A first power amplification transistor comprising an input terminal and an output terminal for amplifying a first signal having a first frequency;
A second power amplifying transistor for amplifying a second signal having an input terminal and an output terminal and having a second frequency different from the first frequency;
A power supply control circuit that receives the power supply voltage and the third signal and supplies an operating voltage to the output terminals of the first power amplification transistor and the second power amplification transistor according to the third signal; Electronic components for high frequency power amplification characterized by   2. The power supply control circuit according to claim 1, wherein the power supply control circuit includes a first transistor that supplies an operating voltage to output terminals of the first power amplification transistor and the second power amplification transistor. Electronic components for high frequency power amplification.   2. The apparatus according to claim 1, further comprising a bias voltage generation circuit that receives an operating voltage and generates a bias voltage supplied to input terminals of the first power amplification transistor and the second power amplification transistor. The electronic component for high frequency power amplification as described. The power supply control circuit
An amplifier circuit that amplifies a potential difference between a third signal and a feedback signal for setting one output level of the first power amplification transistor and the second power amplification transistor;
A MOSFET having a gate terminal connected to the output terminal of the amplifier circuit, a source terminal connected to a power supply voltage terminal, and a drain terminal connected to the first power amplification transistor and the second power amplification transistor. Prepared,
2. The electronic component for high frequency power amplification according to claim 1, wherein the drain voltage of the MOSFET is fed back to the amplifier circuit as the feedback signal. The power supply control circuit
And a phase compensation circuit provided between a gate terminal of the MOSFET that outputs an operating voltage to an output terminal of the amplifier circuit, the first power amplifier transistor, and the second power amplifier transistor. The electronic component for high frequency power amplification according to claim 4.   A third power amplifying transistor which is subordinately connected to the first power amplifying transistor and supplied with an operating voltage from the power supply control circuit to an output terminal; and a power source which is subordinately connected to the second power amplifying transistor. The high frequency power amplifying electronic component according to claim 1, further comprising a fourth power amplifying transistor to which an operating voltage from the control circuit is supplied to an output terminal. A second terminal provided between a power supply voltage terminal and the bias voltage generation circuit, comprising a control terminal connected to the output of the power supply control circuit, an input terminal, and an output terminal;
The high-frequency power according to claim 1, further comprising a voltage terminal connected to an output terminal of the second transistor and receiving an operating voltage based on a voltage when the second transistor is turned off. Electronic components for amplification.   A selection terminal for receiving a band switching signal; and the selection terminal, the first power amplification transistor, and the second power amplification transistor coupled to the first power amplification transistor and the second power amplification transistor according to the band switching signal. 2. The high frequency power amplification electronic component according to claim 1, further comprising: a power amplification transistor control circuit that activates the power amplification transistor indicated by the band switching signal of the two power amplification transistors. 3.   The first power amplification transistor, the second power amplification transistor, the third power amplification transistor, and the fourth power amplification transistor are MOSFETs or heterojunction bipolar transistors, The electronic component for high frequency power amplification according to claim 6.   The power supply control circuit includes a first transistor used to supply an operating voltage to output terminals of the first power amplification transistor and the second power amplification transistor. The electronic component for high frequency power amplification as described.   9. The power supply control circuit according to claim 8, wherein the power supply control circuit includes a first transistor used to supply an operating voltage to output terminals of the first power amplifying transistor and the second power amplifying transistor. The electronic component for high frequency power amplification as described. A first power amplification transistor comprising an input terminal and an output terminal for amplifying a first signal having a first frequency;
A second power amplifying transistor for amplifying a second signal having an input terminal and an output terminal and having a second frequency different from the first frequency;
A power supply control circuit that receives the power supply voltage and the third signal and supplies an operating voltage to the output terminals of the first power amplification transistor and the second power amplification transistor according to the third signal; High frequency power amplification system characterized by   The power supply control circuit includes a first transistor for supplying an operating voltage to output terminals of the first power amplification transistor and the second power amplification transistor. High frequency power amplification system.   13. The apparatus according to claim 12, further comprising a bias voltage generation circuit that receives an operating voltage and generates a bias voltage supplied to input terminals of the first power amplification transistor and the second power amplification transistor. The described high frequency power amplification system. The power supply control circuit
An amplifier circuit that amplifies a potential difference between a third signal and a feedback signal for setting one output level of the first power amplification transistor and the second power amplification transistor;
A MOSFET having a gate terminal connected to the output terminal of the amplifier circuit, a source terminal connected to a power supply voltage terminal, and a drain terminal connected to the first power amplification transistor and the second power amplification transistor. Prepared,
The high frequency power amplification system according to claim 12, wherein the drain voltage of the MOSFET is fed back to the amplifier circuit as the feedback signal. The power supply control circuit
And a phase compensation circuit provided between a gate terminal of the MOSFET that outputs an operating voltage to an output terminal of the amplifier circuit, the first power amplifier transistor, and the second power amplifier transistor. The high frequency power amplification system according to claim 12.   A third power amplifying transistor which is subordinately connected to the first power amplifying transistor and supplied with an operating voltage from the power supply control circuit to an output terminal; and a power source which is subordinately connected to the second power amplifying transistor. The high-frequency power amplification system according to claim 12, further comprising a fourth power amplification transistor to which an operating voltage from the control circuit is supplied to an output terminal. A second terminal provided between a power supply voltage terminal and the bias voltage generation circuit, comprising a control terminal connected to the output of the power supply control circuit, an input terminal, and an output terminal;
The high frequency power according to claim 12, further comprising a voltage terminal connected to an output terminal of the second transistor and receiving an operating voltage based on a voltage when the second transistor is turned off. Amplification system.   A selection terminal for receiving a band switching signal; and the selection terminal, the first power amplification transistor, and the second power amplification transistor coupled to the first power amplification transistor and the second power amplification transistor according to the band switching signal. 13. The high-frequency power amplification system according to claim 12, further comprising: a power amplification transistor control circuit that activates the power amplification transistor indicated by the band switching signal for two power amplification transistors.   The first power amplification transistor, the second power amplification transistor, the third power amplification transistor, and the fourth power amplification transistor are MOSFETs or heterojunction bipolar transistors, The high frequency power amplification system according to claim 17.   The power supply control circuit includes a first transistor used to supply an operating voltage to output terminals of the first power amplification transistor and the second power amplification transistor. The described high frequency power amplification system.   The power supply control circuit includes a first transistor used to supply an operating voltage to output terminals of the first power amplification transistor and the second power amplification transistor. The described high frequency power amplification system.

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