CN115291667A - Wireless communication device and adaptive bias voltage adjusting circuit - Google Patents

Wireless communication device and adaptive bias voltage adjusting circuit Download PDF

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Publication number
CN115291667A
CN115291667A CN202111582515.3A CN202111582515A CN115291667A CN 115291667 A CN115291667 A CN 115291667A CN 202111582515 A CN202111582515 A CN 202111582515A CN 115291667 A CN115291667 A CN 115291667A
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circuit
coupled
power amplifier
current
bias voltage
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CN115291667B (en
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刘树钰
徐汉儒
杨丰林
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Xiaxin Microelectronics Shanghai Co ltd
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Xiaxin Microelectronics Shanghai Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
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Abstract

A wireless communication device and an adaptive bias voltage adjustment circuit, the adaptive bias voltage adjustment circuit comprising: proportional attenuation circuit, difference feedback circuit and bias voltage generation circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the first input end of the difference feedback circuit is coupled with the input end of the power amplifier, the second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, and the difference feedback circuit is used for acquiring a difference value between an input signal of the power amplifier and an output signal of the proportional attenuation circuit to obtain difference feedback; and the bias voltage generating circuit is used for generating a bias voltage according to the input signal of the power amplifier and the difference feedback. The scheme can keep high linearity when the power amplifier is in a high-power output working state, can improve the transmission efficiency in a low-power output working state, and accurately adjusts the bias voltage.

Description

Wireless communication device and adaptive bias voltage adjusting circuit
Technical Field
The invention relates to the technical field of electronics, in particular to wireless communication equipment and a self-adaptive bias voltage regulating circuit.
Background
Wireless communication devices have been widely used in people's daily life, and radio frequency power amplifiers are the most important modules in wireless communication devices. The Power Amplifier (PA) may amplify the Power of the rf signal generated by the modulation oscillation circuit to achieve a predetermined rf output Power, thereby increasing the coverage of the transmitted signal.
In the prior art, for a power amplifier, it is generally necessary to adopt a control strategy of a bias voltage to optimize the output of the power amplifier, so that a wireless communication device can reduce power consumption of distortion of signal output.
However, the existing bias voltage control strategy has poor linearity when the power amplifier is in a high-power output operating state, has low transmission efficiency in a low-power output operating state, and cannot accurately adjust the bias voltage.
Disclosure of Invention
The embodiment of the invention solves the technical problems that: the existing bias voltage control strategy has poor linearity when the power amplifier is in a high-power output working state, has low emission efficiency in a low-power output working state and cannot accurately adjust the bias voltage.
To solve the above technical problem, an embodiment of the present invention provides a wireless communication device, including: the signal generating module is used for generating a signal to be transmitted; the power amplifier is used for carrying out power amplification on the signal to be transmitted; the signal output module is used for receiving and transmitting the signal to be transmitted after power amplification; an adaptive bias voltage adjustment circuit for providing a bias voltage to the power amplifier, the adaptive bias voltage adjustment circuit comprising: proportional attenuation circuit, difference feedback circuit and bias voltage generation circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation times of the proportional attenuation circuit are equal to the amplification times of the power amplifier; a first input end of the difference feedback circuit is coupled with the input end of the power amplifier, and a second input end of the difference feedback circuit is coupled with the output end of the proportional attenuation circuit, so as to obtain a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit, and obtain difference feedback; the first input end of the bias voltage generating circuit is coupled with the input end of the power amplifier, the second input end of the bias voltage generating circuit is coupled with the output end of the difference value feedback circuit, and the output end of the bias voltage generating circuit is coupled with the control end of the power amplifier, and the bias voltage generating circuit is used for generating a bias voltage according to the input end signal of the power amplifier and the difference value feedback and outputting the bias voltage to the control end of the power amplifier.
Optionally, the input signal of the power amplifier includes a first differential signal and a second differential signal; the bias voltage generating circuit includes: a squaring circuit, a current mirror circuit, and a current-to-voltage conversion circuit, wherein: the first input end of the squaring circuit inputs the first differential signal and the difference feedback, and the second input end of the squaring circuit inputs the second differential signal and the difference feedback; the input end of the current mirror circuit is coupled with the output end of the squaring circuit; the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
Optionally, the current mirror circuit includes: the first PMOS tube and the current amplification unit; wherein: the grid electrode of the first PMOS tube is coupled with the input end of the current amplification unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage; and the output end of the current amplification unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
Optionally, the current mirror circuit further includes: and the register is coupled with the control end of the current amplification unit and is used for inputting the set current amplification factor to the current amplification unit.
Optionally, the squaring circuit includes: first NMOS pipe, second NMOS pipe, wherein: the grid electrode of the first NMOS tube is coupled with the first input end of the squaring circuit, the drain electrode of the first NMOS tube is coupled with the output end of the squaring circuit, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
Optionally, the current-voltage conversion circuit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe and third resistance, fourth resistance, wherein: the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with a low potential; the drain of the fifth NMOS transistor is connected with a preset power supply voltage, the grid of the fifth NMOS transistor is coupled with the input end of the current-voltage conversion circuit, and the source of the fifth NMOS transistor is coupled with the first end of the third resistor; the drain of the sixth NMOS transistor is connected to a preset power voltage, the gate of the sixth NMOS transistor is coupled to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is coupled to the first end of the fourth resistor and the gate of the fourth NMOS transistor; and the second end of the third resistor and the second end of the fourth resistor are both connected with a low potential.
Optionally, the bias voltage generating circuit further includes: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier and used for driving and amplifying the bias voltage, and the input voltage of the input end of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
Optionally, the difference feedback circuit includes a comparison amplifying circuit.
Optionally, a pre-power amplifier is coupled to an input end of the power amplifier; the input end of the preposed power amplifier inputs a target signal and is used for amplifying the target signal to obtain an input signal of the power amplifier.
To solve the above technical problem, an embodiment of the present invention further provides an adaptive bias voltage adjusting circuit, configured to output a bias voltage to a power amplifier, including: proportional attenuation circuit, difference feedback circuit and bias voltage generate circuit, wherein: the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation times of the proportional attenuation circuit are equal to the amplification times of the power amplifier; a first input end of the difference feedback circuit is coupled to the input end of the power amplifier, and a second input end of the difference feedback circuit is coupled to the output end of the proportional attenuation circuit, so as to obtain a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit, and obtain a difference feedback; the first input end of the bias voltage generating circuit is coupled with the input end of the power amplifier, the second input end of the bias voltage generating circuit is coupled with the output end of the difference value feedback circuit, and the output end of the bias voltage generating circuit is coupled with the control end of the power amplifier, so that a bias voltage is generated according to the input end signal of the power amplifier and the difference value feedback and is output to the control end of the power amplifier.
Optionally, the input signal of the power amplifier includes a first differential signal and a second differential signal; the bias voltage generating circuit includes: a squaring circuit, a current mirror circuit, and a current-to-voltage conversion circuit, wherein: the first input end of the squaring circuit inputs the first differential signal and the difference feedback, and the second input end of the squaring circuit inputs the second differential signal and the difference feedback; the input end of the current mirror circuit is coupled with the output end of the squaring circuit; the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
Optionally, the current mirror circuit includes: the first PMOS tube and the current amplification unit; wherein: the grid electrode of the first PMOS tube is coupled with the input end of the current amplification unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage; and the output end of the current amplification unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
Optionally, the current mirror circuit further includes: and the register is coupled with the control end of the current amplification unit and is used for inputting the set current amplification factor to the current amplification unit.
Optionally, the squaring circuit includes: first NMOS pipe, second NMOS pipe, wherein: the grid electrode of the first NMOS tube is coupled with the first input end of the squaring circuit, the drain electrode of the first NMOS tube is coupled with the output end of the squaring circuit, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the second input end of the squaring circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
Optionally, the current-voltage conversion circuit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe and third resistance, fourth resistance, wherein: the drain of the third NMOS transistor is coupled to the input terminal of the current-voltage conversion circuit, and the source of the third NMOS transistor is coupled to the drain of the fourth NMOS transistor; the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with a low potential; the drain of the fifth NMOS transistor is connected with a preset power supply voltage, the grid of the fifth NMOS transistor is coupled with the input end of the current-voltage conversion circuit, and the source of the fifth NMOS transistor is coupled with the first end of the third resistor; the drain of the sixth NMOS transistor is connected to a preset power voltage, the gate of the sixth NMOS transistor is coupled to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is coupled to the first end of the fourth resistor and the gate of the fourth NMOS transistor; and the second end of the third resistor and the second end of the fourth resistor are both connected with a low potential.
Optionally, the bias voltage generating circuit further includes: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier and used for driving and amplifying the bias voltage, and the input voltage of the input end of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
Optionally, the difference feedback circuit includes a comparison amplifying circuit.
Optionally, a pre-power amplifier is coupled to an input end of the power amplifier; the input end of the preposed power amplifier inputs a target signal and is used for amplifying the target signal to obtain an input signal of the power amplifier.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the generated bias voltage is adaptively adjusted through the amplitude of an input signal of the power amplifier and the feedback of a difference value between the input signal of the power amplifier and an output signal of the proportional attenuation circuit, so that the output signal and the input signal of the power amplifier are in a linear relation when the power amplifier outputs high power, the transmission efficiency is high when the power amplifier outputs low power, and the power consumption of the wireless communication equipment can be reduced by keeping the accurate bias voltage.
Drawings
Fig. 1 is a schematic structural diagram of a wireless communication device in an embodiment of the present invention;
FIG. 2 is a schematic diagram of an adaptive bias voltage adjusting circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a bias voltage generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a current-voltage conversion circuit in an embodiment of the present invention.
Detailed Description
As described above, in the conventional bias voltage control strategy, the linearity of the power amplifier is poor in the high-power output operating state, and the bias voltage cannot be accurately adjusted in the low-power output operating state.
In the embodiment of the invention, the generated bias voltage is adaptively adjusted through the amplitude of the input signal of the power amplifier and the feedback of the difference value between the input signal of the power amplifier and the output signal of the proportional attenuation circuit, so that the output signal and the input signal of the power amplifier are in a linear relation when the power amplifier outputs at high power, the transmission efficiency is higher when the power amplifier outputs at low power, and the power consumption can be reduced by keeping the accurate bias voltage.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, a radio communication apparatus in an embodiment of the present invention is presented. In the embodiment of the present invention, the wireless communication device includes a signal generation module 11, a power amplifier 10, a signal output module 12, and an adaptive bias voltage adjustment circuit 13, wherein:
a signal generating module 11, configured to generate a signal to be sent;
a power amplifier 10, configured to perform power amplification on the signal to be transmitted;
the signal output module 12 is configured to receive and transmit a signal to be transmitted after power amplification;
an adaptive bias voltage adjusting circuit 13 for providing a bias voltage to the power amplifier.
In a specific implementation, specific working principles and structures of the signal generation module 11, the power amplifier 10 and the signal output module 12 may refer to the prior art, and are not described in detail in this embodiment of the present invention.
The adaptive bias voltage adjusting circuit 13 provided in the above-described embodiment of the present invention will be described in detail below.
Referring to fig. 2, a schematic structural diagram of an adaptive bias voltage adjusting circuit according to an embodiment of the present invention is shown.
In an embodiment of the present invention, the adaptive bias voltage adjusting circuit may include: proportional attenuation circuit 20, difference feedback circuit 30, and bias voltage generation circuit 40.
In a specific implementation, an input of the proportional attenuation circuit 20 may be coupled to an output of the power amplifier 10, and an output of the proportional attenuation circuit 20 may be coupled to a first input of the difference feedback circuit 30. The output signal of the power amplifier 10 can be attenuated by a corresponding attenuation factor by the proportional attenuation circuit 20.
In the embodiment of the present invention, the attenuation factor of the proportional attenuation circuit 20 may be equal to the amplification factor of the power amplifier 10. The amplification factor of the power amplifier 10 is: the power amplifier 10 amplifies the input signal by N times; the amplification factor of the proportional attenuation circuit 20 is: the proportional attenuation circuit 20 attenuates the signal inputted thereto by N times, that is, the amplitude of the signal outputted from the proportional attenuation circuit 20 is 1/N of the amplitude of the signal inputted thereto.
Unless otherwise stated, the attenuation factor described in the embodiments of the present invention is a theoretical attenuation factor, and the amplification factor is a theoretical amplification factor.
Therefore, if the power amplifier 10 is in the linear amplification state, the input signal of the power amplifier 10 and the output signal of the proportional attenuation circuit 20 are nearly equal. If the power amplifier 10 is in saturation, the saturation is a nonlinear amplification state, so that there is a large difference between the input signal of the power amplifier 10 and the output signal of the proportional attenuator.
In an embodiment of the present invention, a first input terminal of the difference feedback circuit 30 may be coupled to an input terminal of the power amplifier 10, a second input terminal of the difference feedback circuit 30 may be coupled to an output terminal of the proportional attenuation circuit 20, and an output terminal of the difference feedback circuit 30 may be coupled to a first input terminal of the bias voltage generating circuit 40. The difference between the input signal of the power amplifier 10 and the output signal of the proportional attenuation circuit 20 can be obtained by the difference feedback circuit 30, and the difference is amplified accordingly to obtain the difference feedback.
In the embodiment of the present invention, a first input terminal of the bias voltage generating circuit 40 is coupled to the input terminal of the power amplifier 10, a second input terminal of the bias voltage generating circuit 40 is coupled to the output terminal of the difference feedback circuit 30, and an output terminal of the bias voltage generating circuit 40 is coupled to the control terminal of the power amplifier 10. The bias voltage generating circuit 40 may generate a corresponding bias voltage according to the input signal of the power amplifier 10 and the amplitude corresponding to the difference feedback, and output the bias voltage to the control terminal of the power amplifier 10, so as to adjust the bias voltage of the power amplifier 10 in real time.
In the embodiment of the present invention, the input signal of the power amplifier 10 may be a differential signal, which is a first differential signal and a second differential signal. Referring to fig. 3, a schematic structural diagram of a bias voltage generating circuit 40 in the embodiment of the present invention is shown.
In a specific implementation, the bias voltage generating circuit 40 may include a squaring circuit, a current mirror circuit, and a current-to-voltage converting circuit, wherein:
a first input end of the squaring circuit can input a first differential signal and difference feedback, and a second input end of the squaring circuit can input a second differential signal and difference feedback;
an input terminal of the current mirror circuit may be coupled to an output terminal of the squaring circuit;
the input terminal of the current-to-voltage conversion circuit may be coupled to the output terminal of the current mirror circuit, and the output terminal of the current-to-voltage conversion circuit may output the bias voltage to the power amplifier 10.
In an embodiment of the present invention, the current mirror circuit may include a first PMOS transistor MP1 and a current amplifying unit, wherein:
the gate of the first PMOS transistor MP1 may be coupled to the input terminal of the current amplifying unit, the drain of the first PMOS transistor may be coupled to the input terminal of the current mirror circuit and the gate of the first PMOS transistor MP1, and the source of the first PMOS transistor is connected to a predetermined power voltage VDD.
The input end of the current amplifying unit is coupled to the gate of the first PMOS transistor MP1, and the output end of the current amplifying unit may be coupled to the output end of the current mirror circuit. And the current output by the squaring circuit is correspondingly amplified by the current amplifying unit and is output to the current-voltage conversion circuit.
In a specific implementation, the amplification factor of the current amplification unit may be set in advance and input to the current amplification unit. The current amplification unit can amplify the current input by the input end correspondingly according to the set amplification factor. The amplification factor of the current amplification unit can be set according to the actual application scenario.
In the embodiment of the present invention, the current mirror circuit may further include a register circuit. The output terminal of the register circuit may be coupled to the control terminal of the current amplifying unit. The register unit may communicate with the current amplification unit, and the value stored in the register unit may be the amplification factor of the current amplification unit. The current amplification times of the current amplification units can be correspondingly adjusted by setting the numerical values stored in the register units.
For example, the register is a 4-bit register in which a 4-bit binary value is stored. When the binary value stored in the register is 1000, it means that the current amplification factor of the current amplification unit is 8 times. When the binary value stored in the register is 1010, it means that the current amplification factor of the current amplification unit is 10 times.
In a specific application, the value in the register may be set according to a specific application scenario, and is not limited to the above example.
In the embodiment of the present invention, the squaring circuit may include a first NMOS transistor MN1 and a second NMOS transistor MN2, where:
the grid electrode of the first NMOS transistor MN1 can be coupled with the first input end of the squaring circuit, the drain electrode of the first NMOS transistor MN1 can be coupled with the output end of the squaring circuit, and the source electrode of the first NMOS transistor MN1 can be grounded;
the gate of the second NMOS transistor MN2 may be coupled to the second input terminal of the squaring circuit, the drain of the second NMOS transistor MN2 may be coupled to the drain of the first NMOS transistor MN1, and the source of the second NMOS transistor MN2 may be grounded.
In a specific implementation, the squaring circuit may further include a first resistor R1 and a second resistor R2, and a first capacitor C1 and a second capacitor C2.
In the embodiment of the present invention, a first end of the first resistor R1 may be coupled to the gate of the first NMOS transistor MN1, and a second end of the first resistor R1 may be coupled to an output end of the difference feedback circuit 30, so as to input the difference feedback; a first end of the second resistor R2 may be coupled to the gate of the second NMOS transistor MN2, and a second end of the second resistor R2 may also be coupled to an output end of the difference feedback circuit 30 for inputting the difference feedback.
A first differential signal is input to a first end of the first capacitor C1, and a second end of the first capacitor C1 is coupled to a gate of the first NMOS transistor MN1 and a first end of the first resistor R1; a second differential signal is input to a first end of the second capacitor C2, and a second end of the second capacitor C2 is coupled to the gate of the second NMOS transistor MN2 and a first end of the second resistor R2.
In a specific implementation, a pre-power amplifier 50 may be coupled to an input of the power amplifier 10. The input of the pre-power amplifier 50 inputs the target signal. The target signal is amplified by the pre-power amplifier 50, and an output signal of the pre-power amplifier 50 is an input signal of the power amplifier 10. An input of the pre-power amplifier 50 may be coupled to an output of the signal generation module 11.
Referring to fig. 4, a schematic structural diagram of a current-to-voltage conversion circuit in an embodiment of the present invention is shown.
In an embodiment of the present invention, the current-voltage conversion circuit may include: third NMOS pipe MN3, fourth NMOS pipe MN4, fifth NMOS pipe MN5, sixth NMOS pipe MN6 and third resistance R3, fourth resistance R4, wherein:
the drain of the third NMOS transistor MN3 may be coupled to the input terminal of the current-to-voltage conversion circuit, and the source of the third NMOS transistor MN3 may be coupled to the drain of the fourth NMOS transistor MN 4;
the grid electrode of the fourth NMOS transistor MN4 is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS transistor MN4 is connected with a low potential VSS;
the grid electrode of the fifth NMOS transistor MN5 is coupled with the input end of the current-voltage conversion circuit, the drain electrode of the fifth NMOS transistor MN5 is connected with a preset power supply voltage VDD, and the source electrode of the fifth NMOS transistor MN5 is connected with the first end of the third resistor R3;
the drain electrode of the sixth NMOS transistor MN6 is connected with a preset power supply voltage VDD, the grid electrode of the sixth NMOS transistor MN6 is coupled with the drain electrode of the fifth NMOS transistor MN5, and the source electrode of the sixth NMOS transistor MN6 is coupled with the first end of the fourth resistor R4;
the second end of the third resistor R3 and the second end of the fourth resistor R4 are both connected to the low voltage VSS.
In a specific implementation, the bias voltage generating circuit 40 may further include a buffer circuit. An input of the buffer circuit may be coupled to the current-to-voltage conversion circuit and an output of the buffer circuit may be coupled to an output of the power amplifier 10. The input voltage of the input end of the buffer circuit is related to the output voltage of the output end of the current-voltage conversion circuit. In the embodiment of the present invention, the input voltage of the buffer circuit may be equal to the output voltage of the current-voltage conversion circuit.
The bias voltage output by the current-voltage conversion circuit is driven and amplified by the buffer circuit and output to the control terminal of the power amplifier 10. That is, the bias voltage input to the control terminal of the power amplifier 10 may be amplified by the buffer driver.
Referring to fig. 4, the buffer circuit may include a seventh NMOS transistor MN7, and the seventh NMOS transistor MN7 may be formed by connecting a plurality of NMOS transistors in parallel, so as to enhance the driving capability of the buffer circuit.
In the embodiment of the present invention, the current-voltage conversion circuit may further include an eighth NMOS transistor MN8. The drain of the eighth NMOS transistor MN8 is coupled to the drain of the third NMOS transistor MN3 and the gate of the fifth NMOS transistor MN5, and the source of the eighth NMOS transistor MN8 is connected to the low potential VSS.
In the embodiment of the present invention, the current-voltage conversion circuit may further include a ninth NMOS transistor MN9. The drain of the ninth NMOS transistor MN9 is coupled to the gate of the fourth NMOS transistor MN4, and the source of the ninth NMOS transistor MN9 is connected to the low voltage VSS. The working state of the current-voltage conversion unit can be controlled through the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9.
The operation principle of the adaptive bias voltage adjusting circuit provided in the above embodiment of the present invention is explained below.
The target signal PAin is input to the pre-power amplifier 50, and the target signal PAin is a differential signal. The pre-power amplifier 50 amplifies and outputs the target signal PAin, and sets the output signal of the pre-power amplifier 50 to pa _ in, i.e., the input signal of the power amplifier 10 to pa _ in, which has a corresponding amplitude of Vpa _ in. As can be seen from the above embodiments of the present invention, the input signals of the power amplifier 10 include the first differential signal Vpa _ in + and the second differential signal Vpa _ in-.
The voltage corresponding to the difference feedback output by the difference feedback circuit 30 is Vb. Vb is related to the difference between the output signal of the proportional damping circuit 20 and the input signal of the power amplifier 10.
An output terminal of the difference feedback circuit 30 is coupled to a first input terminal of the squaring circuit and a second input terminal of the squaring circuit, the first input terminal of the squaring circuit is input with Vpa _ in + and Vb, and the second input terminal of the squaring circuit is input with Vpa _ in-and Vb.
The Vb + Vpa _ in (Vpa _ in including Vpa _ in + and Vpa _ in-) is converted into a corresponding drain current Id by a squaring circuit and output to a current mirror circuit.
The current mirror circuit amplifies the input current Id. And if the amplification factor of the current Id by the current mirror circuit is k, the current output by the current mirror circuit is k Id. The current output by the current mirror circuit forms a bias voltage V on the grid electrode of the fourth NMOS transistor MN4 through the current-voltage conversion circuit pa_bias And output to the power amplifier 10.
Bias voltage V pa_bias And the amplitude of the first differential signal Vpa _ in + is in a linear relationship, and V PA_bias It can be adjusted by the size of Vb. Setting the amplitude of the first differential signal Vpa _ in + to A/2, then V pa_bias The relationship to amplitude A/2 is:
Figure 213543DEST_PATH_IMAGE001
；
wherein, beta in =1/2μ n C ox *(W/L) in ，β out =1/2μ n C ox *(W/L) out ，μ n Is the electron mobility of NMOS transistor, C ox Is unit area gate oxide capacitance (W/L) in Is the width-length ratio (W/L) of the first NMOS tube MN1 or the second NMOS tube MN2 out Is the width-to-length ratio, V, of the fourth NMOS transistor MN4 TH Setting values and V of Vb in a default state for threshold voltages of a first NMOS transistor MN1 and a second NMOS transistor MN2 TH Close.
In the current-voltage conversion circuit, the conversion relationship of current and voltage can be expressed as:
Figure 130684DEST_PATH_IMAGE002
；
wherein,
Figure 910421DEST_PATH_IMAGE003
the phase angles of Vpa _ in + and Vth-Vb,
Figure 305630DEST_PATH_IMAGE004
is the input signal.
In summary, in the embodiment of the present invention, the amplitude of the input signal of the power amplifier 10 and the feedback of the difference between the input signal of the power amplifier 10 and the output signal of the proportional attenuation circuit 20 are used to adaptively adjust the generated bias voltage, so that the output signal and the input signal of the power amplifier 10 are in a linear relationship when outputting high power, and the accurate bias voltage is maintained when outputting low power to reduce power consumption.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (18)

1. A wireless communication device, comprising:
the signal generating module is used for generating a signal to be transmitted;
the power amplifier is used for carrying out power amplification on the signal to be transmitted;
the signal output module is used for receiving and transmitting the signal to be transmitted after power amplification;
an adaptive bias voltage adjustment circuit for providing a bias voltage to the power amplifier, the adaptive bias voltage adjustment circuit comprising:
proportional attenuation circuit, difference feedback circuit and bias voltage generation circuit, wherein:
the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation times of the proportional attenuation circuit are equal to the amplification times of the power amplifier;
a first input end of the difference feedback circuit is coupled to the input end of the power amplifier, and a second input end of the difference feedback circuit is coupled to the output end of the proportional attenuation circuit, so as to obtain a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit, and obtain a difference feedback;
the first input end of the bias voltage generating circuit is coupled with the input end of the power amplifier, the second input end of the bias voltage generating circuit is coupled with the output end of the difference value feedback circuit, and the output end of the bias voltage generating circuit is coupled with the control end of the power amplifier, so that a bias voltage is generated according to the input signal of the power amplifier and the difference value feedback and is output to the control end of the power amplifier.
2. The wireless communication device of claim 1, wherein the input signal of the power amplifier comprises a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein:
the first input end of the squaring circuit inputs the first differential signal and the difference feedback, and the second input end of the squaring circuit inputs the second differential signal and the difference feedback;
the input end of the current mirror circuit is coupled with the output end of the squaring circuit;
the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
3. The wireless communication device of claim 2, wherein the current mirror circuit comprises: the first PMOS tube and the current amplification unit; wherein:
the grid electrode of the first PMOS tube is coupled with the input end of the current amplification unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage;
and the output end of the current amplification unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
4. The wireless communication device of claim 3, wherein the current mirror circuit further comprises: and the register is coupled with the control end of the current amplification unit and is used for inputting the set current amplification factor to the current amplification unit.
5. The wireless communication device of claim 2, wherein the squaring circuit comprises: first NMOS pipe, second NMOS pipe, wherein:
the grid electrode of the first NMOS tube is coupled with the first input end of the squaring circuit, the drain electrode of the first NMOS tube is coupled with the output end of the squaring circuit, and the source electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is coupled with the second input end of the squaring circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
6. The wireless communication device of claim 2, wherein the current-to-voltage conversion circuit comprises: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe and third resistance, fourth resistance, wherein:
the drain electrode of the third NMOS tube is coupled with the input end of the current-voltage conversion circuit, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with a low potential;
the drain of the fifth NMOS transistor is connected with a preset power supply voltage, the grid of the fifth NMOS transistor is coupled with the input end of the current-voltage conversion circuit, and the source of the fifth NMOS transistor is coupled with the first end of the third resistor;
the drain of the sixth NMOS transistor is connected to a preset power voltage, the gate of the sixth NMOS transistor is coupled to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is coupled to the first end of the fourth resistor and the gate of the fourth NMOS transistor;
and the second end of the third resistor and the second end of the fourth resistor are both connected with a low potential.
7. The wireless communication device of claim 2, wherein the bias voltage generation circuit further comprises: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier and used for driving and amplifying the bias voltage, and the input voltage of the input end of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
8. The wireless communication device of claim 1, wherein the difference feedback circuit comprises a compare-amplify circuit.
9. The wireless communication device of claim 1, wherein a pre-power amplifier is coupled to an input of the power amplifier; the input end of the preposed power amplifier inputs a target signal and is used for amplifying the target signal to obtain an input signal of the power amplifier.
10. An adaptive bias voltage adjustment circuit for outputting a bias voltage to a power amplifier, comprising: proportional attenuation circuit, difference feedback circuit and bias voltage generation circuit, wherein:
the input end of the proportional attenuation circuit is coupled with the output end of the power amplifier; the attenuation times of the proportional attenuation circuit are equal to the amplification times of the power amplifier;
a first input end of the difference feedback circuit is coupled to the input end of the power amplifier, and a second input end of the difference feedback circuit is coupled to the output end of the proportional attenuation circuit, so as to obtain a difference between an input signal of the power amplifier and an output signal of the proportional attenuation circuit, and obtain a difference feedback;
the first input end of the bias voltage generating circuit is coupled with the input end of the power amplifier, the second input end of the bias voltage generating circuit is coupled with the output end of the difference value feedback circuit, and the output end of the bias voltage generating circuit is coupled with the control end of the power amplifier, so that a bias voltage is generated according to the input signal of the power amplifier and the difference value feedback and is output to the control end of the power amplifier.
11. The adaptive bias voltage adjustment circuit of claim 10, wherein the input signals to the power amplifier comprise a first differential signal and a second differential signal; the bias voltage generating circuit includes: square circuit, current mirror circuit and current-voltage conversion circuit, wherein:
the first input end of the squaring circuit inputs the first differential signal and the difference feedback, and the second input end of the squaring circuit inputs the second differential signal and the difference feedback;
the input end of the current mirror circuit is coupled with the output end of the squaring circuit;
the input end of the current-voltage conversion circuit is coupled with the output end of the current mirror circuit, and the output end of the current-voltage conversion circuit outputs the bias voltage.
12. The adaptive bias voltage adjustment circuit of claim 11, wherein the current mirror circuit comprises: the first PMOS tube and the current amplification unit; wherein:
the grid electrode of the first PMOS tube is coupled with the input end of the current amplification unit and the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is coupled with the input end of the current mirror circuit, and the source electrode of the first PMOS tube is connected with a preset power supply voltage;
and the output end of the current amplification unit is coupled with the output end of the current mirror circuit and is used for amplifying and outputting the current output by the square circuit.
13. The adaptive bias voltage adjustment circuit of claim 12, wherein the current mirror circuit further comprises: and the register is coupled with the control end of the current amplification unit and is used for inputting the set current amplification factor to the current amplification unit.
14. The adaptive bias voltage adjustment circuit of claim 11, wherein the squaring circuit comprises: first NMOS pipe, second NMOS pipe, wherein:
the grid electrode of the first NMOS tube is coupled with the first input end of the squaring circuit, the drain electrode of the first NMOS tube is coupled with the output end of the squaring circuit, and the source electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is coupled with the second input end of the square circuit, the drain electrode of the second NMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
15. The adaptive bias voltage adjustment circuit of claim 11, wherein the current-to-voltage conversion circuit comprises: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, sixth NMOS pipe and third resistance, fourth resistance, wherein:
the drain of the third NMOS transistor is coupled to the input terminal of the current-voltage conversion circuit, and the source of the third NMOS transistor is coupled to the drain of the fourth NMOS transistor;
the grid electrode of the fourth NMOS tube is coupled with the output end of the current-voltage conversion circuit, and the source electrode of the fourth NMOS tube is connected with a low potential;
the drain of the fifth NMOS transistor is connected with a preset power supply voltage, the grid of the fifth NMOS transistor is coupled with the input end of the current-voltage conversion circuit, and the source of the fifth NMOS transistor is coupled with the first end of the third resistor;
the drain of the sixth NMOS transistor is connected to a preset power voltage, the gate of the sixth NMOS transistor is coupled to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is coupled to the first end of the fourth resistor and the gate of the fourth NMOS transistor;
and the second end of the third resistor and the second end of the fourth resistor are both connected with a low potential.
16. The adaptive bias voltage adjustment circuit of claim 11, wherein the bias voltage generation circuit further comprises: a buffer circuit; the input end of the buffer circuit is coupled with the current-voltage conversion circuit, the output end of the buffer circuit is coupled with the control end of the power amplifier and used for driving and amplifying the bias voltage, and the input voltage of the input end of the buffer circuit is related to the output voltage of the current-voltage conversion circuit.
17. The adaptive bias voltage adjustment circuit of claim 10, wherein the difference feedback circuit comprises a compare amplifier circuit.
18. The adaptive bias voltage adjustment circuit of claim 10, wherein a pre-power amplifier is coupled to an input of the power amplifier; the input end of the preposed power amplifier inputs a target signal and is used for amplifying the target signal to obtain an input signal of the power amplifier.
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