CN113867465A - LDO (low dropout regulator) module for in-chip adjustable bandwidth - Google Patents
LDO (low dropout regulator) module for in-chip adjustable bandwidth Download PDFInfo
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
An LDO module for on-chip adjustable bandwidth comprises a reference voltage generation circuit, a current bias circuit, a reference current generation circuit, an error comparator circuit and a power tube stage circuit. The error comparator circuit adopts a folding cascode operational amplifier structure; the positive input end of the error comparator circuit is connected with the voltage division position of the output end of the power tube stage circuit to form negative feedback, the reference current generating circuit is connected with the current bias circuit through an In _ p pin, and the negative input end of the error comparator circuit is connected with the output end of the reference voltage generating circuit; the output end of the error comparator circuit is connected with the power tube stage circuit. The reference current is adjusted through the current adjusting function of the reference current generating circuit, and parameters such as bandwidth and swing of the error comparator are controlled, so that compromise selection between transient response and power consumption of the LDO is provided. The module circuit has a simple structure, can be used outside a chip and is easy to integrate in the chip, and can play a stable role under various MOS processes. Under the action of low voltage, the error amplifier can still realize larger gain.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to an LDO module capable of adjusting bandwidth in a chip.
Background
With the advent of bandgap reference voltages, the most widely used reference voltages in LDO chips are all provided by bandgap reference voltages. The load regulation capability of the LDO has a direct relationship with the gain of the error amplifier, and the response speed of the LDO to output voltage changes is limited and influenced by the bandwidth and swing of the error amplifier. Therefore, the design of adjusting the bandwidth of the error amplifier in the LDO is important for the adaptability of the LDO.
When the LDO load current or the power supply voltage jumps, the LDO output voltage changes, and then the process that the LDO returns the output voltage to a stable value through a negative feedback system is called LDO transient response. There are two important indexes of overshoot voltage and recovery time in the LDO, the overshoot voltage represents the maximum change of the output voltage, and the recovery time represents the time required for the LDO output voltage to recover to a stable value. The larger overshoot voltage is likely to cause the breakdown of the MOS tube to cause the chip to fail under the condition of long recovery time. The transient response of the LDO is not only determined by the small signal of the LDO loop, but also relates to the signal-hitting response caused by the fact that amplifiers at each stage in the LDO loop charge and discharge load capacitors. Therefore, it is a hot spot of current LDO research to coordinate the relationship among bandwidth, swing, and power consumption in the error amplifier, and add an auxiliary circuit to improve large signal response.
Disclosure of Invention
The invention aims to provide an LDO module with adjustable bandwidth in a chip.
The purpose of the invention is realized by the following technical scheme: an LDO module for on-chip adjustable bandwidth comprises a reference voltage generation circuit, a current bias circuit, a reference current generation circuit, an error comparator circuit and a power tube stage circuit.
The reference voltage generating circuit is a negative feedback system formed by a resistance feedback network and provides a reference voltage which is smaller than the band-gap reference voltage for the input end of the error comparator circuit.
The current bias circuit is composed of 4 PMOS tubes and 1 NMOS tube and is used for controlling the current of the error comparator.
The reference current generating circuit comprises a current regulating module, a long tail type operational amplifier module and a bias voltage module; the current regulation module comprises a bypass switch consisting of 1 NMOS (N-channel metal oxide semiconductor) tube and an vbt port, 2 series resistors and 1 PMOS (P-channel metal oxide semiconductor) tube, wherein the drain electrode of the PMOS tube is connected with the source electrode of the PMOS tube of the current bias circuit through an LPB (low power bus) pin; the long tail type operational amplifier module consists of a group of differential pair transistors, 4 PMOS (P-channel metal oxide semiconductor) transistors and an NMOS (N-channel metal oxide semiconductor) tail tube Mtail; the bias voltage module is formed by connecting 3 PMOS tubes in series, and provides voltage bias by utilizing an MOS tube voltage division structure, namely all the series-connected tubes are in lining source short circuit and grid drain short circuit.
The error comparator circuit adopts a folding cascode operational amplifier structure; the positive input end of the error comparator circuit is connected with the voltage division position of the output end of the power tube stage circuit to form negative feedback, the reference current generating circuit is connected with the current biasing circuit through an In _ p pin, and the negative input end of the error comparator circuit is connected with the output end of the reference voltage generating circuit; and the output end of the error comparator circuit is connected with the power tube stage circuit.
The power tube stage circuit comprises a power tube Mout and a power compensation module.
Further, the current bias circuit is composed of a PMOS tube Mpt1, a PMOS tube Mpt2, a PMOS tube Mpt3, a PMOS tube Mpt4 and an NMOS tube Mnt 0.
Further, the error comparator circuit is a folded cascode operational amplifier composed of a differential tube Md1, a differential tube Md2, a PMOS tube Mpt5, an NMOS tube Mnt1, an NMOS tube Mnt2, an NMOS tube Mnt3, an NMOS tube Mnt4, a PMOS tube Mpt6, a PMOS tube Mpt7, a PMOS tube Mpt8 and a PMOS tube Mpt 9.
Further, the power compensation module of the power tube stage circuit is to connect the resistor Rb and the capacitor MC0 in series between the gate and the drain of the power tube Mout.
Further, a capacitor MC1 is connected between the source end and the output end of the NMOS transistor Mnt 4.
Further, the current regulation module comprises a bypass switch composed of ports of the NMOS transistor MT and vbt, a resistor Rr, a resistor Rt, and a PMOS transistor MP _ D, wherein the bypass switch is used for bypassing the series resistor Rt to change the current passing through the PMOS transistor MP _ D.
Furthermore, the long-tail type operational amplifier module is a long-tail type cascode operational amplifier composed of a differential tube Mnd1, a differential tube Mnd2, a PMOS tube MPL1, a PMOS tube MPL2, a PMOS tube MPL3, a PMOS tube MPL4 and an NMOS tail tube Mtail.
Furthermore, the bias voltage module is formed by connecting a PMOS tube Mg0, a PMOS tube Mg1 and a PMOS tube Mg2 in series, the substrate is connected with the source electrode, the grid electrode is connected with the drain end, the bias voltage is provided for the MOS tube and the conducting tube of the error comparator circuit through the structure, the comparison reference voltage is provided for the long-tail type operational amplifier module, and the drain electrode of the PMOS tube MP _ D is clamped below a fixed voltage; and an In _ p pin is arranged at the output end of the bias voltage module.
Furthermore, the reference voltage generating circuit is connected with the Vref input terminal through an operational amplifier, a PMOS transistor MPB, resistors Vb1 and Vb2 from a bandgap output terminal VBREG, and the output voltage Vref is VBREG × Vb2/(Vb1+ Vb 2).
Further, an NMOS tube MN _ T is disposed between the In _ p pin and the LPB pin, a gate-on voltage of the NMOS tube MN _ T is provided by a divided voltage In _ p obtained by serially connecting MOS tubes, and a capacitor MC3 is connected between a source end of the NMOS tube MN _ T and GND.
The beneficial effects created by the invention are as follows: by adopting the structure, the reference current is regulated by the current regulating module of the reference current generating circuit, and parameters such as bandwidth and swing amplitude of the error comparator are controlled, so that compromise selection between transient response and power consumption of the LDO is provided. As an LDO structure, the structure has good load adjustment capability and larger load carrying capability, and can supply power to not only an analog chip but also a digital chip. The module circuit has a simple structure, can be used outside a chip and is easy to integrate in the chip, and can play a stable role under various MOS processes. Under the action of low voltage, the error amplifier can still realize larger gain.
Drawings
FIG. 1 is a schematic diagram of a current bias circuit, an error comparator circuit, and a power transistor stage circuit according to the present invention.
FIG. 2 is a schematic diagram of a reference current generating circuit portion according to the present invention.
Fig. 3 is a schematic diagram of a reference voltage generating circuit portion of the present invention.
Detailed Description
An LDO module for on-chip adjustable bandwidth comprises a reference voltage generating circuit 1, a current bias circuit 2, a reference current generating circuit 5, an error comparator circuit 3 and a power tube stage circuit 4.
As shown in fig. 3, the reference voltage generating circuit 1 is a negative feedback system formed by a resistor feedback network, and provides a reference voltage smaller than the bandgap reference voltage to the input terminal of the error comparator circuit.
Vref is used as a voltage comparison reference voltage, and since Vref is smaller than the Bandgap reference voltage, the voltage is obtained by resistive voltage division of the Bandgap reference, and since Bandgap has no load capacity, it cannot be directly divided by series resistance at the Bandgap output terminal. Therefore, the reference voltage generating circuit 1 shown in fig. 3 is specially designed, and specifically, the bandgap output terminal VBREG is connected to the Vref input terminal through the operational amplifier, the PMOS transistor MPB, and the resistors Vb1 and Vb 2. This circuit outputs a voltage Vref that is smaller than the bandgap reference voltage (VBREG × Vb2/(Vb1+ Vb 2).
The structures of the current bias circuit 2, the error comparator circuit 3 and the power tube stage circuit 4 are shown in fig. 1.
The current bias circuit 2 is composed of a PMOS tube Mpt1, a PMOS tube Mpt2, a PMOS tube Mpt3, a PMOS tube Mpt4 and an NMOS tube Mnt0 and is used for controlling the current of the error comparator.
The error comparator circuit 3 adopts a folding cascode operational amplifier structure; the folded cascode operational amplifier is composed of a pair of PMOS tubes Md1 and Md2 serving as differential pair tubes, a PMOS tube Mpt5, an NMOS tube Mnt1, an NMOS tube Mnt2, an NMOS tube Mnt3, an NMOS tube Mnt4, a PMOS tube Mpt6, a PMOS tube Mpt7, a PMOS tube Mpt8 and a PMOS tube Mpt 9. The positive input end of the error comparator circuit 3 is connected with the output end of the reference voltage generating circuit 1 through an In _ p pin, and the negative input end of the error comparator circuit is connected with the output end of the bias voltage module 51 of the reference current generating circuit 5; the output end of the error comparator circuit 3 is connected with the power tube stage circuit 4.
The power tube stage circuit 4 includes a power tube Mout and a power compensation module. The power compensation module is formed by serially connecting a resistor Rb and a capacitor MC0 between the grid and the drain of a power tube Mout for frequency compensation, wherein Rb is a zero adjusting resistor, and MC0 is a MOS capacitor.
As shown in fig. 2, the reference current generating circuit 5 includes a current adjusting module 51, a long tail operational amplifier module 52, and a bias voltage module 53.
The current adjusting module 51 includes a bypass switch composed of NMOS transistor MT and vbt ports, a resistor Rr, a resistor Rt, and a PMOS transistor MP _ D. The resistor Rr is connected in series with the resistor Rt, and a bypass switch composed of an NMOS tube and an vbt port is used for bypassing the series resistor Rt and changing the current passing through the PMOS tube MP _ D, so that the current of an error amplifier in the LDO structure is changed to achieve the purpose of adjusting the loop bandwidth. The source electrode of the PMOS tube MP _ D is connected with the drain electrode of the current bias circuit PMOS tube Mpt4 through an LPB pin;
the long-tail operational amplifier module 52 is a long-tail operational amplifier composed of an NMOS transistor Mnd1 and an NMOS transistor Mnd2 as a differential pair transistor, a PMOS transistor MPL1, a PMOS transistor MPL2, a PMOS transistor MPL3, and a PMOS transistor MPL 4.
The bias voltage module 53 is formed by connecting a PMOS tube Mg0, a PMOS tube Mg1 and a PMOS tube Mg2 in series, the substrate is connected with the source electrode, the grid electrode is connected with the drain electrode, bias voltage is provided for the MOS tube and the conducting tube of the error comparator circuit through the structure, comparison reference voltage and bias voltage are provided for the long tail type operational amplifier module, the drain electrode of the PMOS tube MP _ D is clamped under fixed voltage, and bias voltage is provided for the tail NMOS tube Mtail; and an In _ p pin is arranged at the output end of the bias voltage module.
An NMOS tube MN _ T is arranged between the In _ p pin and the LPB pin, the grid breakover voltage of the NMOS tube MN _ T is provided by a partial voltage In _ p obtained by the series connection of MOS tubes, a capacitor MC3 is connected between the source end of the NMOS tube MN _ T and GND, and the grid voltages of Mnt3 and Mnt4 are also provided by an In _ p end.
The capacitor MC1 is connected between the source of the NMOS transistor Mnt4 and the output end VOUT to be used as nested compensation, so that a loop is stabilized and oscillation is avoided.
The working principle of the invention is as follows: when the LDO works normally, the Vref is used as a reference voltage to provide a comparison voltage for the divided voltage of the output end, and a negative feedback closed-loop system is formed through a resistance feedback network. When the voltage at the output end of the LDO is reduced, a feedback signal is provided through a resistance feedback network to be compared with a reference voltage, so that the voltage at the equidirectional input end of the error amplifier is reduced, the grid voltage of the power tube Mout is adjusted, more current is provided for the power tube to the outside, and the voltage at the VOUT end is raised; similarly, when the output end VOUT of the LDO rises, a feedback signal is provided through the resistance feedback network, so that the voltage of the in-phase input end rises, the in-phase input end voltage is compared with the reference voltage of the reverse phase input end of the error comparator, the output end signal of the error comparator is adjusted, namely the grid voltage of the Mout tube is increased, the power tube is driven to reduce the externally provided current, and the voltage of the VOUT is reduced. The transient response of the LDO to the change of the output voltage is limited and influenced by the bandwidth and the swing amplitude in the error amplifier, the essence of the error amplifier is a folding type cascade operational amplifier, and parameters such as the bandwidth and the swing amplitude of the operational amplifier are functions of the reference current. In fig. 1, the series branch of Mpt3 and Mpt4 is a reference current branch of the LDO error comparator, and is connected to the source terminal of the MP _ D transistor in fig. 2 through the LPB, and the reference current is selected under the action of the bypass switch transistor MT. The operating current of the error amplifier of fig. 1 is mirror-copied by the reference current to control the bandwidth and swing and gain of the error amplifier. The reference voltage in fig. 2 can be obtained by the serial voltage division of PMOS transistors, and the drain voltage of the MP _ D transistor is clamped at a certain stable value under the action similar to the LDO circuit structure, so that a precise and controllable reference current can be obtained. Under the voltage selection of vbt, the circuit can provide two reference currents, thereby enlarging the working range of the LDO and enabling a user to autonomously select a working mode under different conditions. In fig. 3, a reference voltage generating circuit is proposed for providing a stable and accurate reference voltage smaller than the bandgap reference voltage, which is also based on the principle of forming a negative feedback system to output a stable voltage through a resistive feedback network.
Claims (8)
1. An LDO module for on-chip adjustable bandwidth, wherein the LDO circuit comprises a reference voltage generating circuit, a current bias circuit, a reference current generating circuit, an error comparator circuit and a power tube stage circuit;
the reference voltage generating circuit is a negative feedback system formed by a resistance feedback network and provides a reference voltage which is less than the band-gap reference voltage for the input end of the error comparator circuit;
the current bias circuit consists of 4 PMOS tubes and 1 NMOS tube and is used for controlling the current of the error comparator;
the reference current generating circuit comprises a current regulating module, a long tail type operational amplifier module and a bias voltage module;
the current regulation module comprises a bypass switch consisting of 1 NMOS (N-channel metal oxide semiconductor) tube and an vbt port, 2 series resistors and 1 PMOS (P-channel metal oxide semiconductor) tube, wherein the drain electrode of the PMOS tube is connected with the source electrode of the PMOS tube of the current bias circuit through an LPB (low power bias) pin;
the long tail type operational amplifier module is a long tail type cascode operational amplifier formed by a group of differential pair transistors, 4 PMOS transistors and an NMOS (N-channel metal oxide semiconductor) tube;
the bias voltage module is formed by connecting 3 PMOS tubes in series, and provides voltage bias by utilizing an MOS tube voltage division structure;
the error comparator circuit adopts a folding cascode operational amplifier structure; the positive input end of the error comparator circuit is connected with the voltage division position of the output end of the power tube stage circuit to form negative feedback, the reference current generating circuit is connected with the current biasing circuit through an In _ p pin, and the negative input end of the error comparator circuit is connected with the output end of the reference voltage generating circuit; the output end of the error comparator circuit is connected with the power tube stage circuit;
the power tube stage circuit comprises a power tube Mout and a power compensation module.
2. The LDO module of claim 1, wherein the error comparator circuit is a folded cascode operational amplifier composed of a differential transistor Md1, a differential transistor Md2, a PMOS transistor Mpt5, an NMOS transistor Mnt1, an NMOS transistor Mnt2, an NMOS transistor Mnt3, an NMOS transistor Mnt4, a PMOS transistor Mpt6, a PMOS transistor Mpt7, a PMOS transistor Mpt8, and a PMOS transistor Mpt 9.
3. The LDO module according to claim 1, wherein the power compensation module of the power tube stage circuit is formed by connecting a resistor Rb and a capacitor MC0 in series between the gate and the drain of the power tube Mout.
4. The LDO module as claimed in claim 2, wherein a capacitor MC1 is connected between the source terminal of the NMOS transistor Mnt4 and the output terminal VOUT.
5. The LDO module of claim 1, wherein the current regulation module comprises a bypass switch having ports of NMOS transistor MT and vbt, a resistor Rr, a resistor Rt connected in series, and a PMOS transistor MP _ D.
6. The LDO module of claim 1, wherein the bias voltage module is formed by connecting a PMOS transistor Mg0, a PMOS transistor Mg1 and a PMOS transistor Mg2 In series In such a way that a substrate is connected to a source, a gate is connected to a drain, and an In _ p pin is provided at an output terminal of the bias voltage module.
7. The LDO module according to claim 1, wherein the reference voltage generating circuit is connected from the bandgap reference module bandgap output terminal VBREG to the Vref input terminal via the operational amplifier, the PMOS transistor MPB, the resistors Vb1, Vb2, and the output voltage Vref is VBREG × Vb2/(Vb1+ Vb 2).
8. The LDO module of claim 6, wherein an NMOS transistor MN _ T is disposed between the In _ p pin and the LPB pin, a gate turn-on voltage of the NMOS transistor MN _ T is provided by a divided voltage In _ p obtained by a MOS transistor In series, and a capacitor MC3 is connected between a source terminal and GND.
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| CN202111191089.0A CN113867465B (en) | 2021-10-13 | 2021-10-13 | LDO (low dropout regulator) module for in-chip adjustable bandwidth |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116430945A (en) * | 2023-06-12 | 2023-07-14 | 珠海智融科技股份有限公司 | Low dropout linear voltage stabilizing circuit and power supply equipment |
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| US20120293149A1 (en) * | 2011-05-17 | 2012-11-22 | Stmicroelectronics (Rousset) Sas | Device for Generating an Adjustable Bandgap Reference Voltage with Large Power Supply Rejection Rate |
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| CN108052153A (en) * | 2018-01-26 | 2018-05-18 | 成都市海芯微纳电子科技有限公司 | The LDO linear voltage regulators of New-type CMOS structure |
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2021
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Patent Citations (5)
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| US20120293149A1 (en) * | 2011-05-17 | 2012-11-22 | Stmicroelectronics (Rousset) Sas | Device for Generating an Adjustable Bandgap Reference Voltage with Large Power Supply Rejection Rate |
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| CN108052153A (en) * | 2018-01-26 | 2018-05-18 | 成都市海芯微纳电子科技有限公司 | The LDO linear voltage regulators of New-type CMOS structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116430945A (en) * | 2023-06-12 | 2023-07-14 | 珠海智融科技股份有限公司 | Low dropout linear voltage stabilizing circuit and power supply equipment |
| CN116430945B (en) * | 2023-06-12 | 2023-09-01 | 珠海智融科技股份有限公司 | Low dropout linear voltage stabilizing circuit and power supply equipment |
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