CN219392541U - Low dropout linear voltage regulator and power supply - Google Patents

Abstract

A low dropout linear regulator and a power supply, the low dropout linear regulator includes: an error amplifier, a buffer, a phase compensation unit, a feedback unit and an adjustment transistor; the adjusting transistor is connected with the output voltage end and is used for providing output voltage for a load; the feedback unit is used for detecting the change of the output voltage and providing a feedback signal for the error amplifier according to the change; the error amplifier is used for receiving the reference voltage signal and the feedback signal, amplifying the difference value of the reference voltage signal and the feedback signal to obtain a first amplified signal, and outputting the first amplified signal to the buffer; the buffer is used for carrying out secondary amplification on the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the adjusting transistor; the phase compensation unit is used for realizing frequency compensation; the buffer includes a push-pull unit for increasing a slew rate of the on-state and the off-state of the tuning transistor. The transient response characteristic and stability of the low dropout linear voltage regulator are improved.

Description

Low dropout linear voltage regulator and power supply

Technical Field

The present disclosure relates to integrated circuit technology, and more particularly, to a low dropout linear regulator and a power supply.

Background

The low dropout linear regulator voltage (Low Dropout Regulator, LDO) is a buck type direct current linear regulator, has the advantages of low cost, small output noise, simple circuit structure, high integration level, small occupied chip area and the like, becomes an important circuit in a power management chip, and has wide application in the power supply field of electronic products such as computers, communication, instruments, consumer electronics, camera monitoring and the like.

Conventional LDOs guarantee circuit stability by employing off-chip capacitors. However, for on-chip applications, LDOs with no off-chip capacitance are often employed in order to reduce the area of the chip and printed circuit board. In portable electronic devices, in order to reduce power consumption and extend battery life, it is necessary to design LDOs with ultra-low power supply voltages, for example, 0.5V or less. For this reason, the conventional design method is to use a large-sized P-type transistor as a power device. This can lead to a significant increase in gate parasitic capacitance, resulting in poor LDO stability and transient characteristics. In addition, in low load current applications, the stability of the LDO is limited by the load current.

For on-chip applications, how to improve the stability and transient characteristics of the LDO is an important technical problem that the art is constantly working to solve.

Disclosure of Invention

In view of the above, embodiments of the present application provide a low dropout linear regulator and a power supply for solving at least one of the problems in the background art.

In a first aspect, an embodiment of the present application provides a low dropout linear regulator, including: an error amplifier, a buffer, a phase compensation unit, a feedback unit and an adjustment transistor connected between the reference voltage input terminal and the output voltage terminal;

the adjusting transistor is connected with the output voltage end and is used for providing output voltage for a load;

the feedback unit is used for detecting the change of the output voltage and providing a feedback signal for the error amplifier according to the change;

the error amplifier is used for receiving a reference voltage signal and the feedback signal, amplifying the difference value between the reference voltage signal and the feedback signal to obtain a first amplified signal, and outputting the first amplified signal to the buffer;

the buffer is connected between the error amplifier and the adjusting transistor and is used for secondarily amplifying the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the adjusting transistor;

the phase compensation unit is respectively connected between the output voltage end and the error amplifier and is used for realizing frequency compensation;

the buffer includes a push-pull unit for increasing slew rates of on-state and off-state of the tuning transistor.

With reference to the first aspect of the present application, in an optional implementation manner, the push-pull unit includes at least a sixth P-type transistor and a ninth N-type transistor; the buffer further includes a first signal dependent current source for providing a bias current to the sixth P-type transistor in accordance with the first amplified signal.

With reference to the first aspect of the present application, in an optional implementation manner, the buffer further includes a first gain unit, configured to gain the first amplified signal to obtain a first gain signal, and output the first gain signal to the gate of the sixth P-type transistor.

With reference to the first aspect of the present application, in an optional implementation manner, the first gain unit includes a fifth P-type transistor; the first signal-dependent current source includes a seventh P-type transistor, an eighth N-type transistor, and a ninth N-type transistor;

the grid electrode of the fifth P-type transistor is connected with the output end of the error amplifier, the drain electrode of the fifth P-type transistor is connected with the grid electrode of the sixth P-type transistor, and the source electrode of the fifth P-type transistor is connected with the power supply voltage;

the source electrode of the seventh P-type transistor is connected with the power supply voltage, and the drain electrode of the seventh P-type transistor is connected with the drain electrode of the eighth N-type transistor; the source electrode of the eighth N-type transistor is grounded, and the grid electrode of the eighth N-type transistor is connected with the drain electrode of the eighth N-type transistor and the grid electrode of the ninth N-type transistor; the source electrode of the ninth N-type transistor is grounded; and the drain electrode of the sixth P-type transistor and the drain electrode of the ninth N-type transistor are connected with the grid electrode of the adjusting transistor.

With reference to the first aspect of the present application, in an optional implementation manner, the push-pull unit includes a sixth P-type transistor and a ninth N-type transistor; the buffer further includes a second signal dependent current source; the second signal dependent current source is configured to provide a bias current to the ninth N-type transistor in accordance with the first amplified signal.

With reference to the first aspect of the present application, in an optional implementation manner, the buffer further includes a second gain unit, configured to gain the first amplified signal to obtain a second gain signal, and output the second gain signal to the gate of the ninth N-type transistor.

With reference to the first aspect of the present application, in an optional implementation manner, the second gain unit includes a seventh P-type transistor; the second signal related current source comprises a fifth P-type transistor, a sixth P-type transistor and a twelfth N-type transistor;

the grid electrode of the seventh P-type transistor is connected with the output end of the error amplifier, the source electrode of the seventh P-type transistor is connected with the power supply voltage, and the drain electrode of the seventh P-type transistor is connected with the grid electrode of the ninth N-type transistor;

the grid electrode of the fifth P-type transistor is connected with the output end of the error amplifier, the drain electrode of the fifth P-type transistor is connected with the grid electrode of the sixth P-type transistor, and the source electrode of the fifth P-type transistor is connected with the power supply voltage; the drain electrode of the twelfth N-type transistor is connected with the drain electrode of the fifth P-type transistor, the grid electrode of the twelfth N-type transistor receives a reference current signal, and the source electrode of the twelfth N-type transistor is grounded; the source electrode of the sixth P-type transistor is connected with the power supply voltage, and the drain electrode of the sixth P-type transistor is connected with the drain electrode of the ninth N-type transistor; and the drain electrode of the sixth P-type transistor and the drain electrode of the ninth N-type transistor are connected with the grid electrode of the adjusting transistor.

With reference to the first aspect of the present application, in an optional implementation manner, the low dropout linear regulator further includes an enable signal control module, where the enable signal control module is configured to control a voltage output of the output voltage terminal.

With reference to the first aspect of the present application, in an alternative embodiment, the enable signal control module includes a first inverter, a second inverter, and a transmission gate connected between an enable signal input terminal and an output voltage terminal; the transmission gate includes a thirteenth P-type transistor and a fourteenth N-type transistor;

the first inverter and the second inverter are connected in series and are used for respectively generating two paths of opposite control signals to respectively control the thirteenth P-type transistor and the fourteenth N-type transistor so as to control the on and off of the transmission gate.

In a second aspect, an embodiment of the present application provides a power supply, including the low dropout linear regulator according to any one of the first aspects.

According to the low dropout linear voltage regulator and the power supply, the push-pull unit is arranged in the buffer, the transistors M6 and M9 of the push-pull unit are controlled to be respectively turned on and turned off under different change states of rapid rising and falling of the output voltage, so that the adjusting transistors are respectively discharged and charged, even if the output capacitor is not added outside the LDO, the LDO can cope with the instantaneous change of the load, and the transient response characteristic of the LDO is improved. Meanwhile, the push-pull unit moves the pole P3 at the output voltage terminal 200 in the high frequency direction, so that the LDO has stable output without any minimum load current requirement. Therefore, the problem that the traditional LDO is limited by the minimum load current and has poor stability under the condition of no minimum load current requirement is solved, and the stability of the LDO is improved.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a related art low dropout linear regulator;

FIG. 2 is a schematic diagram of an overall framework of an LDO according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an overall framework of an LDO according to another embodiment of the present disclosure;

FIG. 4 is a circuit diagram of an LDO according to an embodiment of the present application;

FIG. 5 is a first equivalent circuit diagram of an LDO according to an embodiment of the present application;

FIG. 6 is a second equivalent circuit diagram of an LDO in an embodiment of the present application;

FIG. 7 is a circuit diagram of an enable signal control module according to an embodiment of the present application;

fig. 8 is a working effect diagram of the enable signal control module in an embodiment of the present application.

Detailed Description

In order to make the technical solution and the beneficial effects of the present application more obvious and understandable, the technical solution in the embodiments of the present application will be clearly and completely described by way of listing specific embodiments, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor. When "first" is described, it does not necessarily mean that "second" is present; and when "second" is discussed, it does not necessarily mean that the first element, component, region, layer or section is present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The meaning of "a plurality of" is two or more, unless specifically defined otherwise. It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, but do not preclude the presence or addition of one or more other features. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

It is to be understood that in the context of this application "connected" means that the connected end and the connected end have electrical signals or data transfer to each other, and can be understood as "electrically connected", "communicatively connected" or the like. In the context of this application, "a is directly connected to B" means that no other components than wires are included between a and B.

FIG. 1 shows a related art low dropout linear regulator, which comprises an error amplifier EA, a power tube, and a feedback resistor R _f1 、R _f2 Load capacitor C _L The composition is formed. Feedback resistor R _f1 、R _f2 And forming a partial pressure feedback network. The divided voltage is fed back to an inverting input of an Error Amplifier (EA), and a non-inverting input of the Error amplifier EA receives the reference voltage Vref. Error amplifier EA can amplify the difference between the feedback voltage and the reference voltage and output the difference to the grid electrode of the power tube, and the power tube is driven to adjust the output current, so that the voltage output by the LDO is ensured to be stable in a rated value range.

When the load of the LDO increases, the load current I _load The pumping load of the load capacitor can lead the voltage output by the LDO to drop, and a negative feedback network consisting of the feedback resistor, the EA and the power tube acts at the moment to increase the voltage of the grid electrode of the power tube, thereby increasing the charging current of the power tube to the load capacitor and leading the output of the LDO to be recovered to a normal value. Otherwise, when the output of the LDO is jumped from heavy load to light load, the negative feedback loop can also reduce the charging current of the power tube to the load capacitor, and release the charge on the load capacitor through the path from the feedback resistor to the ground, so that the output of the LDO is restored to a normal value.

The conventional LDO circuit structure has the following defects: the transient characteristic of the LDO is enhanced by adopting the large capacitor CL added on the chip, along with the increase of load current, the frequency of the primary pole of the circuit is increased, the position of the secondary primary pole is not moved, the loop bandwidth GBW of the circuit is increased, and the phase margin is reduced, so that the loop stability is poor. For the LDO without an off-chip capacitor, no additional energy storage element provides instantaneous current phase compensation for the load when the load changes, the output voltage is completely regulated by regulating the power tube, and the transient characteristic of the LDO is limited by the reaction speed of the power tube. For ultra-low supply voltage designs, the supply voltage is, for example, 0.5V or less. For this reason, the conventional design method is to use a large-sized P-type transistor as a power device. This can lead to a significant increase in gate parasitic capacitance, resulting in poor LDO stability and transient characteristics. In addition, in low load current applications, the stability of the LDO is limited by the load current.

The embodiment of the present application provides a low dropout linear regulator, referring to fig. 2, including an error amplifier 10, a buffer 20, a regulating transistor 30, a feedback unit 40 and a phase compensation unit 50 connected between a reference voltage input terminal 100 and an output voltage terminal 200.

The regulating transistor 30 is connected to the output voltage terminal 200 for providing an output voltage to a load (not shown). Alternatively, the adjustment transistor may be a power transistor of various types, such as a power transistor (GTR), a power field effect transistor (power MOSFET), a turn-off thyristor (GTO), an Insulated Gate Bipolar Transistor (IGBT), a MOS Control Thyristor (MCT), an electrostatic induction transistor (SIT), an electrostatic induction thyristor (SITH), an Integrated Gate Commutated Thyristor (IGCT), or the like.

The feedback unit 40 is configured to detect a change in the output voltage and provide a feedback signal to the error amplifier 10 based on the change. The signal input 42 of the feedback unit 40 is connected to the output voltage terminal 200 and the feedback signal output 41 of the feedback unit 40 is connected to the second input 102 of the error amplifier 10. The ground terminal 43 of the feedback unit 40 is grounded. Optionally, the feedback unit adopts a voltage division feedback network.

The error amplifier 10 is configured to receive a feedback signal of the reference voltage signal and the output voltage, amplify a difference between the reference voltage signal and the feedback signal, obtain a first amplified signal, and then output the first amplified signal to the buffer 20. The error amplifier 10 comprises a first signal input 101, a second signal input 102 and a signal output 103. A first signal input 101 of the error amplifier 10 is connected 100 to the reference voltage input for receiving a reference voltage signal. The second signal input 102 of the error amplifier 10 is connected to the feedback signal output 41 for obtaining the output voltage V _out Is provided. The first amplified signal is output to the buffer 20 via the output 103 of the error amplifier 10.

The buffer 20 is connected between the error amplifier 10 and the adjustment transistor 30, and is used for secondarily amplifying the first amplified signal to obtain a second amplified signal, and then outputting the second amplified signal to the adjustment transistor 30. Buffer 20 constitutes a low voltage embedded gain stage of the LDO.

The phase compensation unit 50 is connected between the output voltage terminal 200 and the output terminal 103 of the error amplifier 10, respectively, for achieving frequency compensation. The phase compensation unit 50 includes a capacitive device. Optionally, the phase compensation unit 50 includes a miller compensation capacitor C _m 。

The buffer 20 comprises a push-pull unit for increasing the slew rate of the on-state and the off-state of the tuning transistor. The push-pull unit comprises at least two transistors with different polarities and same parameters, and the push-pull mode is used for controlling the adjusting transistor to charge and discharge respectively under different change states of the output voltage, so that the state conversion rate of the on and off states of the adjusting transistor is greatly improved. Optionally, the at least two transistors of different polarities include a P-type transistor M6 and an N-type transistor M9.

The working principle of the LDO is as follows:

when the load current suddenly increases, the output voltage V of the LDO _out Rapidly decline. The feedback unit 40 detects the output voltage V _out After a change of (a) generates an output voltage V _out And the feedback signal which is rapidly reduced is output to the error amplifier. The error amplifier outputs the feedback signal V _fb And reference voltage signal V _ref And the difference of the first amplified signal is obtained and outputted to the buffer 20. Reaction output voltage V _out The rapidly falling first amplified signal causes the transistors M6 and M9 of the push-pull unit to be in an off and on state, respectively. Thus, the gate of the adjustment transistor 30 discharges through M9, and the gate voltage of the power transistor 30 is reduced to raise the output voltage of the LDO, so as to maintain the stability of the output voltage.

Similarly, when the load current suddenly drops, the output voltage of the LDO rapidly rises. The feedback unit 40 detects the output voltage V _out After a change of (a) generates an output voltage V _out And the feedback signal which rises rapidly is output to the error amplifier. The error amplifier outputs the feedback signal V _fb And reference voltage signal V _ref And the difference of the first amplified signal is obtained and outputted to the buffer 20. Reaction output voltage V _out The fast rising first amplified signal causes the transistors M6 and M9 of the push-pull unit to be turned on and off, respectively, and the transistor M6 injects a current to charge the gate of the adjusting transistor 30, resulting in the gate voltage of the adjusting transistor 30 being raised to reduce the output voltage of the LDO, thereby maintaining the stability of the output voltage.

The phase compensation unit 50 exploits the miller effect such that the dominant pole P1 is at the output of the error amplifier. Adjustment ofParasitic capacitance C of whole transistor _gd The pole P2 can also be separated to high frequency as a miller capacitance.

With a buffer comprising a push-pull unit, the transistors M6 and M9 of the push-pull unit are controlled to turn on and off in different changing states of the rapid rise and fall of the output voltage, respectively, to discharge and charge the regulating transistor, respectively, so that even if no output capacitor is added outside the LDO, the LDO can cope with the instantaneous change of the load. At the same time, the push-pull unit moves the pole P3 at the output voltage terminal 200 in the high frequency direction. Because the non-main parasitic pole is pushed to a higher frequency, the LDO of the embodiment of the application has stable output under the condition of no minimum load current requirement, and the stability of the LDO is improved.

Another embodiment of the present application provides a low dropout linear regulator, referring to fig. 3, which is different from the above embodiment in that the low dropout linear regulator further includes an enable signal control module. The enable signal control module is connected to the driving signal output terminal 31 and the output voltage terminal 200 of the adjusting transistor 30. The enabling signal control module is used for controlling whether the voltage of the output voltage terminal is output or not. The enable signal is received by the enable signal receiving terminal 61.

The first threshold value and the second threshold value are obtained by setting the on-voltages of the thirteenth PMOS transistor 63 and the fourteenth NMOS transistor 64. When the enable signal is greater than the first threshold, the LDO outputs a voltage. When the enable signal is smaller than the second threshold, the LDO is turned off, and no voltage is output. And the LDO is enabled to be gated or ungated under the control of the enable signal through the enable signal control module so as to conveniently control the LDO. Optionally, the first threshold is the same as or different from the second threshold.

Fig. 4 is a circuit configuration diagram of a low dropout linear regulator according to some embodiments of the present application. The transistor is illustrated as an insulated gate field effect transistor (MOSFET, simply referred to as MOS transistor), but the embodiments of the present application are not limited thereto, and other types of transistors, such as a junction transistor (BJT) or a Junction Field Effect Transistor (JFET), may be used, which is not limited thereto.

As shown in fig. 4, the error amplifier 10 includes a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and an eleventh NMOS transistor Mb1. Transistors M1 and M2 constitute a differential input pair of transistors. The aspect ratios of M1 and M2 are consistent. M3 and M4 constitute a current mirror. The aspect ratios of M3 and M4 are consistent. The transistor Mb1 serves as a current source of the error amplifier 10. The tenth NMOS transistor Mb3 is a reference current replica circuit, and is configured to receive the reference current signal, and perform replication.

The gate of M1 is connected as a second signal input terminal of the error amplifier 10, connected to the feedback signal output terminal 41 of the feedback unit 40, and receives the feedback signal of the output voltage Vout. The drain of M1 is connected to the drain of M3, and the source of M1 is connected to the drain of Mb1. The grid electrode of M2 is connected with the first signal input end and receives a reference voltage signal. The drain of M2 is connected to the drain of M4, and the source of M2 is connected to the drain of Mb1. The source of M3 is connected to the supply voltage Vdda, and the gate and drain of M3 are connected. The source of M4 is connected to the power supply voltage Vdda and the drain of M4 is connected to the signal output 103 of the error amplifier 10.

The gate of Mb1 is connected to the reference current input 104 for receiving the reference current. The source electrode of Mb3 is grounded; mb3 has its gate and drain connected to the reference current input 104 and Mb1 has its source connected to ground.

The error amplifier 10 receives the feedback signals of the reference voltage signal Vref and the output voltage Vout, amplifies the difference between the reference voltage signal and the feedback signal to obtain a first amplified signal, and then outputs the first amplified signal to the buffer 20 through the signal output terminal 103.

The buffer 20 comprises a push-pull unit 201, a first gain unit 202, a second gain unit 203, a first signal dependent current source 204 and a second signal dependent current source 205.

The push-pull unit 201 includes at least two transistors of different polarities. As illustrated in fig. 4, the push-pull unit includes at least a sixth P-type transistor M6 and a ninth N-type transistor M9. The first gain unit 202 includes a fifth PMOS transistor M5. The first signal-dependent current source 204 includes a seventh PMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9. The twelfth NMOS transistor Mb2 is used as the current source 206 of the fifth PMOS transistor M5. Rz is the parallel feedback resistance of the M6 gate and drain.

The gate of M5 is connected to the output 103 of the error amplifier 10, the drain of M5 is connected to the gate of M6, and the source of M5 is connected to the power supply voltage Vdda. M5 performs a second amplification on the first amplified signal output from the error amplifier 10 to increase the gain. The source electrode of M7 is connected with the power supply voltage Vdda, and the drain electrode of M7 is connected with the drain electrode of M8; the source electrode of M8 is grounded, and the grid electrode of M8 is connected with the drain electrode of M8 and the grid electrode of M9. The source of M9 is grounded. The drain of M6 and the drain of M9 are both connected to the gate of the trim transistor 30.

The adjusting transistor comprises a PMOS tube Mp. The phase compensation unit 50 includes a compensation capacitor Cm which is miller. The feedback unit includes voltage dividing resistors R1 and R2 connected in series with each other. The feedback signal output 41 of the feedback unit leads from between R1 and R2.

Fig. 5 is an equivalent circuit diagram (first equivalent circuit diagram) when the load current suddenly drops and the output voltage Vout of the LDO rapidly rises. The following describes the working principle with reference to fig. 4 and 5. When the output voltage Vout of the LDO rises rapidly, an overshoot phenomenon will occur at the gate terminals of the transistors M5 and M7, and then the transistors M6 and M9 are turned on and off, respectively. At this time, M7, M8 and M9 form a first signal dependent current source 204, providing current to M6. M5 is the common source of the first signal dependent current source 204. The twelfth NMOS transistor Mb2 is used as a current source of the fifth PMOS transistor M5. M5 performs a second amplification on the first amplified signal output from the error amplifier 10 to increase the gain. The output voltage of M5 is used as the gate voltage of M6. In the small signal state, the voltage change of the M6 grid electrode can be increased, so that the transient response speed of the push-pull unit is improved. Transistor M6 injects current to charge the gate of the regulation transistor 30, and the power transistor Mp gate voltage is raised so that the power transistor Mp is turned off to reduce the load current, thereby stabilizing the output voltage Vout.

In some embodiments of the present application, with continued reference to fig. 4, the second gain unit 203 includes M7 and M8. The second signal dependent current source 205 includes M5, M6, and Mb 2. M7 and M8 secondarily amplify the first amplified signal output from the error amplifier 10 to increase the gain.

FIG. 6 shows the output voltage Vout of the LDO when the load current suddenly increases and the output voltage Vout drops rapidlyEquivalent circuit diagram (second equivalent circuit diagram). The following describes the working principle with reference to fig. 4 and 6. When the output voltage Vout of the LDO drops rapidly, the feedback unit 40 detects the output voltage V _out After a change of (a) generates an output voltage V _out And the feedback signal which is rapidly reduced is output to the error amplifier. The error amplifier outputs the feedback signal V _fb And reference voltage signal V _ref And the difference of the first amplified signal is obtained and outputted to the buffer 20. Reaction output voltage V _out The rapidly falling first amplified signal causes the transistors M6 and M9 of the push-pull unit to be in an off and on state, respectively.

At this time, M5, M6, and Mb2 form the second signal-dependent current source 205, which supplies current to M9. M7 and M8 secondarily amplify the first amplified signal output from the error amplifier 10 to increase the gain. The output voltage of M7, along with the gate of M8, is connected to the gate of M9 as the gate control voltage of M9. In the small signal state, the voltage change of the M9 grid electrode can be increased, so that the transient response speed of the push-pull unit is improved. The gate of the regulator transistor 30 discharges through M9, and the gate voltage of the power transistor Mp decreases, and the power transistor Mp is turned on to supply a desired load current, thereby stabilizing the output voltage Vout.

As can be seen from the above working principle, the bias currents of the transistors M6 and M9 of the push-pull unit are provided by the first signal-dependent current source 204 and the second signal-dependent current source 205, respectively, and the first signal-dependent current source 204 and the second signal-dependent current source 205 each receive the first amplified signal of the feedback signal of the output voltage Vout from the error amplifier 10. I.e. the bias currents of the transistors M6 and M9 of the push-pull cell, are dependent on the variation of the output voltage Vout, a "signal correlation" of the "signal dependent current source" is derived. Therefore, the voltage variation capability at the node P3 of the current source that generates the current variation with the variation of the output voltage Vout of the first signal-dependent current source 204 and the second signal-dependent current source 205 is not limited any more as in the case of the static current source. Under a small signal model, the buffer with the structure can provide additional transient current for the push-pull unit, and compared with the static bias current at the node P3, the current is far larger than the value of the static bias current, so that the transient response characteristic of the LDO is improved. The slew rate of the state of the tuning transistor on and off is greatly improved without increasing the static bias current.

In some embodiments of the present application, referring to fig. 7, the enable signal control module 60 of the ldo includes a first inverter 61, a second inverter 62, and a transmission gate connected between the enable signal input terminal 601 and the output voltage terminal 200. The transfer gate includes a thirteenth P-type transistor 63 and a fourteenth N-type transistor 64. The transistor is illustrated as an insulated gate field effect transistor (MOSFET, simply referred to as MOS transistor), but the embodiments of the present application are not limited thereto, and other types of transistors, such as a junction transistor (BJT) or a Junction Field Effect Transistor (JFET), may be used, which is not limited thereto.

The thirteenth PMOS transistor 63 and the fourteenth NMOS transistor 64 have a very low on-resistance and a very high off-resistance. The signal input 602 of the enable signal control module 60 is connected to the driving signal output 31 of the adjusting transistor 30 to receive the driving signal output by the adjusting transistor 30. The signal output terminal 603 of the enable signal control module 60 is connected to the output voltage terminal 200 for outputting a voltage to a load.

The first inverter 61 and the second inverter 62 are connected in series with each other. The thirteenth PMOS transistor 63 and the fourteenth NMOS transistor 64 are connected in parallel with each other. The signal input 601 of the first inverter 61 is arranged to receive the enable signal en. The first inverter 61 and the second inverter 62 are used for respectively generating two opposite control signals ctlb and ctl to respectively control the thirteenth PMOS transistor 63 and the fourteenth NMOS transistor 64, so as to control the on and off of the transmission gate, and finally determine whether VOUT is output. The gate of the thirteenth PMOS transistor 63 is connected to the signal output terminal of the first inverter 61, and the source of the thirteenth PMOS transistor is connected to the signal input terminal 602 of the enable signal control module 60. The substrate of thirteenth PMOS transistor 63 is connected to power supply voltage Vdda. The gate of the fourteenth NMOS transistor 64 is connected to the signal output terminal of the second inverter 62, and the drain of the fourteenth NMOS transistor 64 is connected to the signal input terminal 602 of the enable signal control module 60. The source of the fourteenth NMOS transistor 64 is connected to the signal output 603 of the enable signal control module 60. The substrate of the fourteenth NMOS transistor 64 is grounded.

The first threshold value and the second threshold value are obtained by setting the on-voltages of the thirteenth PMOS transistor 63 and the fourteenth NMOS transistor 64. When the enable signal is greater than the first threshold, the LDO outputs a voltage. When the enable signal is smaller than the second threshold, the LDO is turned off, and no voltage is output. And the LDO is enabled to be gated or ungated under the control of the enable signal through the enable signal control module so as to conveniently control the LDO. Optionally, the first threshold is the same as or different from the second threshold.

Illustratively, the first threshold is 1.8V. Optionally, the second threshold is 0.5V. When the enable signal is greater than 1.8V, the LDO voltage stabilizer starts to output the target voltage. When the enable signal is less than 0.5V, the LDO regulator is turned off.

Illustratively, the first threshold is 1.1V and the second threshold is 1.05V. When the enable signal is greater than 1.1V, the LDO voltage stabilizer starts to output the target voltage. When the enable signal is less than 1.05V, the LDO regulator is turned off. The effect is shown in fig. 8.

Optionally, the enable signal control module 60 further includes a fifteenth N-type transistor 65 for implementing a filtering function. Taking a MOS transistor as an example, a gate of the fifteenth NMOS transistor 65 is connected to the driving signal output terminal, and a source, a drain, and a substrate of the fifteenth NMOS transistor 65 are all grounded.

Optionally, in the above embodiment of the present application, the LDO is manufactured by using an integrated circuit process, and the transistors are integrated together to form a composite power transistor with a push-pull structure, including a low-voltage embedded gain stage and a power transistor Mp. M5-M9 form a low voltage embedded gain stage.

Optionally, the reference voltages and reference currents in the above embodiments of the present application are provided by a bandgap reference voltage source.

In some embodiments of the present application, the error amplifier 10, the buffer 20, the adjustment transistor 30, and the enable signal control module are all connected to the power supply voltage Vdda and the ground Vssa.

Another embodiment of the present application further provides a power supply, which includes the LDO described in the foregoing embodiment. The power source includes a switch mode power supply, a base station power supply, an electric vehicle charging station power supply, a notebook computer power supply, a tablet computer power supply, a battery charger, a battery power supply system, a mobile phone power supply, a hand held meter power supply, and the like.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A low dropout linear regulator, comprising: an error amplifier, a buffer, a phase compensation unit, a feedback unit and an adjustment transistor connected between the reference voltage input terminal and the output voltage terminal;

the adjusting transistor is connected with the output voltage end and is used for providing output voltage for a load;

the feedback unit is used for detecting the change of the output voltage and providing a feedback signal for the error amplifier according to the change;

the error amplifier is used for receiving a reference voltage signal and the feedback signal, amplifying the difference value between the reference voltage signal and the feedback signal to obtain a first amplified signal, and outputting the first amplified signal to the buffer;

the buffer is connected between the error amplifier and the adjusting transistor and is used for secondarily amplifying the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the adjusting transistor;

the phase compensation unit is respectively connected between the output voltage end and the error amplifier and is used for realizing frequency compensation;

the buffer includes a push-pull unit for increasing slew rates of on-state and off-state of the tuning transistor.

2. The low dropout linear regulator according to claim 1, wherein the push-pull unit includes at least a sixth P-type transistor and a ninth N-type transistor; the buffer further includes a first signal dependent current source for providing a bias current to the sixth P-type transistor in accordance with the first amplified signal.

3. The low dropout linear regulator according to claim 2, wherein the buffer further comprises a first gain unit configured to gain the first amplified signal to obtain a first gain signal, and output the first gain signal to the gate of the sixth P-type transistor.

4. The low dropout linear regulator according to claim 3, wherein said first gain unit comprises a fifth P-type transistor; the first signal-dependent current source includes a seventh P-type transistor, an eighth N-type transistor, and a ninth N-type transistor;

the grid electrode of the fifth P-type transistor is connected with the output end of the error amplifier, the drain electrode of the fifth P-type transistor is connected with the grid electrode of the sixth P-type transistor, and the source electrode of the fifth P-type transistor is connected with the power supply voltage;

the source electrode of the seventh P-type transistor is connected with the power supply voltage, and the drain electrode of the seventh P-type transistor is connected with the drain electrode of the eighth N-type transistor; the source electrode of the eighth N-type transistor is grounded, and the grid electrode of the eighth N-type transistor is connected with the drain electrode of the eighth N-type transistor and the grid electrode of the ninth N-type transistor; the source electrode of the ninth N-type transistor is grounded; and the drain electrode of the sixth P-type transistor and the drain electrode of the ninth N-type transistor are connected with the grid electrode of the adjusting transistor.

5. The low dropout linear regulator according to claim 1, wherein the push-pull unit includes a sixth P-type transistor and a ninth N-type transistor; the buffer further includes a second signal dependent current source; the second signal dependent current source is configured to provide a bias current to the ninth N-type transistor in accordance with the first amplified signal.

6. The low dropout linear regulator according to claim 5, wherein the buffer further comprises a second gain unit configured to gain the first amplified signal to obtain a second gain signal, and output the second gain signal to the gate of the ninth N-type transistor.

7. The low dropout linear regulator of claim 6, wherein said second gain unit comprises a seventh P-type transistor; the second signal related current source comprises a fifth P-type transistor, a sixth P-type transistor and a twelfth N-type transistor;

the grid electrode of the seventh P-type transistor is connected with the output end of the error amplifier, the source electrode of the seventh P-type transistor is connected with the power supply voltage, and the drain electrode of the seventh P-type transistor is connected with the grid electrode of the ninth N-type transistor;

the grid electrode of the fifth P-type transistor is connected with the output end of the error amplifier, the drain electrode of the fifth P-type transistor is connected with the grid electrode of the sixth P-type transistor, and the source electrode of the fifth P-type transistor is connected with the power supply voltage; the drain electrode of the twelfth N-type transistor is connected with the drain electrode of the fifth P-type transistor, the grid electrode of the twelfth N-type transistor receives a reference current signal, and the source electrode of the twelfth N-type transistor is grounded; the source electrode of the sixth P-type transistor is connected with the power supply voltage, and the drain electrode of the sixth P-type transistor is connected with the drain electrode of the ninth N-type transistor; and the drain electrode of the sixth P-type transistor and the drain electrode of the ninth N-type transistor are connected with the grid electrode of the adjusting transistor.

8. The low dropout linear regulator according to claim 1, further comprising an enable signal control module for controlling a voltage output of said output voltage terminal.

9. The low dropout linear regulator according to claim 8, wherein the enable signal control module includes a first inverter, a second inverter, and a transmission gate connected between an enable signal input terminal and an output voltage terminal; the transmission gate includes a thirteenth P-type transistor and a fourteenth N-type transistor;

the first inverter and the second inverter are connected in series and are used for respectively generating two paths of opposite control signals to respectively control the thirteenth P-type transistor and the fourteenth N-type transistor so as to control the on and off of the transmission gate.

10. A power supply comprising a low dropout linear regulator according to any one of claims 1 to 9.