CN109358689B - Self-bias peak detection circuit and low dropout linear regulator - Google Patents

Self-bias peak detection circuit and low dropout linear regulator Download PDF

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CN109358689B
CN109358689B CN201811122569.XA CN201811122569A CN109358689B CN 109358689 B CN109358689 B CN 109358689B CN 201811122569 A CN201811122569 A CN 201811122569A CN 109358689 B CN109358689 B CN 109358689B
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bias
self
module
signal
detection circuit
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CN109358689A (en
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卫婷婷
王瑜
王乾乾
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Changcun Chuangxin (Beijing) IC Design Co.,Ltd.
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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Abstract

The embodiment of the invention discloses a self-bias peak detection circuit and a low dropout linear regulator, wherein the self-bias peak detection circuit is used for the low dropout linear regulator circuit, the low dropout linear regulator circuit further comprises an error amplifier, and the self-bias peak detection circuit comprises: the power control module is used for receiving the input signal output by the error amplifier and carrying out power control on the input signal to obtain a power control signal; the bias module is used for obtaining a bias signal after the power control signal is subjected to self-bias and dynamic bias when the output voltage of the low dropout linear regulator circuit changes; and the current mirror module is used for carrying out current regulation on the bias signal to obtain a current regulation signal and feeding the current regulation signal back to the power control module.

Description

Self-bias peak detection circuit and low dropout linear regulator
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a Self-bias spike-Detection (SBSD) circuit and a low dropout regulator.
Background
The core architecture of L DO is mainly composed of an operational amplifier and a P-channel Metal oxide semiconductor (PMOS), and the operation principle is to regulate the output of the PMOS through the operational amplifier, the systems now require more and more functions, more and more devices are integrated in a limited area, when the traditional L DO has a large load and a rapid change of the load, a large load capacitor is required to maintain the stability of the output, and the large capacitor is difficult to integrate on a single Chip, so that no external capacitor L is required in the current System on Chip (System on) design.
L DO without off-chip capacitance, saving area for integration, but transient responseThe voltage amplitude of the gate of the power transistor and the bandwidth of the whole circuit are limited, in addition, the power transistor has a large area and a large gate capacitance, a low-frequency secondary dominant pole is generated, and the stability of off-chip capacitor L DO is also seriously influenced, fig. 1A is a schematic diagram of a circuit structure of L DO in the related art, as shown in fig. 1A, L DO comprises an error amplifier, a source follower MOS transistor and a power transistor gmpAnd two resistors Rf1、Rf2Wherein V isEA,outThe output voltage of the error amplifier is connected with a source follower MOS tube behind the error amplifier to play a role of buffering, and a power tube g is connected behind the source follower MOS tubempSo that the regulated larger current can pass through the power tube gmpIs connected with two resistors R connected in seriesf1And Rf2The output between the two resistors is connected to the negative input of the error amplifier, so that the whole circuit forms a feedback loop, VGSIs the gate-source voltage, V, of the source follower MOS tubeOVIs the overdrive voltage, V, of the source follower MOS transistorTHIs the threshold voltage of the source follower MOS transistor, the power transistor gmpVoltage V of gridPWith the voltage V of the output of the error amplifierEA,outThe relationship therebetween is shown by the following equation (0):
VP＝VEA,out+VGS＝VEA,out+VOV+VTH(0)；
therefore, the power tube gm is reduced by using the source follower MOS tube as a buffer in the related artpThe grid resistance is used for pushing up the secondary main pole, transient response is enhanced, the resistance is reduced from the resistance of the amplifier to the reciprocal of transconductance, and the technical scheme has the defect that when the voltage margin is reduced by a threshold value, the power tube gmpThe minimum voltage of the grid is limited, and the power tube g is controlledmpThe driving capability of the load is reduced, a larger power tube is required to provide the same load current, and an additional path of current consumption is increased.
Disclosure of Invention
In view of the above, it is desirable to provide a self-biased spike detection circuit and a low dropout regulator, which can stabilize the output voltage and greatly reduce the recovery time.
The technical scheme of the invention is realized as follows:
the embodiment of the invention provides a self-bias spike detection circuit, wherein the self-bias spike detection circuit and an error amplifier form a low dropout linear regulator circuit, and the self-bias spike detection circuit comprises: the power control module is used for receiving the input signal output by the error amplifier and performing power control on the input signal to obtain a power control signal; the bias module is used for obtaining a bias signal after the power control signal is subjected to self-bias and dynamic bias when the output voltage of the low dropout linear regulator circuit changes; and the current mirror module is used for carrying out current regulation on the bias signal to obtain a current regulation signal and feeding the current regulation signal back to the power control module.
In other embodiments, the biasing module comprises a self-biasing module and a dynamic biasing module, wherein:
the self-bias module is used for carrying out direct current bias on the power control signal when the output voltage of the low dropout linear regulator circuit changes so as to obtain a second direct current bias signal regulated by a voltage amplitude;
and the dynamic bias module is used for dynamically biasing the power control signal to obtain a dynamic bias signal through voltage amplitude adjustment, and the second direct current bias signal and the dynamic bias signal form the bias signal through superposition.
In other embodiments, the self-bias module is further configured to perform dc bias on the power control signal when the output voltage of the voltage-difference linear regulator circuit does not change, to obtain a first dc bias signal adjusted by a voltage amplitude, and input the first dc bias signal to the power control module.
In other embodiments, the self-bias spike detection circuit further comprises: the connection module is used for outputting the bias signal to the current mirror module;
the self-bias module comprises a divider resistor, is used for automatically biasing and feeding back to the negative input end of the error amplifier, and provides direct current bias for the connecting module.
In other embodiments, the voltage divider resistor comprises at least two resistors connected in series.
In other embodiments, the self-bias spike detection circuit further comprises: the connection module is used for outputting the bias signal to the current mirror module;
the dynamic bias module comprises a coupling capacitor, and when the voltage output by the low dropout linear regulator circuit changes, the coupling capacitor transmits the voltage change to the connection module so that the connection module outputs current to achieve dynamic bias;
in other embodiments, the power control module includes a power transistor, the output of which is regulated by the error amplifier.
In other embodiments, the self-bias spike detection circuit further comprises: the connection module is used for outputting the bias signal to the current mirror module;
the connecting module comprises an MOS tube; or the current output by the current mirror module is adjustable in magnitude.
In other embodiments, the current mirror module comprises two MOS transistors, wherein:
the grid electrodes of the two MOS tubes are connected, the source electrodes of the two MOS tubes are connected with the power supply voltage of the self-bias peak detection circuit, the drain electrode of one MOS tube is connected with the power control module, and the drain electrode of the other MOS tube is connected with the current mirror module.
In other embodiments, the transient enhancement circuit formed by the self-bias spike detection circuit is bidirectional when the low dropout linear regulator circuit generates the overshoot signal and the undershoot signal.
An embodiment of the present invention further provides a low dropout regulator, including:
a self-biased spike detection circuit as provided above;
an error amplifier;
and the power control module in the self-bias spike detection circuit is used for receiving the input signal output by the error amplifier and carrying out power control on the input signal.
The embodiment of the invention provides a self-bias peak detection circuit and a low dropout linear regulator; wherein, self-bias spike detection circuit is used for low dropout regulator circuit, low dropout regulator circuit still includes error amplifier, self-bias spike detection circuit includes: the power control module is used for receiving the input signal output by the error amplifier and performing power control on the input signal to obtain a power control signal; the bias module is used for obtaining a bias signal after the power control signal is subjected to self-bias and dynamic bias when the output voltage of the low dropout linear regulator circuit changes; the current mirror module is used for carrying out current regulation on the bias signal to obtain a current regulation signal and feeding the current regulation signal back to the power control module; therefore, the self-bias peak detection circuit reduces power loss by dynamically adjusting extra current through the bias module in two directions of charging and discharging, improves the voltage amplitude of the grid electrode of the power tube in the power control module, reduces the minimum signal resistance of the grid electrode of the power tube in the power control module, increases the bandwidth, and simultaneously ensures the rail-to-rail voltage margin.
Drawings
FIG. 1A is a schematic diagram of L DO circuit structure in the related art;
FIG. 1B is a schematic diagram of a self-biased spike detection circuit according to an embodiment of the present invention;
FIG. 1C is a schematic diagram of the load change outside L DO according to one embodiment of the present invention;
FIG. 1D is a schematic diagram showing the comparison of the output voltages of the circuit of the present embodiment and the circuit of the related art;
FIG. 1E is a schematic diagram illustrating the regulation of the gate voltage of the power transistor by the dynamically increased current provided by the circuit of the present embodiment;
FIG. 2A is a schematic diagram of a self-biased spike detection circuit according to a second embodiment of the present invention;
FIG. 2B is a schematic diagram of a second self-biased spike detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a third self-biased spike detection circuit according to an embodiment of the present invention;
FIG. 4A is a schematic diagram of a quad self-biased spike detection circuit according to an embodiment of the present invention;
FIG. 4B is a schematic diagram of the input resistance of the self-biased spike detection circuit according to the present invention;
FIG. 4C is a schematic diagram of a small signal model of a self-biased spike detection circuit according to an embodiment of the present invention;
FIG. 4D is a schematic diagram of the current variation of the circuits according to the embodiment of the present invention;
fig. 4E is a diagram illustrating that the self-bias spike detection circuit according to the embodiment of the invention greatly reduces the recovery time of the output voltage of the L DO circuit.
Detailed Description
The technical solution of the present invention is further elaborated below with reference to the drawings and the embodiments.
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Example one
The embodiment of the present invention provides a self-biased spike detection circuit, and fig. 1B is a schematic structural diagram of a self-biased spike detection circuit according to an embodiment of the present invention, as shown in fig. 1B, the self-biased spike detection circuit is a transient enhancement circuit having a feedback loop, the self-biased spike detection circuit is used for a low dropout linear regulator circuit, the low dropout linear regulator circuit further includes an error amplifier, and the self-biased spike detection circuit includes:
a power control module 11, configured to receive an input signal output by the error amplifier 10, and perform power control on the input signal to obtain a power control signal;
the bias module 12 is configured to obtain a bias signal after the power control signal is subjected to self-bias and dynamic bias when the output voltage of the low dropout linear regulator circuit changes;
and the current mirror module 14 is configured to perform current adjustment on the bias signal to obtain a current adjustment signal, and feed back the current adjustment signal to the power control module 11.
In other embodiments, the self-bias spike detection circuit further comprises a connection module 13 for outputting the bias signal to the current mirror module 14.
In other embodiments, the power control module 11 includes a power transistor, the output of which is regulated by the error amplifier 10.
In other embodiments, the current mirror module 14 includes two MOS transistors, wherein: the grid electrodes of the two MOS tubes are connected, the source electrodes of the two MOS tubes are connected with the power supply voltage of the self-bias peak detection circuit, the drain electrode of one MOS tube is connected with the power control module, and the drain electrode of the other MOS tube is connected with the connection module.
In other embodiments, the transient enhancement circuit formed by the self-bias spike detection circuit is bidirectional when the low dropout linear regulator circuit generates the overshoot signal and the undershoot signal.
In other embodiments, the current mirror module outputs a current with an adjustable magnitude.
The embodiment of the invention provides a self-bias peak detection circuit, and in two directions of charging and discharging, a bias module in the scheme provided by the embodiment can dynamically adjust extra current, reduce power loss and reduce the recovery time of output voltage, so that the voltage amplitude of a power tube grid in a power control module is improved, the minimum signal resistance of the power tube grid in the power control module is reduced, the bandwidth is increased, and meanwhile, the rail-to-rail voltage margin is ensured.
FIG. 1C is a schematic diagram of the variation of the load outside L DO according to an embodiment of the present invention, as shown in FIG. 1C, the voltage, V, is applied outside L DO circuitREFIs a reference voltage, VDDIs the supply voltage, VSSWhen the load current changes, the output voltage at L DO changes accordingly (see fig. 1D and 1E) for grounding.
FIG. 1D is a diagram showing a comparison between the output voltage of the circuit of the present embodiment and the output voltage of the circuit of the related art, and referring to FIG. 1D, the solid line shows the output voltage of the circuit of the present embodiment, and the dotted line shows the output voltage of the circuit of the related art, the upper diagram of FIG. 1D shows that when the current outputted by the circuit changes twice (at the time t1 and t 2), the output current jumps from 0 to 1 (the current change is normalized, and therefore the current change ranges from 0 to 1) at the time t1, and the output current jumps from 1 to 0 again at the time t2, the lower diagram of FIG. 1D corresponds to the upper diagram of FIG. 1D in time, and at the time t1 and t2, the output voltage of the circuit of the present embodiment greatly reduces the recovery time of the output voltage of the L DO circuit, and therefore, the self-bias spike detection circuit provided by the present embodiment greatly reduces the recovery time of the output voltage L DO circuit.
Fig. 1E shows a schematic diagram of the adjustment of the dynamically increased current provided by the circuit of the present embodiment to the gate voltage of the power tube, and referring to fig. 1E, the upper diagram of fig. 1E shows that when the current output by the circuit changes twice (at times t1 and t 2), the output current jumps from 0 to 1 at time t1 (the current change is normalized, so the current change range is between 0 and 1); at time t2, the output current again transitions from 1 to 0. The middle graph of fig. 1E shows the variation of the dynamically increased current provided by the circuit of the present embodiment, that is, at the time t1 and t2, the dynamically increased current provided by the dynamic bias module in the circuit rises and falls in a moment (which can be understood as a transient current). The lower graph of fig. 1E corresponds to the upper graph and the middle graph of fig. 1E in terms of time, and since the current provided by the dynamic bias module in the circuit is transient current at times t1 and t2 in the upper graph and the middle graph of fig. 1E, the gate voltage amplitude of the power tube in the power control module of the circuit provided by this embodiment is improved at times t1 and t2 in the lower graph of fig. 1E.
Example two
The embodiment of the present invention provides a self-biased spike detection circuit, and fig. 2A is a schematic structural diagram of a self-biased spike detection circuit according to an embodiment of the present invention, as shown in fig. 2A, the self-biased spike detection circuit is a transient enhancement circuit having a feedback loop, the self-biased spike detection circuit is used for a low dropout linear regulator circuit, the low dropout linear regulator circuit further includes an error amplifier, and the self-biased spike detection circuit includes:
a power control module 11, configured to receive an input signal output by the error amplifier 10, and perform power control on the input signal to obtain a power control signal;
the biasing module 12 includes a self-biasing module 121 and a dynamic biasing module 122, wherein:
the self-bias module 121 is configured to perform dc bias on the power control signal when the output voltage of the low dropout linear regulator circuit changes, so as to obtain a second dc bias signal adjusted by a voltage amplitude;
a dynamic bias module 122, configured to dynamically bias the power control signal to obtain a dynamic bias signal through voltage amplitude adjustment, where the second dc bias signal and the dynamic bias signal form a bias signal by being superimposed
A connection module 13, configured to output the bias signal to the current mirror module 14;
and the current mirror module 14 is configured to perform current adjustment on the bias signal to obtain a current adjustment signal, and feed back the current adjustment signal to the power control module 11.
In other embodiments, the self-bias module 121 is further configured to perform dc bias on the power control signal when the output voltage of the voltage-difference linear regulator circuit does not change, to obtain a first dc bias signal adjusted by a voltage amplitude, and input the first dc bias signal to the power control module.
The self-bias module comprises a divider resistor, and is used for automatically biasing and feeding back to the negative input end of the error amplifier to provide direct current bias for the connection module.
In other embodiments, the dynamic bias module 122 includes a coupling capacitor, and when the voltage output by the low dropout linear regulator circuit changes, the coupling capacitor transmits the voltage change to the connection module, so that the connection module outputs a current to achieve dynamic bias.
In other embodiments, the voltage divider resistor comprises at least two resistors connected in series.
In other embodiments, the power control module includes a power transistor, the output of which is regulated by the error amplifier.
In other embodiments, the current mirror module comprises two MOS transistors, wherein: the grid electrodes of the two MOS tubes are connected, the source electrodes of the two MOS tubes are connected with the power supply voltage of the self-bias peak detection circuit, the drain electrode of one MOS tube is connected with the power control module, and the drain electrode of the other MOS tube is connected with the connection module.
In other embodiments, when the low dropout linear regulator circuit generates the overshoot signal, as shown in fig. 2B, the L DO circuit includes an error amplifier and a unidirectional self-bias peak detection circuit, when the output voltage is the overshoot signal, the self-bias peak detection circuit suddenly reduces the load current, the circuit does not have time to stabilize the voltage, and the output generates an overshoot signal, the overshoot signal is coupled to the current mirror module, and the M of the connection module is openedFF2A tube for generating a large dynamic current; copying current to the grid of power tube to speed up the charging of grid and turn off power tube MPPower tube MPAnd a small current is provided, and the output voltage is stabilized. In the unidirectional self-bias peak detection circuit, a self-bias module in a bias module comprises a voltage dividing resistor RF21And RF22，RF21One end of which is connected to the negative input terminal of the error amplifier 10, RF22Grounding; the dynamic bias module comprises a capacitor C12，C12Is connected to the power tube MPAnd a second terminal connected to RF21And RF22To (c) to (d); the connecting pipe MFF2Is C in a grid-connected dynamic bias module12The drain of the second terminal is grounded, the source is connected with the drain of M2 in the current mirror module, and the connecting pipe MFF2Communicating the bias module and the current mirror module, the current mirror module comprising M1 and M2, the drain of the output M2 of the current mirror module being passed to the power transistor MPIn the gate of (1).
In other embodiments, the current mirror module outputs a current with an adjustable magnitude, or the connection module includes a MOS transistor.
In this embodiment, when the output voltage of the low dropout linear regulator circuit changes, the self-bias module performs dc bias on the power control signal to obtain a second dc bias signal adjusted by the voltage amplitude; and then the dynamic bias module carries out dynamic bias on the power control signal again to obtain a dynamic bias signal through voltage amplitude adjustment, and the second direct current bias signal and the dynamic bias signal form a bias signal through superposition. When the output voltage of the low dropout linear regulator circuit does not change, only the self-bias module carries out direct current bias on the power control signal to obtain a first direct current bias signal adjusted by the voltage amplitude, and the first direct current bias signal is directly input to the power control module.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a third self-bias spike detection circuit according to an embodiment of the present invention, when the low dropout regulator circuit generates an overshoot signal and an undershoot signal, as shown in fig. 3, a transient enhancement circuit formed by the self-bias spike detection circuit is bidirectional. The self-bias spike detection circuit includes: the power control module 11 and the bias module comprise a self-bias module 121 and a dynamic bias module 122, a connection module 13 and a current mirror module 14; wherein:
MP is a device of the power control module 11, the input end is connected with the output end of the error amplifier 10, and the power tube MP outputs the voltage V of the low dropout linear regulator circuitOUT；
The self-bias module in the bias module comprises a voltage dividing resistor RF21And RF22，RF21One end of which is connected to the negative input terminal of the error amplifier 10, RF22Grounding; the dynamic bias module comprises a capacitor C12，C12Is connected to the output terminal of the power control module 11, and has a second terminal connected to RF21And RF22To (c) to (d); the connection module 13 is a MOS transistor MFF2The MOS transistor MFF2Dynamic gate connectionBias module in C12The drain of the second terminal of (1) is grounded, the source of the second terminal of (14) is connected to the current mirror module, the connection module 13 connects the bias module 12 and the current mirror module 14, the current mirror module 14 includes M1 and M2, and the drain of the output M2 of the current mirror module 14 is transmitted to the gate of the power transistor MP of the power control module 11.
The self-bias module in the bias module 12 comprises a voltage dividing resistor RF11And RF12，RF11One end of the power control module 11 is connected with the drain electrode R of the power tube MPF12Grounding; the dynamic bias module comprises a capacitor C11，C11Is connected to the output terminal of the power control module 11, and has a second terminal connected to RF11And RF12To (c) to (d); the connection module 13 is a MOS transistor MFF1The MOS transistor MFF1Grid connection dynamic bias module C11The drain of the second terminal of the current mirror module 14 is grounded, the source of the second terminal of the current mirror module 14 is connected to the source of the bias module 12, the connection module 13 connects the bias module 12 and the current mirror module 14, the current mirror module 14 includes M3 and M4, and the source of the output M3 of the current mirror module 14 is transmitted to the gate of the power transistor MP of the power control module 11.
In this embodiment, the self-biased spike detection circuit is not only suitable for L DO, but also suitable for other circuit nodes requiring resistance reduction.
Example four
Fig. 4A is a schematic structural diagram of a self-biased spike detection circuit according to an embodiment of the present invention, as shown in fig. 4A, the self-biased spike detection circuit is a transient enhancement circuit having a feedback loop, the self-biased spike detection circuit and the error amplifier 10 form a low dropout linear regulator circuit, and the self-biased spike detection circuit includes:
resistance Rf1And Rf2；
Power control module including power tube gmp；
The biasing module includes a first self-biasing module, a second self-biasing module, a first dynamic biasing module, and a second dynamic biasing module, wherein,
the first isThe self-bias module comprises a resistor Rf11And a resistance Rf12；
The second self-biasing module comprises a resistor Rf21And a resistance Rf22；
The first dynamic bias module comprises a capacitor Cf1And the second dynamic bias module comprises a capacitor Cf2；
A first connection module including MOS transistor MFF1；
A second connection module including MOS transistor MFF2；
A first current mirror module comprising MOS transistors M1 and M2;
and the second current mirror module comprises MOS tubes M3 and M4.
As shown in FIG. 4A, applicants analyzed the technical problem of the L DO circuit without off-chip capacitor, wherein the L DO circuit is composed of an error amplifier and a self-bias spike detection circuit, and the output voltage V of the circuit is detectedOUTIn a steady state, MFF1Pipe or MFF2The tube is biased in a subthreshold region by a divider resistor, and the self-bias spike detection circuit does not work, namely, the tube is not provided with a dynamic bias module, a connection module and a current mirror module, and is equivalent to a power tube gmpThe drain electrode of the transistor is connected in series with a resistor Rf1And a resistance Rf1The two resistors are connected in series to ground, as shown by the dotted line; output voltage VOUTIn case of sudden change, CfThe capacitor acts as a high-pass device for coupling the output voltage to MFF1Or MFF2Pipe, MFF1Pipe or MFF2The tube is opened, starts to conduct current and is mirrored to the power tube g through the current mirrormpGrid for providing additional charging current to accelerate power transistor gmpL DO transient response is limited by grid voltage amplitude of power tube and circuit bandwidth, self bias peak detection circuit achieves self bias by separating resistance feedback to provide DC bias for voltage amplitude, enhancing circuit does not increase power consumption, feedback loop reduces resistance of power tube to enlarge bandwidth, dynamic bias is achieved by injecting many currents through coupling capacitor to improve grid of power tubeThe magnitude of the voltage.
Power tube gmpA gate connected to the error amplifier of the L DO body circuit, a source connected to the power supply voltage, a drain outputting an output voltage of L DO, and a resistor Rf21And a resistance Rf22A first series resistor is formed and is connected between the negative input end of the error amplifier and the ground; the drain electrode of the M1 of the first current mirror is connected with the power tube gmpThe drain of M2 is connected with the MOS transistor MFF2A source electrode of (a); MOS transistor MFF2Drain grounded, MOS transistor MFF2The grid of the first resistor is connected with the middle of the first series resistor; capacitor Cf2Is connected to the power tube gmpDrain electrode of (1), capacitor Cf2Second end of the MOS transistor M is connected with the MOS transistor MFF2A gate electrode of (1).
L DO circuit output generates an overshoot signal, the error amplifier is followed by a self-bias spike detection circuit of the structure of FIG. 4A, which couples the overshoot signal to the current mirror module, turning on MOS transistor MFF2Generating a large dynamic current, which is copied to the MOS transistor MFF2Grid of (1) accelerating MOS transistor MFF2Charging the grid and turning off the MOS transistor MFF2(ii) a MOS transistor MFF2And a small current is provided, and the output voltage is stabilized.
As shown in fig. 4D, the self-bias spike detection circuit achieves self-bias by feedback of the separation resistor, and the coupling capacitor injects many currents to achieve dynamic bias, both of which can improve the voltage amplitude of the gate of the power transistor, when the output of the circuit varies greatly, the voltage amplitude is affected by both the automatic bias and the dynamic bias, and when the output does not vary, the automatic bias provides the voltage amplitude with the dc bias enhancement circuit without increasing power consumption, and the dynamically increased current Δ I is as shown in formula (1):
Figure BDA0001811542990000121
in the formula (1), the first and second groups,
Figure BDA0001811542990000122
is a MOS transistor MFF2The width-to-length ratio of (a),m is the current mirror ratio of M1 to M2, munAs a migration rate of electrons, CoxIs unit area gate oxide capacitance, and Δ V is the variation of capacitance coupling output voltagegsIs MFF2Gate-to-gate source voltage, VthIs a MOS transistor MFF2The threshold voltage of (2).
MOS transistor M influenced by dynamically increasing current delta IFF2Gate voltage V ofgsAs in equation (2):
Figure BDA0001811542990000123
in the formula (2), VoutIs the output voltage of L DO circuit, S is the variable of complex frequency domain, CfIs a coupling capacitor Cf2The capacitance value of (2). As shown in fig. 4D, the dynamically increased current Δ I of the self-biased spike detection circuit accelerates the gate voltage rise of the power tube, and the recovery time of the output voltage is greatly reduced.
A feedback loop in the self-bias peak detection circuit reduces the resistance of the power tube, and the bandwidth can be enlarged. As shown in FIG. 4B, the current mirror has a ratio of m:1, and the resistance R of the input of the self-bias spike detection circuitgateSee formula (3):
Figure BDA0001811542990000131
in the formula (3), ro,EAIs the output resistance of the error amplifier, gmpIs a power tube gmpTransconductance of gmffIs a MOS transistor MFF2Transconductance of (1). The mathematical expressions for the small signal model of the self-biased spike detection circuit (as shown in FIG. 4C) are seen in equations (4-1) through (4-3):
Figure BDA0001811542990000132
h0＝gmff*gmp*R2*roff(4-2)；
Figure BDA0001811542990000133
in equations (4-1) to (4-3), h(s) is the s-domain transfer function of the self-biased spike detection circuit, h0As a direct current transfer function of the self-biased spike detection circuit, ZfAnd PfZero and pole of the circuit, ropIs a first power tube gmpOutput resistance of roffIs a VoOutput resistance at' because the circuit has an effect on small signals, CfA pair of zero pole pairs is located that is more than 2 times the product of the L DO loop gain bandwidths.
Fig. 4D shows changes in the output current and the output voltage of the unidirectional circuit according to the present embodiment, and diagrams a and B of fig. 4D are similar to the upper diagram and the middle diagram of fig. 1E, where the upper diagram and the middle diagram of fig. 1E are changes in the output current and the dynamically increased current of the bidirectional circuit, and thus diagram a of fig. 4D corresponds to the right half portion of the upper diagram of fig. 1E, and diagram B of fig. 4D corresponds to the right half portion of the middle diagram of fig. 1E.
A graph C of fig. 4D shows a comparison schematic diagram of the output voltage of the circuit of the present embodiment with that of the circuit in the related art when the output current changes, the output voltage of the circuit of the present embodiment rises instantaneously when the output current changes, so that the recovery time is very short (negligible), whereas the recovery time of the output voltage of the circuit in the related art when the output current changes takes a long time (about 0.005 milliseconds (ms)).
Fig. 4E is a schematic diagram showing a comparison of the output voltages of the circuit of the present embodiment and the circuit of the related art, and referring to fig. 4E, the broken line indicates the output voltage of the circuit of the present embodiment, and the solid line indicates the output voltage of the circuit of the related art; in the related art circuit, i.e., without the self-bias spike detection circuit, the recovery time of the output voltage is 7 microseconds (us); the circuit provided by the embodiment has a recovery time of 2us after being adjusted by the self-bias spike detection circuit. Compared with the prior art, the circuit provided by the embodiment can greatly reduce the recovery time of the output voltage, namely, from 7us to 2 us.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention, and all such changes or substitutions are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (11)

1. A self-bias spike detection circuit for a low dropout linear regulator circuit, the low dropout linear regulator circuit further comprising an error amplifier, the self-bias spike detection circuit comprising:
the power control module is used for receiving the input signal output by the error amplifier and performing power control on the input signal to obtain a power control signal;
the bias module is used for obtaining a bias signal after the power control signal is subjected to self-bias and dynamic bias when the output voltage of the low dropout linear regulator circuit changes; the bias module comprises a self-bias module and a dynamic bias module;
the connecting module is used for outputting the bias signal to the current mirror module; the connection module comprises a connection pipe, the grid electrode of the connection pipe is connected with the dynamic bias module, the drain electrode of the connection pipe is grounded, the source electrode of the connection pipe is connected with the current mirror module, and the connection pipe enables the dynamic bias module and the current mirror module to be communicated;
and the current mirror module is used for carrying out current regulation on the bias signal to obtain a current regulation signal and feeding the current regulation signal back to the power control module.
2. The self-bias spike detection circuit of claim 1,
the self-bias module is used for carrying out direct current bias on the power control signal when the output voltage of the low dropout linear regulator circuit changes so as to obtain a second direct current bias signal regulated by a voltage amplitude;
and the dynamic bias module is used for dynamically biasing the power control signal to obtain a dynamic bias signal through voltage amplitude adjustment, and the second direct current bias signal and the dynamic bias signal form the bias signal through superposition.
3. The self-bias spike detection circuit of claim 2, wherein the self-bias module is further configured to, when the output voltage of the voltage-difference linear regulator circuit does not change, perform dc bias on the power control signal to obtain a first dc bias signal adjusted by a voltage amplitude, and input the first dc bias signal to the power control module.
4. The self-bias spike detection circuit of claim 2,
the self-bias module comprises a divider resistor, is used for automatically biasing and feeding back to the negative input end of the error amplifier, and provides direct current bias for the connecting module.
5. The self-bias spike detection circuit of claim 4 wherein the voltage divider resistor comprises at least two resistors in series or the connection module comprises a MOS transistor.
6. The self-bias spike detection circuit of claim 2,
the dynamic bias module comprises a coupling capacitor, and when the voltage output by the low dropout linear regulator circuit changes, the coupling capacitor transmits the voltage change to the connection module, so that the connection module outputs current to achieve dynamic bias.
7. The self-bias spike detection circuit of any one of claims 1 to 6 wherein the power control module includes a power transistor, the output of the power transistor being regulated by the error amplifier to obtain a power control signal.
8. The self-bias spike detection circuit of any one of claims 1 to 6 wherein the current mirror module comprises two MOS transistors, wherein:
the grid electrodes of the two MOS tubes are connected, the source electrodes of the two MOS tubes are connected with the power supply voltage of the self-bias peak detection circuit, the drain electrode of one MOS tube is connected with the power control module, and the drain electrode of the other MOS tube is connected with the connection module.
9. The self-bias spike detection circuit of any one of claims 1 to 6 wherein the transient enhancement circuit formed by the self-bias spike detection circuit is bi-directional when the low dropout linear regulator circuit generates the overshoot signal and the undershoot signal.
10. The self-bias spike detection circuit of any one of claims 1 to 6 wherein the current mirror module outputs a current of an adjustable magnitude.
11. A low dropout linear regulator comprising:
the self-bias spike detection circuit of any one of claims 1 to 10;
an error amplifier;
and the power control module in the self-bias spike detection circuit is used for receiving the input signal output by the error amplifier and carrying out power control on the input signal.
CN201811122569.XA 2018-09-26 2018-09-26 Self-bias peak detection circuit and low dropout linear regulator Active CN109358689B (en)

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CN112684846B (en) * 2019-10-18 2022-10-14 圣邦微电子（北京）股份有限公司 Error amplifier of low dropout regulator and low dropout regulator
US20220247362A1 (en) * 2021-02-02 2022-08-04 Macronix International Co., Ltd. High-speed, low distortion receiver circuit
CN113625810B (en) * 2021-07-29 2022-11-11 西安电子科技大学 Low-power-consumption full-range stable LDO linear voltage regulator without off-chip capacitor
CN114035646A (en) * 2021-10-26 2022-02-11 北京理工大学 Dynamic bias circuit of linear voltage stabilizer
CN114242020B (en) * 2022-02-22 2022-06-10 深圳通锐微电子技术有限公司 Transient recovery circuit
CN114647271B (en) * 2022-05-23 2022-08-12 芯海科技（深圳）股份有限公司 LDO circuit, control method, chip and electronic equipment
CN115291660B (en) * 2022-06-20 2024-06-11 西安电子科技大学 Overshoot suppression circuit of low dropout linear voltage regulator and driving method thereof

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US7502719B2 (en) * 2007-01-25 2009-03-10 Monolithic Power Systems, Inc. Method and apparatus for overshoot and undershoot errors correction in analog low dropout regulators
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US9946283B1 (en) * 2016-10-18 2018-04-17 Qualcomm Incorporated Fast transient response low-dropout (LDO) regulator
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