CN108541309B - Low-dropout voltage stabilizer - Google Patents
Low-dropout voltage stabilizer Download PDFInfo
- Publication number
- CN108541309B CN108541309B CN201680002062.3A CN201680002062A CN108541309B CN 108541309 B CN108541309 B CN 108541309B CN 201680002062 A CN201680002062 A CN 201680002062A CN 108541309 B CN108541309 B CN 108541309B
- Authority
- CN
- China
- Prior art keywords
- control signal
- low dropout
- output
- transistor
- dropout regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
A low dropout regulator (10) comprises a control unit (106) including a control circuit (112) and a switch module (114) for controlling the conduction of the switch module (114) according to a plurality of control signals (SG1-SG6) of the control circuit (112); and an output transistor module (108) coupled to the control unit (106), the output transistor module (108) comprising a first transistor unit (M1) and a second transistor unit (M2) for providing an output current (IL) to an output terminal according to the conduction of the switch module (114); wherein, according to the conducting state of the switch module (114) controlled by the control circuit (112), the output current (IL) with different current amounts is provided to the output end in a power-down mode, a soft start mode and a normal start mode. The low dropout regulator has the advantages of continuously and stably outputting Voltage (VOUT) to a post-stage circuit, small circuit area and simplicity.
Description
Technical Field
The present application relates to a low dropout regulator, and more particularly, to a low dropout regulator capable of providing a regulated voltage with a simple circuit.
Background
With the development and progress of science and technology, mobile electronic devices such as mobile phones, digital cameras, tablet computers, notebook computers and the like have become indispensable tools in people's lives. In order to save power consumption of electronic devices, linear regulators (LDO regulators) capable of providing stable output Voltage are widely used in various portable electronic products, wherein the output Voltage of the Low Drop-Out Voltage Regulator (LDO Regulator) can be very close to the input Voltage. However, the conventional low dropout regulator often operates in a phase operation manner, which results in high circuit complexity and large circuit area, and is not suitable for being applied to a small-sized electronic device.
Therefore, it is an objective of the industry to provide a low dropout regulator apparatus that can stably provide an output voltage to a subsequent circuit and has the advantages of low complexity and small size.
Disclosure of Invention
Therefore, it is a primary object of some embodiments of the present invention to provide a low dropout regulator with a less complex and smaller circuit size, and which can stably provide an output voltage to a subsequent circuit.
In order to solve the above technical problem, some embodiments of the present application provide a low dropout regulator, which includes a control unit including a control circuit and a switch module, for controlling the switch module to be turned on according to a plurality of control signals of the control circuit; and an output transistor module coupled to the control unit, the output transistor module including a first transistor unit and a second transistor unit for providing an output current to an output terminal according to the conduction of the switch module; and according to the conduction state of the switch module controlled by the control circuit, the output current with different current quantities is provided to the output end in a power-down mode, a soft start mode and a normal start mode.
For example, the low dropout regulator includes a voltage source module for generating a plurality of reference voltage signals, wherein the reference voltage signals include a first reference voltage signal; and an amplifier, coupled to the voltage source module, for receiving the first reference voltage signal and a feedback voltage signal to generate an output control signal.
For example, the low dropout regulator further comprises a resistor circuit coupled to the amplifier and the output terminal of the output transistor module for generating the feedback voltage signal according to a voltage division corresponding to the output current.
For example, the voltage source module includes a first reference voltage source and a second reference voltage source, wherein the voltage source module generates the first reference voltage signal according to the first voltage source, and generates a second reference voltage signal according to a first resistor, a second resistor and the second voltage source.
For example, a power supply input of the amplifier is connected to the output of the low dropout regulator.
For example, the first transistor unit and/or the second transistor unit are metal oxide semiconductor field effect transistors.
For example, the control signals include a first control signal, a second control signal, and a third control signal, and one of the first control signal, the second control signal, and the third control signal or a combination of two or more of the first control signal, the second control signal, and the third control signal controls the low dropout regulator to be in the power-down mode, the soft start mode, or the normal start mode.
For example, when the first control signal is at a first logic level, the LDO enters the power-down mode and precharges a floating voltage source to the second reference voltage signal.
For example, when the first control signal is at a second logic level, the first transistor unit and the second transistor unit are driven by the floating voltage source.
For example, when the first control signal is the second logic level and the second control signal is the first logic level, the low dropout regulator enters the soft start mode to turn off the first transistor unit and drive the second transistor unit, so as to reduce an inrush current during start-up.
For example, when the first control signal is the second logic level and the second control signal is the second logic level, the low dropout regulator enters the normal start mode to drive the first transistor unit and the second transistor unit to obtain the larger output current.
For example, the output voltage of the soft start mode has a first convergence time, and the output voltage of the normal start mode has a second convergence time; wherein the first convergence time is greater than the second convergence time.
For example, when the first control signal is the first logic level and the third control signal is the first logic level, the low dropout regulator enters the power-down mode to turn off the first transistor and the second transistor, so as to reduce an output voltage of the low dropout regulator to a ground potential.
For example, when the first control signal is the first logic level and the third control signal is the second logic level, the first transistor and the second transistor are driven by the second reference voltage signal to reduce the output voltage of the low dropout regulator.
For example, the first transistor unit has a first gate width, and the second transistor unit has a second gate width; wherein the first gate width is greater than the second gate width.
The low dropout regulator apparatus that this patent application provided has can be in succession and output voltage to the back stage circuit steadily to circuit area is little and simple advantage.
Drawings
Fig. 1 is a schematic diagram of a low dropout regulator according to some embodiments of the present application.
Fig. 2 is a schematic diagram of a control unit according to some embodiments of the present application.
Fig. 3 is a schematic diagram of a signal timing diagram of a low dropout regulator apparatus according to some embodiments of the present application.
Fig. 4 is a schematic diagram of another signal timing diagram of the low dropout regulator apparatus according to some embodiments of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the present application is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present patent application and are not limiting of the present patent application.
Referring to fig. 1, fig. 1 is a schematic diagram of a low dropout regulator 10 according to a partial embodiment of the present application. The low dropout regulator 10 includes a voltage source module 102, an amplifier 104, a control unit 106, an output transistor module 108, and a resistor circuit 110. In the present embodiment, the voltage source module 102 generates the reference voltage signals VREF1 and VREF2 according to the reference voltage sources V1 and V2, wherein the reference voltage signal VREF2 is generated by dividing the voltage of the reference voltage source V2 and the voltage dividing resistors R1 and R2 connected to the two ends of the reference voltage source V2, and the reference voltage signal VREF1 can be generated by the reference voltage source V1.
The amplifier 104 is coupled to the voltage source module 102 for receiving the reference voltage signal VREF1 and a feedback voltage signal VFB to generate an output control signal OPVO. Referring to fig. 2, fig. 2 is a schematic diagram of the control unit 106 of the low dropout regulator 10. The control unit 106 includes a control circuit 112 and a switch module 114, coupled to a floating voltage source VF, which may be a storage capacitor unit C1, and the voltage source module 102, for controlling the switch module 114 to be turned on according to a plurality of control signals of the control circuit 112. The output transistor module 108 includes a first transistor unit M1 and a second transistor unit M2, both coupled to the control unit 106, for determining the conduction degree thereof according to the conduction of the switch module 114 of the control unit 106, and determining the current amount passing through the output transistor module 108, and providing an output current (i.e. load current) IL to the output terminal of the low dropout regulator 10 for the subsequent stage, wherein the output current IL forms an output voltage VOUT through a load Cload. The resistor circuit 110 is coupled to the amplifier 104 and the output transistor module 108, the feedback voltage signal VFB is generated by dividing the output voltage VOUT according to the output current IL through the resistors R3 and R4, and the feedback voltage signal VFB is fed back to the inverting input terminal ("") of the amplifier 104, wherein the reference voltage signal VREF1 is inputted to the non-inverting input terminal ("+") of the amplifier 104.
The conventional low dropout regulator usually utilizes the phase operation characteristic to provide a stable output voltage to the output terminal, which results in a high circuit complexity and a large circuit area. In this embodiment, the switch module 114 is controlled by the control circuit 112 to be turned on, so that the low dropout regulator 10 can maintain the stable output current IL with the control circuit 112 having a simpler circuit and the switch module 114 in a power-down mode, a soft start mode and a normal start mode. In detail, the control unit 106 generates the control signals SG1, SG2, SG3, SG4, SG5, and SG6 corresponding to the switch elements SW1, SW2, SW3, SW4, SW5, and SW6 according to a first control signal RESET, a second control signal SS _ LDO, and a third control signal NCTRL _ LDO of the control circuit 112 to control the conduction of the switch module 114, so as to determine the current amount of the output transistor module 108. The switch elements SW1, SW2, SW3, SW4, SW5 and SW6 may be any type of switches, and are not limited thereto as long as they can be used as integrated elements on a semiconductor substrate. For example, when the switch element SW3 forms a short-circuit conductive connection, the gate terminal M1G of the first transistor unit M1 is logic 0; when the switch element SW2 and the switch element SW6 are short-circuited, the gate terminal M2G of the second transistor unit M2 is logic 1. It should be noted that the Power input op _ PWR of the amplifier 104 is supplied by the output VOUT of the low dropout regulator 10, rather than an external Power VDDA _ PWR, so as to improve the Power supply rejection of the conventional low dropout regulator.
Please refer to fig. 1, fig. 2, and fig. 3 for the operation principle of the low dropout regulator 10. Fig. 3 is a schematic diagram of a signal timing diagram of the low dropout regulator 10 according to some embodiments of the present application. In actual operation, when the first control signal RESET is logic 1, the low dropout regulator 10 enters a Power-down mode (Power down mode), the storage capacitor unit C1 enters a Pre-charge mode (Pre-charge) through the switch element SW1 and the switch element SW2, and at this time, the control signals SG1 and SG2 are both logic 1 and logic 0, respectively, and the voltage across the storage capacitor unit C1 is Pre-charged to the potential of the reference voltage signal VREF 2. It is noted that, since the reference voltage signal VREF2 is divided by the resistors R1 and R2 from the reference voltage source V2, the problem of reliability caused by the floating voltage source VF being too high when the switch module 114 is turned on can be avoided.
When the first control signal RESET is logic 0, the low dropout regulator 10 is in an active state, and must provide the output voltage VOUT to the external circuit load, and the switch elements SW1 and SW2 are opened. In this case, the storage capacitor unit C1, which is charged to the level of the reference voltage signal VREF2 in the power down mode, provides a voltage VC1 to be superimposed on the output control signal OPVO of the amplifier 104, forms a floating voltage source VF to drive the gate terminals M1G and M2G of the first transistor unit M1 and the second transistor unit M2, and maintains its output voltage VOUT through the control of the feedback loop. During the period when the LDO 10 is active, the storage capacitor unit C1 will gradually discharge due to the leakage current at the node where the floating voltage source VF is located, the voltage VC1 of the storage capacitor unit C1 will drop at a corresponding rate, and the LDO 10 can normally maintain its output voltage by measuring the maximum leakage current and selecting an appropriate capacitance to maintain a sufficiently high value of the floating voltage source VF.
In this embodiment, the first transistor unit M1 and the second transistor unit M2 can be n-type metal oxide semiconductor field effect transistors (nMOS), in which the width of the first transistor unit M1 is larger than the width of the second transistor unit M2, so that the first transistor unit M1 can be used as a main driving transistor unit, and the second transistor unit M2 is a sub-driving transistor unit.
Generally, when the low dropout regulator 10 is powered on, a Soft-start mode is used to avoid the reliability problem caused by excessive surge current. Therefore, when the first control signal RESET is logic 0 and the second control signal SS _ LDO is logic 1, the low dropout regulator 10 enters the soft-start mode, the control signals SG3 and SG4 are both logic 1, the control signals SG5 and SG6 are both logic 0, the switch elements SW4 and SW5 are open, and the switch elements SW3 and SW6 are short-circuited. At this time, the gate terminal M1G of the first transistor unit M1 is at AVSS (0V) ground potential, the first transistor unit M1 is turned off, and the gate terminal M2G of the second transistor unit M2 is at the potential of the floating voltage source VF. Therefore, by driving the smaller second transistor unit M2, the inrush current at the time of startup is reduced. It is noted that, in the case of the soft-start mode, since only the second transistor unit M2 is driven (the potential of the gate terminal M1G of the first transistor unit M1 is 0V), the convergence time TS1 of the output voltage VOUT of the low dropout regulator 10 will take a longer time.
When the first control signal RESET and the second control signal SS _ LDO are both logic 0, the low dropout regulator 10 is in the normal start mode. At this time, the control signals SG3, SG4, SG5 and SG6 are all logic 0, the switch elements SW3 and SW5 are opened, and the switch elements SW4 and SW6 are short-circuited, so that the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 are floating to the potential of the voltage source VF. Therefore, by driving the first transistor unit M1 and the second transistor unit M2, the low dropout regulator 10 can output a larger output current IL. It is noted that, in the case of the normal start-up mode, since the first transistor unit M1 and the second transistor unit M2 are both driven, the convergence time TS2 of the output voltage VOUT of the low dropout regulator 10 is shorter than the convergence time TS1 of the soft start-up mode (i.e., TS2< TS 1).
Furthermore, when the first control signal RESET is logic 1 and the low dropout regulator 10 is in the power-down mode, the gate terminals M1G and M2G of the first transistor unit M1 and the second transistor unit M2 can be selected to be connected to the potential of the floating voltage source VF or AVSS (0V) ground potential by the third control signal NCTRL _ LDO. That is, when the first control signal RESET is logic 1 and the third control signal NCTRL _ LDO is logic 1, the control signals SG3, SG4, SG5 and SG6 are all logic 1, the switch elements SW4 and SW6 are opened, the switch elements SW3 and SW5 are short-circuited, the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 are connected to AVSS (0V) ground potential, and the first transistor unit M1 and the second transistor unit M2 are turned off, so that the output voltage VOUT of the low dropout regulator 10 is gradually lowered to AVSS (0V) ground potential.
On the other hand, when the first control signal RESET is logic 1 and the third control signal NCTRL _ LDO is logic 0, the control signals SG3, SG4, SG5 and SG6 are all logic 0, the switching elements SW4 and SW6 are short-circuited, the switching elements SW3 and SW5 are open-circuited, and the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 are set to the potential of the floating voltage source VF (in this case, VREF 2). In this way, the first transistor unit M1 and the second transistor unit M2 are driven by the lower reference voltage signal VREF2, so that the output voltage VOUT of the low dropout regulator 10 is lowered to another lower level.
In addition, referring to fig. 4, fig. 4 is a schematic diagram of another signal timing diagram of the low dropout regulator 10 according to some embodiments of the present application. The difference from fig. 3 is that the signal timing chart shown in fig. 4 is a signal timing chart when the third control signal NCTRL _ LDO is logic 0. It should be noted that when the third control signal NCTRL _ LDO is logic 0 and the low dropout regulator 10 is in the power-down mode, the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 are at the level of the floating voltage source VF, and at this time, the low dropout regulator 10 can perform pre-charge output to supply the output level of the output voltage VOUT with a lower level and reduce the response time when the low dropout regulator 10 is turned on.
It should be noted that the foregoing embodiments are provided to illustrate the concepts of the present application and that various modifications may be made by those skilled in the art without limiting the scope of the invention. For example, the transistor module may be implemented by a p-type metal oxide semiconductor field effect transistor (pMOS) in addition to an nMOS, or may control different switches by different control signals, which all belong to the scope of the present application.
To sum up, the low dropout regulator that this patent application provided has removed the advantage that has that the circuit is simple and the circuit area is little, also can provide output voltage to back stage circuit steadily.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (11)
1. A low dropout voltage regulator apparatus comprising:
the control unit comprises a control circuit and a switch module, and is used for controlling the conduction of the switch module according to a plurality of control signals of the control circuit;
an output transistor module coupled to the control unit, the output transistor module including a first transistor unit and a second transistor unit for providing an output current to an output terminal according to the conduction of the switch module; and
a voltage source module for generating a plurality of reference voltage signals, wherein the reference voltage signals include a first reference voltage signal;
an amplifier, coupled to the voltage source module, for receiving the first reference voltage signal and a feedback voltage signal to generate an output control signal;
according to the conducting state of the switch module controlled by the control circuit, the output current with different current quantities is provided to the output end in a power-down mode, a soft start mode and a normal start mode;
wherein, when the low dropout regulator enters the power-down mode, a voltage of a floating voltage source is superimposed on the output control signal of the amplifier;
the plurality of control signals comprise a first control signal, a second control signal and a third control signal, and the low-dropout voltage regulator is controlled to be in the power-down mode, the soft start mode or the normal start mode through one of the first control signal, the second control signal and the third control signal or the combination of two or more than two of the first control signal, the second control signal and the third control signal;
when the first control signal is a first logic level and the third control signal is the first logic level, the low dropout regulator enters the power-down mode to turn off the first transistor and the second transistor, so as to reduce an output voltage of the low dropout regulator to a ground potential.
2. The low dropout regulator apparatus of claim 1, wherein the low dropout regulator apparatus further comprises:
and the resistance circuit is coupled to the amplifier and the output end of the output transistor module and used for generating the feedback voltage signal according to a partial voltage corresponding to the output current.
3. The LDO of claim 1, wherein the voltage source module comprises a first reference voltage source and a second reference voltage source, wherein the voltage source module generates the first reference voltage signal according to a first voltage source and generates the second reference voltage signal according to a first resistor, a second resistor, and a second voltage source.
4. The low dropout regulator apparatus of claim 1 wherein a power supply input of said amplifier is connected to said output of said low dropout regulator apparatus.
5. The low dropout voltage regulator apparatus of claim 1, wherein the first transistor unit and/or the second transistor unit is a metal oxide semiconductor field effect transistor.
6. The low dropout regulator apparatus according to claim 1, wherein the first transistor unit and the second transistor unit are driven by the floating voltage source when the first control signal is at a second logic level.
7. The low dropout regulator apparatus according to claim 1, wherein when the first control signal is at a second logic level and the second control signal is at the first logic level, the low dropout regulator apparatus enters the soft start mode to turn off the first transistor unit and drive the second transistor unit to reduce an inrush current during start-up.
8. The low dropout regulator apparatus according to claim 1, wherein when the first control signal is at a second logic level and the second control signal is at the second logic level, the low dropout regulator apparatus enters the normal start mode for driving the first transistor unit and the second transistor unit to obtain the larger output current.
9. The low dropout voltage regulator apparatus according to claim 7 or 8, wherein the output voltage of the soft start mode has a first convergence time, and the output voltage of the normal start mode has a second convergence time; wherein the first convergence time is greater than the second convergence time.
10. The low dropout regulator apparatus according to claim 3, wherein when the first control signal is at a first logic level and the third control signal is at a second logic level, the first transistor and the second transistor are driven by the second reference voltage signal to reduce the output voltage of the low dropout regulator apparatus.
11. The low dropout regulator apparatus of any one of claims 1-8, 10, wherein said first transistor unit has a first gate width and said second transistor unit has a second gate width; wherein the first gate width is greater than the second gate width.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2016/106827 WO2018094580A1 (en) | 2016-11-22 | 2016-11-22 | Low dropout voltage stabilising apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108541309A CN108541309A (en) | 2018-09-14 |
| CN108541309B true CN108541309B (en) | 2021-04-02 |
Family
ID=62194572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680002062.3A Active CN108541309B (en) | 2016-11-22 | 2016-11-22 | Low-dropout voltage stabilizer |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108541309B (en) |
| WO (1) | WO2018094580A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377088B (en) * | 2019-07-10 | 2024-06-18 | 深圳市锐能微科技有限公司 | Integrated circuit, low dropout linear voltage stabilizing circuit and control method thereof |
| CN112947657B (en) * | 2021-01-29 | 2022-05-27 | 漳州立达信光电子科技有限公司 | High-low end driving system |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005198439A (en) * | 2004-01-08 | 2005-07-21 | Matsushita Electric Ind Co Ltd | Ldo output short-circuit protection system |
| ATE537496T1 (en) * | 2006-03-03 | 2011-12-15 | Dialog Semiconductor Bv | LOW VOLTAGE LOSS VOLTAGE REGULATOR FOR TIME SLOT BASED OPERATION |
| TWI377460B (en) * | 2008-09-02 | 2012-11-21 | Faraday Tech Corp | Reference current generator circuit for low-voltage applications |
| US8044646B2 (en) * | 2009-04-10 | 2011-10-25 | Texas Instruments Incorporated | Voltage regulator with quasi floating gate pass element |
| US8248150B2 (en) * | 2009-12-29 | 2012-08-21 | Texas Instruments Incorporated | Passive bootstrapped charge pump for NMOS power device based regulators |
| CN102545589B (en) * | 2010-12-27 | 2015-09-16 | 上海天马微电子有限公司 | Direct current voltage conversion circuit |
| JP5749551B2 (en) * | 2011-04-20 | 2015-07-15 | ラピスセミコンダクタ株式会社 | Charge pump type boosting system and semiconductor chip |
| CN102364407B (en) * | 2011-09-20 | 2013-06-26 | 苏州磐启微电子有限公司 | Novel low-dropout linear voltage regulator |
| CN203366174U (en) * | 2013-06-07 | 2013-12-25 | 灿芯半导体(上海)有限公司 | Output dynamic adjusting circuit of low dropout regulator (LDO) |
| US9459642B2 (en) * | 2013-07-15 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low dropout regulator and related method |
| CN103729007B (en) * | 2013-11-22 | 2016-08-17 | 三星半导体(中国)研究开发有限公司 | There is the linear stable of SS (soft start) control circuit |
| CN104699153B (en) * | 2013-12-10 | 2017-02-08 | 展讯通信（上海）有限公司 | Low-dropout linear regulator |
| CN105094193B (en) * | 2014-05-04 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Low-dropout regulator |
| CN104460802B (en) * | 2014-11-27 | 2016-04-20 | 电子科技大学 | The low pressure difference linear voltage regulator of one self-adaptive current multiple circuit and this circuit integrated |
| US9405309B2 (en) * | 2014-11-29 | 2016-08-02 | Infineon Technologies Ag | Dual mode low-dropout linear regulator |
| US9471078B1 (en) * | 2015-03-31 | 2016-10-18 | Qualcomm Incorporated | Ultra low power low drop-out regulators |
| CN105549673B (en) * | 2015-12-25 | 2017-01-25 | 上海华虹宏力半导体制造有限公司 | Dual-mode switching type LDO circuit |
-
2016
- 2016-11-22 CN CN201680002062.3A patent/CN108541309B/en active Active
- 2016-11-22 WO PCT/CN2016/106827 patent/WO2018094580A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018094580A1 (en) | 2018-05-31 |
| CN108541309A (en) | 2018-09-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI668552B (en) | Low-dropout regulators | |
| US10852756B2 (en) | Low dropout voltage regulator integrated with digital power gate driver | |
| US9052728B2 (en) | Start-up circuit and method thereof | |
| EP2846213B1 (en) | Method and apparatus for limiting startup inrush current for low dropout regulator | |
| US9323263B2 (en) | Low dropout regulator with hysteretic control | |
| US8054052B2 (en) | Constant voltage circuit | |
| US10122270B2 (en) | Tunable voltage regulator circuit | |
| US9195244B2 (en) | Voltage regulating apparatus with enhancement functions for transient response | |
| US10038378B2 (en) | Device and method to stabilize a supply voltage | |
| US20160231758A1 (en) | Circuit for regulating startup and operation voltage of an electronic device | |
| US20210157349A1 (en) | Low quiescent current low-dropout regulator (ldo) | |
| CN114978059A (en) | Amplifier circuit and method for reducing output voltage overshoot in amplifier circuit | |
| US9059699B2 (en) | Power supply switching circuit | |
| KR101432494B1 (en) | Low drop out voltage regulator | |
| JP2013206381A (en) | Overcurrent protection circuit, and power supply device | |
| KR20150105809A (en) | control circuit including load switch, electronic apparatus including the load switch and controlling method thereof | |
| CN108541309B (en) | Low-dropout voltage stabilizer | |
| US20170141564A1 (en) | Low power circuit for transistor electrical overstress protection in high voltage applications | |
| US9921592B2 (en) | Bandgap reference circuit with low output impedance stage and power-on detector | |
| JP2008152690A (en) | Power supply device | |
| CN116301157A (en) | Low-dropout linear voltage regulator circuit capable of reducing output overcharge |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |