WO2018094580A1

WO2018094580A1 - Low dropout voltage stabilising apparatus

Info

Publication number: WO2018094580A1
Application number: PCT/CN2016/106827
Authority: WO
Inventors: 庄朝贵; 杨富强
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2016-11-22
Filing date: 2016-11-22
Publication date: 2018-05-31
Also published as: CN108541309B; CN108541309A

Abstract

A low dropout voltage stabilising apparatus (10), comprising: a control unit (106), comprising a control circuit (112) and a switch module (114), and used for controlling the connection of the switch module (114) on the basis of a plurality of control signals (SG1-SG6) of the control circuit (112); and an output transistor module (108) coupled to the control unit (106), the output transistor module (108) comprising a first transistor unit (M1) and a second transistor unit (M2), and being used for providing an output current (IL) to an output end on the basis of the connection of the switch module (114); on the basis of the connection state of the switch module (114) controlled by the control circuit (112), a power-down mode, a soft-start mode, and a normal start mode provide an output current (IL) of a different current amount to the output end. The present low dropout voltage stabilising apparatus has the advantages of continuous and stable output of voltage to a post-stage circuit, and a small and simple circuit.

Description

Low dropout regulator

Technical field

The present patent application relates to a low-dropout voltage regulator device, and more particularly to a low-dropout voltage regulator device that can provide a stable voltage with a simple circuit.

Background technique

With the development and advancement of technology, mobile electronic devices such as mobile phones, digital cameras, tablet computers, and notebook computers have become indispensable tools in people's lives. In order to save power consumption of electronic devices, linear regulators with stable output voltage are widely used in various portable electronic products, among which Low Drop-Out Voltage Regulator (LDO Regulator) The output voltage can be very close to the input voltage and is widely used. However, since the current low-dropout voltage regulators tend to operate in a phase-operated manner, the complexity of the circuit is high and the circuit area is large, which is disadvantageous for use in a small-sized electronic device.

Therefore, how to provide a low-dropout voltage regulator device that stably supplies an output voltage to a subsequent stage circuit and has the advantages of a low complexity and a small volume circuit has become one of the goals of the industry.

Summary of the invention

Therefore, a main object of some embodiments of the present patent application is to provide a low-dropout voltage regulator device which is low in complexity, small in size, and stably provides an output voltage to a subsequent stage circuit.

In order to solve the above technical problem, some embodiments of the present patent application provide a low dropout voltage regulator device, including a control unit, including a control circuit and a switch module for controlling a plurality of control signals according to the control circuit. Controlling the conduction of the switch module; and an output transistor module, The output transistor module is coupled to the control unit, and the output transistor module includes a first transistor unit and a second transistor unit for providing an output current to an output terminal according to the conduction of the switch module; The conduction state of the switch module controlled by the control circuit supplies the output current of different current quantities to the output terminal in a power down mode, a soft start mode, and a normal start mode.

For example, the low dropout voltage regulator includes a voltage source module for generating a plurality of reference voltage signals, wherein the reference voltage signal includes a first reference voltage signal; and an amplifier coupled to the voltage source module And receiving the first reference voltage signal and a feedback voltage signal to generate an output control signal.

For example, the low-dropout voltage regulator further includes a resistor circuit coupled to the output of the amplifier and the output transistor module for generating the feedback according to a voltage division corresponding to the output current. Voltage signal.

For example, the voltage source module includes a first reference voltage source and a second reference voltage source, wherein the voltage source module generates the first reference voltage signal according to the first voltage source, and according to a first resistor And a second resistor and the second voltage source generate a second reference voltage signal.

For example, a power supply input of the amplifier is coupled to the output of the low dropout regulator.

For example, the first transistor unit and/or the second transistor unit are metal oxide semiconductor field effect transistors.

For example, the plurality of control signals include a first control signal, a second control signal, and a third control signal, and one or both of the first control signal, a second control signal, and the third control signal The above combination controls the low dropout voltage stabilizing device in the power down mode, the soft start mode, or the normal start mode.

For example, when the first control signal is at a first logic level, the low dropout voltage regulator enters the power down mode, and precharges a voltage of a floating voltage source to the second reference voltage signal. Voltage.

For example, when the first control signal is a second logic level, the floating voltage source is driven The first transistor unit and the second transistor unit are moved.

For example, when the first control signal is the second logic level and the second control signal is the first logic level, the low dropout voltage regulator enters the soft start mode for The first transistor unit is turned off and the second transistor unit is driven to reduce a surge current during startup.

For example, when the first control signal is the second logic level and the second control signal is the second logic level, the low-dropout voltage regulator enters the normal startup mode for The first transistor unit and the second transistor unit are driven to obtain a larger output current.

For example, the output voltage of the soft start mode has a first convergence time, and the output voltage of the normal startup mode has a second convergence time; wherein the first convergence time is greater than the second convergence time time.

For example, when the first control signal is the first logic level and the third control signal is the first logic level, the low-dropout voltage regulator enters the power-down mode for The first transistor and the second transistor are turned off to reduce an output voltage of the low dropout regulator to a ground potential.

For example, when the first control signal is the first logic level and the third control signal is the second logic level, driving the first transistor and the The second transistor is described to reduce the output voltage of the low dropout regulator.

For example, the first transistor unit has a first gate width, and the second transistor unit has a second gate width; wherein the first gate width is greater than the second gate width.

The low-dropout voltage regulator provided by this patent application has the advantage of continuously and stably outputting a voltage to a subsequent stage circuit, and having a small circuit area and simplicity.

DRAWINGS

1 is a schematic diagram of a low dropout voltage regulator device according to some embodiments of the present patent application.

2 is a schematic diagram of a control unit of a portion of the present patent application.

3 is a schematic diagram of a signal timing diagram of a low dropout voltage regulator device according to some embodiments of the present patent application; Figure.

4 is a schematic diagram of another signal timing diagram of the low dropout voltage regulator device according to some embodiments of the present patent application.

detailed description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to be limiting.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a low-dropout voltage regulator device 10 according to an embodiment of the present application. The low dropout voltage regulator device 10 includes a voltage source module 102, an amplifier 104, a control unit 106, an output transistor module 108, and a resistor circuit 110. The voltage source module 102 includes a plurality of reference voltage sources. In this embodiment, the voltage source module 102 generates reference voltage signals VREF1 and VREF2 according to the reference voltage sources V1 and V2, wherein the reference voltage signal VREF2 is connected through the reference voltage source V2 and connected. The voltage dividing resistors R1 and R2 across the reference voltage source V2 are divided, and the reference voltage signal VREF1 can be generated by the reference voltage source V1.

The amplifier 104 is coupled to the voltage source module 102 for receiving the reference voltage signal VREF1 and a feedback voltage signal VFB to generate an output control signal OPVO. Please refer to FIG. 2 together. FIG. 2 is a schematic diagram of the control unit 106 of the low dropout voltage regulator 10. The control unit 106 includes a control circuit 112 and a switch module 114 coupled to a floating voltage source VF and a voltage source module 102 for controlling the conduction of the switch module 114 according to a plurality of control signals of the control circuit 112. The floating voltage source VF can be a storage capacitor unit C1. The output transistor module 108 includes a first transistor unit M1 and a second transistor unit M2, which are both coupled to the control unit 106 for determining the degree of conduction according to the conduction of the switch module 114 of the control unit 106, and It is determined that an output current (ie, load current) IL is supplied to the output terminal of the low-dropout voltage regulator 10 through the current amount of the output transistor module 108 for use by the subsequent stage circuit, and the output current IL forms an output voltage VOUT through a load Cload. The resistor circuit 110 is coupled to the amplifier 104 and the output transistor module 108, and the feedback voltage signal VFB is based on The output voltage VOUT corresponding to the output current IL is generated by the voltage division of the resistors R3, R4, and the feedback voltage signal VFB is fed back to the inverting input terminal ("-") of the amplifier 104, wherein the reference voltage signal VREF1 is input to The non-inverting input of the amplifier 104 ("+").

Since the current low-dropout regulators often utilize the characteristics of phase operation to provide a stable output voltage to the output, the circuit complexity is high and the circuit area is too large. In this embodiment, according to the conduction of the switch module 114 controlled by the control circuit 112, the low-dropout voltage regulator device 10 has a simpler control circuit 112 and the switch module 114 in a power-down mode, a soft-start mode, and a The normal startup mode provides the low dropout regulator 10 to maintain a stable output current IL. In detail, the control unit 106 generates corresponding to the switch components SW1, SW2, SW3, SW4, SW5, and SW6 according to a first control signal RESET, a second control signal SS_LDO, and a third control signal NCTRL_LDO of the control circuit 112. The control signals SG1, SG2, SG3, SG4, SG5, and SG6 control the conduction of the switch module 114 to determine the amount of current of the output transistor module 108. The switch components SW1, SW2, SW3, SW4, SW5, and SW6 may be any type of switches, and as long as they are integrated components that can be used on a semiconductor substrate, they can be used as a switch component without being limited thereto. For example, when the switch component SW3 forms a short-circuit conduction connection, the gate terminal M1G of the first transistor unit M1 is logic 0; and when the switch component SW2 and the switch component SW6 are short-circuited, the gate terminal of the second transistor unit M2 M2G is logic 1. It is worth noting that the power input op_pwr of the amplifier 104 is supplied by the output terminal VOUT of the low dropout regulator 10 instead of an external power supply VDDA_PWR, thereby improving the power supply rejection of the current low dropout regulator. (Power supply rejection) advantages.

Please refer to Figure 1, Figure 2 and Figure 3 for the working principle of the low-dropout regulator 10. FIG. 3 is a schematic diagram of a signal timing diagram of the low dropout voltage regulator device 10 according to some embodiments of the present patent application. In actual operation, when the first control signal RESET is logic 1, the low-dropout voltage regulator device 10 enters a power down mode, and the storage capacitor unit C1 passes through the switch component SW1 and the switch component SW2. The pre-charge mode is entered. At this time, the control signals SG1 and SG2 are both logic 1 and logic 0, respectively, and are turned on, so that the voltage across the storage capacitor unit C1 is precharged to the potential of the reference voltage signal VREF2. It is worth noting that since the reference voltage signal VREF2 is divided from the reference voltage source V2 through the resistors R1 and R2, the reliability problem caused by the floating voltage source VF being too high when the switch module 114 is turned on can be avoided.

When the first control signal RESET is logic 0, the low dropout regulator 10 is in its active state, and the output voltage VOUT must be supplied to the external circuit load, at which time the switch components SW1 and SW2 are opened. In this case, the storage capacitor unit C1 charged to the potential of the reference voltage signal VREF2 in the power down mode provides a voltage VC1 superimposed on the output control signal OPVO of the amplifier 104 to form a floating voltage source VF to drive the first The gate terminals M1G and M2G of the transistor unit M1 and the second transistor unit M2 maintain their output voltage VOUT by the control of the feedback loop. During the period in which the low dropout voltage stabilizing device 10 is in an active state, the storage capacitor unit C1 will be gradually discharged due to the leakage current at the node where the floating voltage source VF is located, and the voltage VC1 of the storage capacitor unit C1 will drop at a corresponding speed and pass Measure the maximum leakage current and select the appropriate capacitance to maintain a sufficiently high floating voltage source VF value so that the low dropout regulator 10 can maintain its output voltage normally.

In this embodiment, the first transistor unit M1 and the second transistor unit M2 may be n-type metal oxide semiconductor field effect transistors (nMOS), wherein the width of the first transistor unit M1 is greater than the width of the second transistor unit M2, The first transistor unit M1 can serve as a primary drive crystal unit, and the second transistor unit M2 is a secondary drive crystal unit.

In general, the low-dropout regulator 10 uses a soft-startup mode at power-on to avoid excessive surge currents and cause reliability problems. Therefore, when the first control signal RESET is logic 0 and the second control signal SS_LDO is logic 1, the low-dropout voltage regulator device 10 enters a soft-start mode, and the control signals SG3 and SG4 are both logic 1, control signals SG5 and SG6. For logic 0. The switch components SW4 and SW5 are open, and the switch components SW3 and SW6 are short-circuited. At this time, the gate terminal M1G of the first transistor unit M1 has an AVSS (0 V) ground potential, the first transistor unit M1 is turned off, and the gate terminal M2G of the second transistor unit M2 has a potential of the floating voltage source VF. Therefore, the surge current at the time of startup is lowered by driving the smaller second transistor unit M2. It is to be noted that, in the case of the soft start mode, since only the second transistor unit M2 is driven (the potential of the gate terminal M1G of the first transistor unit M1 is 0 V), the output voltage of the low drop voltage regulator 10 is VOUT. The convergence time TS1 will take a long time.

When the first control signal RESET and the second control signal SS_LDO are both logic 0, the low dropout regulator 10 will be in the normal startup mode. At this time, the control signals SG3, SG4, SG5, and SG6 are all logic 0, the switch components SW3 and SW5 are open, and the switch components SW4 and SW6 are short-circuited, so that the gate terminal M1G and the second transistor unit M2 of the first transistor unit M1 are connected. The gate terminal M2G has the potential of the floating voltage source VF. Therefore, by driving the first transistor unit M1 and the second transistor unit M2, the low-dropout regulator device 10 can output a large output current IL. It should be noted that in the case of the normal startup mode, since the first transistor unit M1 and the second transistor unit M2 are both driven, the convergence time TS2 of the output voltage VOUT of the low-dropout regulator 10 is softer than the soft-start mode. The convergence time TS1 is short (ie TS2<TS1).

Furthermore, when the first control signal RESET is logic 1, when the low-dropout voltage regulator device 10 is in the power-down mode, the gate terminal M1G of the first transistor unit M1 and the second transistor unit M2 may be selected by the third control signal NCTRL_LDO and M2G is the potential connected to the floating voltage source VF or the AVSS (0V) ground potential. That is, when the first control signal RESET is logic 1 and the third control signal NCTRL_LDO is logic 1, then the control signals SG3, SG4, SG5, and SG6 are all logic 1, the switch components SW4 and SW6 are opened, and the switch component SW3 And SW5 is short-circuited, so that the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 have an AVSS (0V) ground potential. At this time, the first transistor unit M1 and the second transistor unit M2 are Turning off, the output voltage VOUT of the low-dropout regulator 10 is gradually lowered to the AVSS (0V) ground potential.

On the other hand, when the first control signal RESET is logic 1 and the third control signal NCTRL_LDO is logic 0, the control signals SG3, SG4, SG5, and SG6 are all logic 0, the switch components SW4 and SW6 are short-circuited, and the switch component SW3 and SW5 are opened such that the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 have a potential of a floating voltage source VF (in this case, VREF2). As a result, the first transistor unit M1 and the second transistor unit M2 are driven by the lower reference voltage signal VREF2, so that the output voltage VOUT of the low-dropout regulator 10 is lowered to another lower potential.

In addition, please refer to FIG. 4. FIG. 4 is a schematic diagram of another signal timing diagram of the low-dropout voltage regulator device 10 according to some embodiments of the present patent application. The difference from FIG. 3 is that the signal timing chart shown in FIG. 4 is a signal timing chart when the third control signal NCTRL_LDO is logic 0. It should be noted that when the third control signal NCTRL_LDO is logic 0, the low-voltage difference voltage regulator device 10 is in the power-down mode, the gate terminal M1G of the first transistor unit M1 and the gate terminal M2G of the second transistor unit M2 have a floating voltage source. The potential of the VF, at this time, the low-dropout regulator 10 can perform a precharge output to supply a lower output level of the output voltage VOUT, and reduce the reaction time when the low-dropout regulator 10 is turned on.

It should be noted that the foregoing embodiments are for explaining the concept of the present patent application, and those skilled in the art may make various modifications, and are not limited thereto. For example, in addition to nMOS implementation, transistor modules can also be implemented as p-type metal oxide semiconductor field effect transistors (pMOS) or with different control signals to control different switches, which are within the scope of this patent application.

In summary, the low-dropout voltage regulator provided by the present patent application can provide a stable output voltage to the subsequent circuit in addition to the advantages of simple circuit and small circuit area.

The above description is only for the preferred embodiment of the present application, and is not intended to limit the present patent application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this patent application should be included in the present disclosure. Within the scope of protection of patent applications.

Claims

A low dropout voltage regulator device comprising:

a control unit comprising a control circuit and a switch module for controlling conduction of the switch module according to a plurality of control signals of the control circuit;

An output transistor module is coupled to the control unit, the output transistor module includes a first transistor unit and a second transistor unit for providing an output current to an output according to the conduction of the switch module end;

The output current of different current amounts is supplied to the output terminal in a power down mode, a soft start mode, and a normal start mode according to an on state of the switch module controlled by the control circuit.
The low dropout voltage regulator of claim 1, wherein the low dropout voltage regulator comprises:

a voltage source module for generating a plurality of reference voltage signals, wherein the reference voltage signal includes a first reference voltage signal;

An amplifier coupled to the voltage source module for receiving the first reference voltage signal and a feedback voltage signal to generate an output control signal.
The low dropout voltage regulator of claim 2, wherein the low dropout voltage regulator further comprises:

a resistor circuit coupled to the amplifier and the output terminal of the output transistor module for generating the feedback voltage signal according to a voltage division corresponding to the output current.
The low dropout voltage regulator of claim 2, wherein the voltage source module comprises a first reference voltage source and a second reference voltage source, wherein the voltage source module generates the location according to the first voltage source Decoding a first reference voltage signal and generating a second reference voltage signal according to a first resistor, a second resistor, and the second voltage source.
A low dropout voltage regulator according to claim 2, wherein a power supply input of said amplifier is coupled to said output of said low dropout regulator.
The low dropout voltage stabilizing device according to claim 1, wherein said first transistor unit and/or said second transistor unit are metal oxide semiconductor field effect transistors.
The low dropout voltage regulator of claim 1, wherein the plurality of control signals comprise a first control signal, a second control signal, and a third control signal, by the first control signal, a second control One or a combination of two or more of the signal and the third control signal controls the low dropout voltage regulator to be in the power down mode, the soft start mode, or the normal start mode.
The low dropout voltage regulator of claim 7, wherein when the first control signal is at a first logic level, the low dropout regulator enters the power down mode and a floating voltage The voltage of the source is precharged to the voltage of the second reference voltage signal.
The low dropout voltage regulator of claim 7, wherein the first transistor unit and the second transistor are driven by the floating voltage source when the first control signal is at a second logic level unit.
The low dropout voltage regulator of claim 7, wherein the low voltage is when the first control signal is the second logic level and the second control signal is the first logic level The differential voltage regulator enters the soft start mode to turn off the first transistor unit and drive the second transistor unit to reduce a surge current during startup.
The low dropout voltage stabilizing apparatus according to claim 7, wherein said low voltage is when said first control signal is said second logic level and said second control signal is said second logic level Poor stability The pressing device enters the normal startup mode for driving the first transistor unit and the second transistor unit to obtain a larger output current.
The low dropout voltage regulator device according to claim 10 or 11, wherein said output voltage of said soft start mode has a first convergence time, and said output voltage of said normal startup mode has a second convergence time Wherein the first convergence time is greater than the second convergence time.
The low dropout voltage regulator of claim 7, wherein the low voltage is when the first control signal is the first logic level and the third control signal is the first logic level The difference voltage regulator enters the power down mode for turning off the first transistor and the second transistor to reduce an output voltage of the low dropout regulator to a ground potential.
The low-dropout voltage regulator device according to claim 7, wherein when said first control signal is said first logic level and said third control signal is said second logic level, said The second reference voltage signal drives the first transistor and the second transistor to reduce the output voltage of the low dropout regulator.
The low dropout voltage regulator of any of claims 1 to 14, wherein the first transistor unit has a first gate width and the second transistor unit has a second gate width; The first gate width is greater than the second gate width.