CN203366174U - Output dynamic adjusting circuit of low dropout regulator (LDO) - Google Patents
Output dynamic adjusting circuit of low dropout regulator (LDO) Download PDFInfo
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- CN203366174U CN203366174U CN 201320325579 CN201320325579U CN203366174U CN 203366174 U CN203366174 U CN 203366174U CN 201320325579 CN201320325579 CN 201320325579 CN 201320325579 U CN201320325579 U CN 201320325579U CN 203366174 U CN203366174 U CN 203366174U
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Abstract
The utility model relates to an output dynamic adjusting circuit of a low dropout regulator (LDO). Through the combination of a digital circuit and a simulation circuit, a load control circuit generates control signals according to changes of loads, the output dynamic control circuit in the LDO is used for dynamically controlling combination, different in current output capacity, designed according to proportions to output needed currents. The load control circuit simultaneously controls load changes and changes of output currents of the LDO to realize dynamic, quick and accurate matching of loads and currents needed by the loads. When the loads change, the circuit can simultaneously adjust the magnitude of output currents to meet output requirements, and eliminates impact of rapid changes of the loads on output voltage. Meanwhile, according to the output dynamic adjusting circuit, the output dynamic control circuit and the LDO output circuit are placed at intervals through the interwoven wiring technology, so that the responding speed of the output circuit is improved, the interference of power noise to the LDO circuit is reduced, and the performance of the LDO circuit is improved.
Description
Technical field
The utility model belongs to the power management techniques field, is specifically related to structure and the layout design of output dynamically regulated circuit and the control circuit thereof of a kind of low pressure difference linear voltage regulator LDO.
Background technology
Low pressure difference linear voltage regulator 101(is hereinafter to be referred as LDO) there is the advantages such as cost is low, output noise is little, circuit is simple, chip occupying area is little, in the SoC(SOC (system on a chip)) be widely used in chip, LDO produces the power vd D2 that supplies with digital circuit 102 according to the VDD1 to its input, as shown in Figure 1.
The essence of LDO is that the burning voltage that utilizes band-gap reference to produce and negative feedback control loop obtain one substantially not with the output voltage of environmental change.Existing typical LDO as shown in Figure 2, specifically comprises: efferent duct MP1, error amplifier OA, resistance-feedback network.Its basic functional principle is: resistance-feedback network produces feedback voltage, error amplifier OA amplifies the error between feedback voltage and reference voltage, amplify output through adjusting pipe again, form thus negative feedback, feedback voltage is clamped down on the current potential Vref of reference voltage, and then output voltage is clamped down on the current potential of needs.Because feedback voltage equals Vout*R2/ (R1+R2), converse output voltage V out=(1+R1/R2) Vref.Like this, by the ratio of simple adjustment R1 and R2, just can obtain required voltage.In Fig. 2, the dotted line frame is depicted as load circuit 103.
For higher load capacity is arranged, the area of general efferent duct MP1 is larger, grid at efferent duct MP1 forms the electric capacity up to tens of pF, simultaneously in order to reduce the power consumption of LDO, static working current is very little, make the Slew Rate SR=Ig/Cg of LDO very little, wherein, Cg is efferent duct grid equivalent capacity, and Ig is grid impulse electricity electric current, slower thereby the grid voltage of MP1 pipe changes, cause the drain current of MP1 pipe also to change slowly thereupon, when the output current saltus step, the recovery stabilization time that output voltage need to be longer, and can produce high due to voltage spikes.
Simultaneously, increase along with the SoC chip power-consumption, adopted multinomial power consumption control technology in the design of SoC chip, comprise chip is divided into to a plurality of voltage domains, the a certain functional module of chip without when work by its dump to save power consumption, this makes the load meeting of LDO that dynamic change fast occur.In some cases, when even whole loads of LDO are all without work, whole outputs of LDO all need to be cut off farthest to save power consumption, typical circuit as shown in Figure 3.When the MP2 conducting, the grid of MP1 is forced to draw high VDD1 and then causes MP1 to turn-off.Because the dynamic power management of chip completes usually in digital circuit, digital circuit is operated in the VDD2 voltage domain, and VDD2 is by LDO output but LDO is operated in the VDD1 voltage domain.The signal PDB that the control signal of digital circuit need to be converted to the VDD1 voltage domain from the signal of VDD2 voltage domain by level shifting circuit (Level Shift) controls the grid of MP2 again.
Because MP1 is very large, usually with how finger (Multi-finger) MOS transistor circuit is realized.Because total grid capacitance of MP1 is very large, make the time that MP2 need to be longer when shutoff/conducting MP1, especially the MOS transistor away from exporting from MP2 in MP1, have larger dead resistance and electric capacity to cause its shutoff/conducting that larger time delay is arranged from outputing to its grid of MP2.When the MP2 conducting, its original function is that the grid A point current potential of MP1 is equaled to the current potential of VDD1 and MP1 is turn-offed.Yet for above-mentioned reasons, A point current potential equals the VDD1 current potential larger time delay.That is, the current potential of VDD1 when t1 will could arrive the grid of MP1 when t2, and also there is difference the time of the grid of the different Finger of arrival MP1.Like this, while on power vd D1, high frequency noise being arranged, as, when t0, the voltage of VDD1 is V0, when t1 due to the impact of noise, the voltage of VDD1 is V0+Vnoise, and when t1, due to the reason postponed, voltage on the MP1 grid remains V0 and its source voltage is V0+Vnoise, like this, the pressure reduction of Vnoise is just arranged between its grid source, cause MP1 can't turn-off and then cause larger leakage current fully.
Because MP1 is very large, when high frequency noise is larger, can cause larger leakage current, when serious, make when turn-offing the output of LDO its output VDD2 from zero potential away from, even cause the output of level shifting circuit undesired and further cause LDO to turn-off fully.
Therefore, in order to overcome the recovery stabilization time that LDO output voltage mentioned above need to be longer, and can produce high due to voltage spikes problem.Many researchers has been done large quantity research and has been proposed some solutions.Yet these solutions all concentrate on by various means and strengthen the grid current of LDO efferent duct to alleviate this problem.Its ultimate principle still utilizes negative feedback loop to change the output current of LDO efferent duct after load changes.This adjustment of just carrying out after load changes itself is exactly passive type, can't eliminate the time delay between load change and LDO output change fully and just reduce this time delay, thereby can't eliminate the due to voltage spikes that this time delay causes.In addition, this needs extra mimic channel, has increased power consumption.
The utility model content
The purpose of this utility model is to provide a kind of output dynamically regulated circuit of low pressure difference linear voltage regulator, combination by digital circuit and mimic channel, produce control signal by load control circuit according to the variation of load, then the dynamic output control circuit in LDO is dynamically controlled the combination of the different electric current fan-out capabilities of design in proportion and is exported required electric current, realize the dynamically exact matching fast of load and its required electric current, when eliminating load and sharply changing to the impact of output voltage.Simultaneously, the utility model is put dynamic output control circuit and LDO output circuit interval by the interwoven line technology, to improve the response speed of output circuit, alleviates the interference of power supply noise to the LDO circuit, thereby improves the performance of LDO circuit.
In order to achieve the above object, the technical solution of the utility model is to provide a kind of output dynamically regulated circuit of low pressure difference linear voltage regulator, and it is provided with load control circuit, dynamic output control circuit, LDO output circuit and load circuit;
Wherein, described load control circuit, to the described load circuit be attached thereto, is exported a road and can dynamically be adjusted according to application demand the first control signal of load variations in described load circuit;
Described load control circuit is also simultaneously to the described dynamic output control circuit be attached thereto, and exports another road and can control the second control signal that the output signal of described dynamic output control circuit is changed according to described load variations;
Described dynamic output control circuit is under the control of described the second control signal, export corresponding the 3rd control signal to the described LDO output circuit be attached thereto, export needed electric current to control this LDO output circuit to the described load circuit be attached thereto, the curent change caused because of load variations with coupling.
Described load control circuit comprises:
A plurality of the first electronic switches, whether corresponding and a plurality of described load circuits are connected, with the load of controlling each load circuit, with the electric current of the corresponding output of described LDO output circuit, connect;
Totalizer, added up to connecting the required total current of all loads, the electric current that need to export to obtain the LDO output circuit;
Code translator, the results conversion that described totalizer is calculated is the second control signal to described dynamic output control circuit output.
The described output dynamically regulated circuit be equipped with and described LDO output circuit, divide a plurality of branch circuits arranged according to fan-out capability;
Each branch circuit, comprise: one of them of set a plurality of the second electronic switches of described output dynamically regulated circuit, and one of them of set a plurality of minutes output circuits of described LDO output circuit, the corresponding output current size of controlling each minute output circuit be complementary with it of each described second electronic switch.
The n that described LDO output circuit arranges a described minute output circuit, it is output as 2
(n-1)the electric current of unit, n is positive integer, n=1,2,3 ...
Each described branch circuit further comprises one or more element circuits according to fan-out capability; The electric current of each 1 unit of described element circuit output; The n of described LDO output circuit minute output circuit, comprise 2
(n-1)individual described element circuit.
In each described element circuit, be provided with a unit electronic switch, and the electric current fan-out capability is respectively m unit output circuit of 1/m unit, m is positive integer;
Described unit electronic switch and described unit output circuit intersection layout, and, make this unit electronic switch be positioned at the center of described element circuit.
In each described element circuit, be provided with error amplifier OA, resistance-feedback network, belong to the first transistor MP1 of described LDO output circuit, and belong to the transistor seconds MP2 of described output dynamically regulated circuit;
Wherein, the load of described resistance-feedback network and described load circuit, be connected between the drain electrode and ground of described the first transistor MP1; Described resistance-feedback network also is connected to the negative input end of described error amplifier OA, and feedback voltage is provided; After described error amplifier OA amplifies the error of the reference voltage of its positive input terminal and described feedback voltage, export the grid of described the first transistor MP1 to, form negative feedback;
The grid of described transistor seconds MP2 connects described load control circuit, receives the second control signal; The drain electrode of this transistor seconds MP2 is connected to the source electrode of described the first transistor MP1 and realizes the control to this first transistor MP1.
The beneficial effects of the utility model are: by using the combination of digital circuit and mimic channel, switching in the time of control load circuit and LDO output circuit, realized the active switching of LDO output circuit, the due to voltage spikes of having avoided the relative load circuit handoff delay of LDO output circuit to cause.And in the required load control circuit of the utility model, extra totalizer and code translator can be realized with software fully in the SoC chip of MCU is much arranged, thereby without extra circuit and power consumption.
Simultaneously, by output control circuit and output circuit cooperation are divided into to a plurality of branch circuits by fan-out capability and further it are decomposed into to element circuit and use the intersection layout to make output control circuit be positioned at the center of element circuit, the load of the output control circuit in each element circuit is greatly alleviated like this.In addition, the output circuit that such layout makes the output control circuit in each element circuit control apart from it is very near.Above 2 make output circuit to switch fast, thus the very little leakage current of having avoided power supply noise and having caused of time delay and then guarantee the effectively shutoff/conducting fast of output circuit.
The accompanying drawing explanation
Fig. 1 is the application example block diagram of LDO circuit in SoC in background technology;
Fig. 2 is the structural drawing of LDO circuit in background technology;
Fig. 3 is the structural drawing of the LDO circuit of band shutoff/conducting function in background technology;
Fig. 4 is the schematic block diagram of LDO dynamic load regulating circuit of the present utility model;
Fig. 5 is load control circuit structural drawing of the present utility model;
Fig. 6 is output control circuit of the present utility model and output circuit schematic diagram;
Fig. 7 is output control circuit of the present utility model and output circuit domain schematic diagram;
Fig. 8 is output control circuit of the present utility model and output circuit instance graph.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the utility model is further elaborated.
The utility model provides the output dynamically regulated circuit of a kind of low pressure difference linear voltage regulator (hereinafter to be referred as LDO), as shown in Figure 4, is provided with load control circuit 401, dynamic output control circuit 402, LDO output circuit 403 and load circuit 404.Wherein, load control circuit 401 outputs have road first control signal, and according to application demand, dynamically to adjust load circuit 404, load circuit 404 variations cause the electric current of needs to change; Therefore, load control circuit 401 has been exported another road second control signal according to the variation of load and has been controlled dynamic output control circuit 402 simultaneously; Control again the needed electric current of LDO output circuit 403 output load circuit 404 by dynamic output control circuit 402.
The enforcement of load control circuit 401 described in the utility model is by the combination of digital circuit and mimic channel, as shown in Figure 5, in the SoC(SOC (system on a chip)) on load control circuit basis itself that have, increase totalizer 501 and code translator 502 are arranged, omitted describing other device blocks in figure.The connection of controlling each load and LDO output voltage by a plurality of electronic switches (there is shown two electronic switches 1101 and 1102) whether.Connect the needed total current of all loads by 501 pairs of totalizers and added up, obtain the working current that LDO need to export.Then, produce the needed signal of dynamic output control circuit by code translator 502.A plurality of electronic switches of control load circuit are switched when code translator 502 produces control signal, come proof load and LDO output current to change to accomplish the optimum matching of load and LDO fan-out capability at synchronization.
Described totalizer 501 and code translator 502 can be realized with any general hardware of totalizer and code translator; And the MCU(micro-control unit is being arranged) or the SoC of CPU in, totalizer 501 and code translator 502 also can only realize with corresponding software without additional hardware, above-mentioned two schemes is not just done detailed discussion here.
Described dynamic output control circuit 402 and LDO output circuit 403, as shown in Figure 6, dynamic output control circuit 402 and LDO output circuit 403 are matched, and being divided into a plurality of branch circuits by fan-out capability, each branch circuit further is decomposed into one or more element circuits (hereinafter can this element circuit of specific explanations) by its fan-out capability.By a plurality of electronic switches (be expressed as in the drawings 1301,1302 ... Deng), control the LDO output circuit mated separately with it each branch (correspondingly in the drawings be expressed as 1401,1402 ... Deng) size of output current is controlled.
In a specific embodiment, first output circuit 1,401 1 units of output are as the electric current of 1mA, second output circuit 1402 exported the electric current of 2 units as 2mA, 4 units of the 3rd output circuit (not shown) output, as the electric current of 4mA, increase progressively successively n output circuit and will export 2
(n-1)unit is as 2
(n-1)the electric current of mA.Like this, by the combination of a plurality of electronic switches, just can generate the currents combination of precision within 1 unitary current.
Described dynamic output control circuit 402 and LDO output circuit 403, become the element circuit of 1 unitary current output as 1mA by a plurality of branch circuit Further Divisions.First electronic switch 1301 is comprised of 1 element circuit with its output circuit 1401; Second electronic switch 1302 is comprised of 2 element circuits with its output circuit 1402; N electronic switch and its output circuit are by 2
(n-1)individual element circuit forms.
As shown in Figure 7, each element circuit (in figure with shadow representation) is by the electronic switch of an output control circuit, control four fan-out capabilities and be 1/4 unit as the output transistor circuit of 0.25mA (, the branch of LDO output circuit), therefore each element circuit can provide the electric current output of 1 unit as 1mA.In laying out pattern as shown in Figure 7, by intersecting layout, make output control circuit be positioned at the center of element circuit output control circuit and output circuit, the time delay with the load that alleviates electronic switch and electronic switch on/off to the LDO output circuit.
Practical circuit in the utility model as shown in Figure 8, is provided with error amplifier OA, as the first transistor MP1 of output circuit 403, as dynamically transistor seconds MP2, resistance-feedback network and the load circuit 404 of output control circuit 402.Wherein dynamically output control circuit 402 and output circuit 403 are realized by the PMOS circuit.But, according to actual conditions, output control circuit is available nmos circuit or transmission gate realization also.
Described resistance-feedback network is used for producing feedback voltage, and resistance R 1, R2 are connected between the drain electrode and ground of the first transistor MP1, from being connected to the negative input end of error amplifier OA between these two resistance R 1, R2; Error amplifier OA amplifies the error between feedback voltage and reference voltage, then amplifies output through the first transistor MP1, forms thus negative feedback, feedback voltage is clamped down on the current potential Vref of reference voltage, and then output voltage is clamped down on the current potential of needs.Because feedback voltage equals Vout*R2/ (R1+R2), converse output voltage V out=(1+R1/R2) Vref.Therefore, by the ratio of simple adjustment R1 and R2, just can obtain required voltage.Load circuit 404 in Fig. 8 is for being connected in parallel on drain electrode and the resistance R L between ground and the electric capacity of the first transistor MP1.
Referring to Fig. 8, the transistor seconds MP2(in the utility model is output control circuit 402) to the first transistor MP1(, be output circuit 403) source electrode rather than grid controlled (background technology that the latter sees Fig. 3).Such benefit is that the source capacitance of MP1 has alleviated the load of output control circuit much smaller than its grid capacitance.In addition, it is independent that the grid A point of MP1 can keep, and is not subject to the impact of output control circuit to become stationary singnal.
Dynamic output control circuit 402 shown in Fig. 8 and output circuit 403 be the example of an element circuit just.The grid of the output circuit of all element circuits can directly link together, but in the unit circuit, the control signal PD of output control circuit may be different.Like this, the load of the output control circuit in each element circuit is lighter, can reach the function of quick unlatching output circuit.
In sum, the output dynamically regulated circuit of LDO of the present utility model, combination by digital circuit and mimic channel, produce control signal by load control circuit according to the variation of load, then the dynamic output control circuit in LDO is dynamically controlled the combination of the different electric current fan-out capabilities of design in proportion and is exported required electric current.The variation of load control circuit control load variation simultaneously and LDO output current realizes the dynamically quick exact matching of load and its required electric current.When load variations, this circuit can be adjusted the output current size simultaneously and meet the output demand, when eliminating load and sharply changing to the impact of output voltage.Simultaneously, the utility model puts by dynamic output control circuit and LDO output circuit interval the response speed that has improved output circuit by the interwoven line technology, has alleviated the interference of power supply noise to the LDO circuit, has improved the performance of LDO circuit.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present utility model, should be understood to that protection domain of the present utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these technology enlightenments of the utility model, and these distortion and combination are still in protection domain of the present utility model.
Claims (7)
1. the output dynamically regulated circuit of a low pressure difference linear voltage regulator, is characterized in that, is provided with load control circuit (401), dynamic output control circuit (402), LDO output circuit (403) and load circuit (404);
Wherein, described load control circuit (401), to the described load circuit (404) be attached thereto, is exported a road and can dynamically be adjusted according to application demand the first control signal of load variations in described load circuit (404);
Described load control circuit (401) is also simultaneously to the described dynamic output control circuit (402) be attached thereto, and exports another road and can control the second control signal that the output signal of described dynamic output control circuit (402) is changed according to described load variations;
Described dynamic output control circuit (402) is under the control of described the second control signal, export corresponding the 3rd control signal to the described LDO output circuit (403) be attached thereto, export needed electric current to control this LDO output circuit (403) to the described load circuit (404) be attached thereto, the curent change caused because of load variations with coupling.
2. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that,
Described load control circuit (401) comprises:
A plurality of the first electronic switches, whether corresponding and a plurality of described load circuits (404) are connected, with the load of controlling each load circuit (404), with the electric current of the corresponding output of described LDO output circuit (403), connect;
Totalizer (501), added up to connecting the required total current of all loads, needs the electric current of output to obtain LDO output circuit (403);
Code translator (502), the results conversion that described totalizer (501) is calculated is the second control signal to described dynamic output control circuit (402) output.
3. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 1 or 2, is characterized in that,
The described output dynamically regulated circuit (402) be equipped with and described LDO output circuit (403), divide a plurality of branch circuits arranged according to fan-out capability;
Each branch circuit, comprise: one of them of set a plurality of the second electronic switches of described output dynamically regulated circuit (402), and one of them of set a plurality of minutes output circuits of described LDO output circuit (403), the corresponding output current size of controlling each minute output circuit be complementary with it of each described second electronic switch.
4. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 3, is characterized in that,
The n that described LDO output circuit (403) arranges a described minute output circuit, it is output as 2
(n-1)the electric current of unit, n is positive integer, n=1,2,3 ...
5. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 4, is characterized in that,
Each described branch circuit further comprises one or more element circuits according to fan-out capability; The electric current of each 1 unit of described element circuit output; The n of described LDO output circuit (403) minute output circuit, comprise 2
(n-1)individual described element circuit.
6. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 5, is characterized in that,
In each described element circuit, be provided with a unit electronic switch, and the electric current fan-out capability is respectively m unit output circuit of 1/m unit, m is positive integer;
Described unit electronic switch and described unit output circuit intersection layout, and, make this unit electronic switch be positioned at the center of described element circuit.
7. the output dynamically regulated circuit of low pressure difference linear voltage regulator as claimed in claim 6, is characterized in that,
In each described element circuit, be provided with error amplifier (OA), resistance-feedback network, belong to the first transistor (MP1) of described LDO output circuit (403), and belong to the transistor seconds (MP2) of described output dynamically regulated circuit (402);
Wherein, the load of described resistance-feedback network and described load circuit (404), be connected between the drain electrode and ground of described the first transistor (MP1); Described resistance-feedback network also is connected to the negative input end of described error amplifier (OA), and feedback voltage is provided; After described error amplifier (OA) amplifies the error of the reference voltage of its positive input terminal and described feedback voltage, export the grid of described the first transistor (MP1) to, form negative feedback;
The grid of described transistor seconds (MP2) connects described load control circuit (401), receives the second control signal; The drain electrode of this transistor seconds (MP2) is connected to the source electrode of described the first transistor (MP1) and realizes the control to this first transistor (MP1).
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320325579 CN203366174U (en) | 2013-06-07 | 2013-06-07 | Output dynamic adjusting circuit of low dropout regulator (LDO) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320325579 CN203366174U (en) | 2013-06-07 | 2013-06-07 | Output dynamic adjusting circuit of low dropout regulator (LDO) |
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| CN203366174U true CN203366174U (en) | 2013-12-25 |
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| CN 201320325579 Withdrawn - After Issue CN203366174U (en) | 2013-06-07 | 2013-06-07 | Output dynamic adjusting circuit of low dropout regulator (LDO) |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324234A (en) * | 2013-06-07 | 2013-09-25 | 灿芯半导体(上海)有限公司 | Output dynamic regulation circuit of low dropout linear regulator (LDO) |
| CN103941798A (en) * | 2014-04-30 | 2014-07-23 | 杭州士兰微电子股份有限公司 | Low dropout regulator |
| CN105388956A (en) * | 2015-11-13 | 2016-03-09 | 上海斐讯数据通信技术有限公司 | Dynamic adjustment method and system for load current and electronic equipment |
| WO2018094580A1 (en) * | 2016-11-22 | 2018-05-31 | 深圳市汇顶科技股份有限公司 | Low dropout voltage stabilising apparatus |
-
2013
- 2013-06-07 CN CN 201320325579 patent/CN203366174U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324234A (en) * | 2013-06-07 | 2013-09-25 | 灿芯半导体(上海)有限公司 | Output dynamic regulation circuit of low dropout linear regulator (LDO) |
| CN103324234B (en) * | 2013-06-07 | 2015-05-06 | 灿芯半导体(上海)有限公司 | Output dynamic regulation circuit of low dropout linear regulator (LDO) |
| CN103941798A (en) * | 2014-04-30 | 2014-07-23 | 杭州士兰微电子股份有限公司 | Low dropout regulator |
| CN103941798B (en) * | 2014-04-30 | 2015-12-02 | 杭州士兰微电子股份有限公司 | Low pressure difference linear voltage regulator |
| CN105388956A (en) * | 2015-11-13 | 2016-03-09 | 上海斐讯数据通信技术有限公司 | Dynamic adjustment method and system for load current and electronic equipment |
| WO2018094580A1 (en) * | 2016-11-22 | 2018-05-31 | 深圳市汇顶科技股份有限公司 | Low dropout voltage stabilising apparatus |
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Granted publication date: 20131225 Effective date of abandoning: 20150506 |
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