CN112114611A - Circuit for improving transient response speed of voltage mode control loop - Google Patents
Circuit for improving transient response speed of voltage mode control loop Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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Abstract
A circuit capable of improving transient response speed of a voltage mode control loop can push a second zero point of a compensation network to a high frequency position by reducing a resistance value of a loop access resistor, so that transient response speed of a system loop is improved.
Description
Technical Field
The invention relates to a voltage mode control loop transient response technology in a power management chip, in particular to a circuit for improving the transient response speed of a voltage mode control loop.
Background
In a power management chip, voltage mode feedback is a common loop control mode. However, since the inductor and the capacitor in the voltage mode loop form a second-order LC filter network, a dual pole is formed to cause insufficient phase margin, thereby affecting the loop stability, and therefore an additional compensation network is required to compensate the loop. The TPYE-iii type compensation network is often used in voltage mode loop compensation due to its one pole-zero, two zeros and two poles. When the system is switched from the DCM Mode (discontinuous Conduction Mode) to the CCM Mode (Continuous Conduction Mode), the output of the error amplifier ea (error amplifier) rises slowly due to the influence of the compensation network zero point, so that the transient response of the output voltage is degraded.
Fig. 1 is a schematic diagram of a conventional voltage mode control loop structure. As shown in fig. 1, the dotted square box is a typical TYPE-iii compensation network structure, and the compensation network poles-zero (one pole-zero, two zeros, and two poles) are distributed as follows:
normally, to satisfy the stability of the loop phase margin, the zero point f needs to be setz0、fz1Is arranged at the double pole of the power stage, and meanwhile, in order to ensure the stability of other loops, the value of the resistor R1 (namely the loop access resistor in the compensation network) is larger, and then the zero point f is largerz0Are relatively low. When the load jumps from light load to heavy load, i.e. the system is switched from DCM to CCM mode, the output eao of the error amplifier (i.e. the error output voltage Veao) will increase, so that the duty cycle of the pwm (pulse width modulation) signal increases. Since the zero point satisfies the phase margin of the loop, the response speed is slow, eao rises slowly, the rising speed of the load current is slow, and the transient response of the output voltage Vout is deteriorated.
Fig. 2 is a schematic diagram showing the time-varying output voltage Vout, feedback output voltage Vfbo, error output voltage Veao, and inductor current IL in fig. 1. Fig. 2 shows that when the load jumps, i.e., the load resistance RL suddenly increases or suddenly decreases, the output voltage Vout suddenly increases or decreases, and the response time of the output voltage Veao of the error amplifier is slow, so that the time for the output voltage Vout to return to the normal value is long, and the transient response is poor. The inventor believes that, for the case that the value of the loop access resistor R1 is large, if the loop access resistor R1 is split into a series structure of two resistors, one large resistor and one small resistor, and the large resistor is connected in parallel with the short-circuit switch controlled by the loop response speed boosting circuit, the second zero fz0 of the compensation network can be pushed to a high frequency by reducing the resistance value of the loop access resistor, so as to improve the transient response speed of the system loop. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a circuit for improving the transient response speed of a voltage mode control loop, which divides a loop access resistor in a compensation network into a series structure of a large resistor and a small resistor, and connects the large resistor in parallel with a short-circuit switch controlled by a loop response speed boosting circuit, and can push a second zero point of the compensation network to a high frequency position by reducing the resistance value of the loop access resistor, thereby improving the transient response speed of a system loop.
The technical scheme of the invention is as follows:
a circuit for improving the transient response speed of a voltage mode control loop comprises a system loop transient response compensation network, wherein the compensation network comprises a loop access resistor R1, and the circuit is characterized in that the loop access resistor R1 is a series structure of a loop access first resistor R11 and a loop access second resistor R12, the loop access first resistor R11 is connected in parallel with a short-circuit switch, and the control end of the short-circuit switch is connected with a switch control circuit.
The short-circuit switch is a third NMOS tube, a source electrode of the third NMOS tube is connected with a feedback output voltage end of the first comparator through a loop access second resistor R12, a drain electrode of the third NMOS tube is connected with a negative input end of the error amplifier, the loop access first resistor R11 is located between the source electrode and the drain electrode of the third NMOS tube, and a grid electrode of the third NMOS tube is connected with the switch control circuit.
The switch control circuit is a loop response speed boosting circuit, a control signal output end of the loop response speed boosting circuit is connected with a grid electrode of the third NMOS tube, a first input end of the loop response speed boosting circuit is connected with a second reference voltage end, the second reference voltage end is connected with a positive input end of the error amplifier, and a second input end of the loop response speed boosting circuit is connected with a feedback output voltage end of the first comparator.
The loop response speed boost circuit comprises a third comparator and a fourth comparator (both of which are hysteresis comparators generally), wherein a positive input end of the third comparator and a positive input end of the fourth comparator are both connected with the feedback output voltage end, a negative input end of the third comparator and a negative input end of the fourth comparator are both connected with the second reference voltage end, an output end of the third comparator and an output end of the fourth comparator are respectively connected with a nor logic device, and the nor logic device is connected with a grid electrode of the third NMOS tube through a phase inverter.
The outer end of the loop access first resistor R11 is connected with one end of a second capacitor through a third resistor, and the other end of the second capacitor is connected with the outer end of the loop access second resistor R12.
A third capacitor is connected in parallel between the negative input end and the output end of the error amplifier, the output end of the error amplifier is connected with the negative input end of the error amplifier through a second resistor and a first capacitor, the output end of the error amplifier is connected with the positive input end of a second comparator, the negative input end of the second comparator is connected with a third reference voltage end, and the output end of the second comparator is connected with a driving circuit.
The negative input end of the first comparator is connected with a first reference voltage end, and the positive input end of the first comparator is connected with an output voltage feedback node.
The output voltage feedback node is connected with an output voltage end through a first feedback resistor and is grounded through a second feedback resistor.
The output voltage end is grounded through a load resistor, the output voltage end is grounded through a load capacitor, the output voltage end is respectively connected with a source electrode of a first NMOS tube and a drain electrode of a second NMOS tube through an inductor, the source electrode of the second NMOS tube is grounded, a grid electrode of the second NMOS tube is connected with a driving circuit, the drain electrode of the first NMOS tube is connected with an input voltage end, and the grid electrode of the first NMOS tube is connected with the driving circuit.
The resistance value of the loop-in first resistor R11 is greater than the resistance value of the loop-in second resistor R12 (generally R11> > R12).
The invention has the following technical effects: the invention relates to a circuit for improving the transient response speed of a voltage mode control loop, which improves a compensation network, automatically detects the difference value of a feedback voltage and the reference voltage of an error amplifier under the condition of ensuring that the stability of the system loop is not influenced, and reduces a resistor to push a second zero point of the compensation network to a high frequency position by a loop response boosting circuit after the difference value of the feedback output voltage and the reference voltage of the error amplifier exceeds a certain range, thereby improving the response speed of the system loop. The invention has the following characteristics: 1. the feedback output voltage and the reference voltage are automatically monitored, and a plurality of feedback loops can be optimized simultaneously. 2. The structure is simple, and the purpose of accelerating loop response can be realized without additional complex design. 3. Is not easy to be triggered by mistake, has stable and reliable circuit structure, realizes the dynamic compensation of the loop, improves the transient response speed of the system and does not influence the stability of the loop
Drawings
Fig. 1 is a schematic diagram of a conventional voltage mode control loop structure. The dotted box in fig. 1 is a typical TYPE-iii compensation network structure, where resistors R and capacitors C (R1 and C1, R1 and C2, R2 and C1, R3 and C2, R2 and C3) form compensation network zeros fz and pole fp distributions (fp0, fz0, fz1, fp1, fp2, i.e. one zero pole, two zeros and two poles).
Fig. 2 is a schematic diagram showing the time-varying output voltage Vout, feedback output voltage Vfbo, error output voltage Veao, and inductor current IL in fig. 1. In FIG. 2, the abscissa (time) scale is 0-0.5-1-1.5-2-2.5-3-3.5-4-4.5 seconds, the ordinate scale of Vout is 0.5-1.5-2.5-3.5-4 volts (V), the ordinate scale of Vfbo is 0-0.2-0.4-0.6-0.8-1.2 volts (V), the ordinate scale of Veao is 0.6-0.8-1-1.2-1.4-1.6 volts (V), and the ordinate scale of IL is 0-0.5-1-1.5-2-2.5-3 amperes (A).
Fig. 3 is a schematic diagram of a circuit structure for improving the transient response speed of a voltage mode control loop according to the present invention. The dashed box in FIG. 3 is a compensation network structure, where R11 and R12 correspond to R1 in FIG. 1, and the total resistance of R11 and R12 is R1, but R11> > R12. The loop response speed boosting circuit ea-tran-helper within the dashed line box is an additional circuit structure added to fig. 1 to achieve the conversion speed improvement.
Fig. 4 is a schematic diagram showing the time (abscissa time) variation of the output signal extra, the input signal Vref2 and the input signal Vfbo involved in the loop response speed boost circuit ea-tran-helper in fig. 3. In fig. 4, when the difference between Vref2 and Vfbo exceeds a certain range, extra is high Vhigh; when the difference between Vref2 and Vfbo is within a certain range, extra is low Vlow. The high level enables the M3 to be opened, namely, the short circuit is realized through the R11, the loop access resistance is R12, the R12 is small resistance, and the R1 is R12, so that fz0 is pushed to high frequency, the loop response speed is increased, Veao rising is accelerated, and Vout is kept stable; the low level turns off the M3, the loop-in resistance at this time is "R11 + R12", that is, R1 — R11+ R12, and the compensation network structure returns to the original normal mode.
Fig. 5 is a schematic structural diagram of the loop response speed boosting circuit ea-tran-helper in fig. 3.
Fig. 6 is a schematic diagram showing the time-varying output voltage Vout, feedback output voltage Vfbo, error output voltage Veao, and inductor current IL in fig. 3. The change of the output voltage Vout when the load changes in fig. 6 is more stable than that in fig. 2, that is, the loop transient response speed of the circuit of fig. 3 of the present invention is increased compared to the loop transient response speed of the prior art circuit of fig. 1.
The reference numbers are listed below: vin-input voltage or input voltage terminal; vout-output voltage or output voltage terminal; vref1 — first reference voltage or first reference voltage terminal; vref2 — a second reference voltage or second reference voltage terminal; vramp-third reference voltage or third reference voltage terminal; Drive-Drive circuit; ea-tran-helper-loop response speed boosting circuit; comp 1-first comparator; comp 2-second comparator; comp 3-third comparator (e.g., Hysteresis comparator, etc.); comp 4-fourth comparator (e.g., Hysteresis comparator, etc.); EA-error amplifier; PWM-pulse width modulation (pulse width modulation); NORgate-NOR logic; a NOTGate-inverter; veao-error output voltage; vfbo-feedback output voltage; vfb-output voltage feedback node; r1-loop access resistance; r2 — second resistance; r3 — third resistance; r11-loop into the first resistance; r12-loop into the second resistance; rf1 — first feedback resistance; rf2 — second feedback resistance; RL-fourth resistance (i.e., load resistance); m1-first NMOS transistor; m2-second NMOS tube; m3-third NMOS tube; an L-inductor; c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; c-fourth capacitance (i.e., load capacitance); and an extra-short circuit switch control signal or loop response speed boosting signal output end.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 3-6).
Fig. 3 is a schematic diagram of a circuit structure for improving the transient response speed of a voltage mode control loop according to the present invention. Fig. 4 is a schematic diagram showing the time (abscissa time) variation of the output signal extra, the input signal Vref2 and the input signal Vfbo involved in the loop response speed boost circuit ea-tran-helper in fig. 3. Fig. 5 is a schematic structural diagram of the loop response speed boosting circuit ea-tran-helper in fig. 3. Fig. 6 is a schematic diagram showing the time-varying output voltage Vout, feedback output voltage Vfbo, error output voltage Veao, and inductor current IL in fig. 3. Referring to fig. 3 to 6, a circuit for improving the transient response speed of a voltage mode control loop includes a system loop transient response compensation network (e.g., a circuit in a dashed box in fig. 3), where the compensation network includes a loop access resistor R1 (refer to fig. 1), the loop access resistor R1 is a series structure of a loop access first resistor R11 and a loop access second resistor R12, the loop access first resistor R11 is connected in parallel to a short-circuit switch (e.g., M3), and a control end of the short-circuit switch is connected to a switch control circuit. The short-circuit switch is a third NMOS transistor M3, the source of the third NMOS transistor M3 is connected to the feedback output voltage end Vfbo of the first comparator Comp1 through a loop access second resistor R12, the drain of the third NMOS transistor M3 is connected to the negative input terminal (-) of the error amplifier EA, the loop access first resistor R11 is located between the source and the drain of the third NMOS transistor M3, and the gate of the third NMOS transistor M3 is connected to the switch control circuit. The switch control circuit is a loop response speed boosting circuit EA-tran-helper, a control signal output end extra of the loop response speed boosting circuit EA-tran-helper is connected with a grid electrode of the third NMOS transistor M3, a first input end of the loop response speed boosting circuit EA-tran-helper is connected with a second reference voltage end Vref2, the second reference voltage end Vref2 is connected with a positive input end (+) of the error amplifier EA, and a second input end of the loop response speed boosting circuit EA-tran-helper is connected with a feedback output voltage end Vfbo of the first comparator Comp 1. The loop response speed boosting circuit ea-tran-helper includes a third comparator Comp3 and a fourth comparator Comp4, a positive input terminal (+) of the third comparator Comp3 and a positive input terminal (+) of the fourth comparator Comp4 are both connected to the feedback output voltage terminal Vfbo, a negative input terminal (-) of the third comparator Comp3 and a negative input terminal (-) of the fourth comparator Comp4 are both connected to the second reference voltage terminal Vref2, an output terminal of the third comparator Comp3 and an output terminal of the fourth comparator Comp4 are both connected to a nor gate, respectively, which is connected to the gate of the third NMOS transistor M3 through an inverter NOTgate. The outer end of the loop access first resistor R11 is connected with one end of a second capacitor C2 through a third resistor R3, and the other end of the second capacitor C2 is connected with the outer end of the loop access second resistor R12.
A third capacitor C3 is connected in parallel between a negative input (-) and an output of the error amplifier EA, the output of the error amplifier EA is connected to the negative input (-) of the error amplifier EA through a second resistor R2 and a first capacitor C1, the output of the error amplifier EA is connected to a positive input (+) of a second comparator Comp2, the negative input (-) of the second comparator Comp2 is connected to a third reference voltage terminal Vramp, and the output of the second comparator Comp2 is connected to a Drive circuit Drive. The negative input (-) of the first comparator Comp1 is connected to the first reference voltage terminal Vref1, and the positive input (+) of the first comparator Comp1 is connected to the output voltage feedback node Vfb. The output voltage feedback node Vfb is connected to the output voltage terminal Vout through a first feedback resistor Rf1, and the output voltage feedback node Vfb is grounded through a second feedback resistor Rf 2. The output voltage terminal Vout is grounded through a fourth resistor RL (i.e., a load resistor), the output voltage terminal Vout is grounded through a fourth capacitor C (i.e., a load capacitor), the output voltage terminal Vout is respectively connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2 through an inductor L, the source of the second NMOS transistor M2 is grounded, the gate of the second NMOS transistor M2 is connected to a driving circuit Drive, the drain of the first NMOS transistor M1 is connected to the input voltage terminal Vin, and the gate of the first NMOS transistor M1 is connected to the driving circuit Drive. The resistance value of the loop-in first resistor R11 is greater than the resistance value of the loop-in second resistor R12 (generally R11> > R12).
The invention realizes the improvement of the conversion speed by designing an additional loop response speed boosting circuit EA _ tran _ helper circuit structure, the structure of which is shown in fig. 3, the loop response speed boosting circuit EA _ tran _ helper circuit can automatically detect and compare the feedback output voltage fbo and the EA reference voltage Vref2, and when the difference value between the fbo voltage and the Vref voltage exceeds a certain range, an extra signal can output a high level to open the MOS transistor M3 to short circuit the resistor R11. The total resistance value of the resistor R11 and the resistor R12 is R1, but the resistor R11> > R12, when the system load suddenly jumps from light load to heavy load, namely, in the process of converting DCM to CCM, the loop response speed boosting circuit EA _ tran _ helper will cut off the resistor R11 to push the zero fz0 to a high frequency, so that the loop response speed is increased, and the EA output is increased. When the feedback output fbo rises or falls within a certain fixed range of the reference voltage Vref, the M3 tube is turned off by the extra signal output low level to connect the resistor R11 into the loop, and the compensation structure returns to the normal mode. For example, if the difference between Vref2 and Vfbo is large in fig. 4, extra is high Vhigh; near the intersection of Vref2 and Vfbo (i.e., when the difference is small), extra is low Vlow. The high level enables the M3 to be opened, namely, the short circuit is realized through the R11, the loop access resistance is R12, the R12 is small resistance, and the R1 is R12, so that fz0 is pushed to high frequency, the loop response speed is increased, Veao rising is accelerated, and Vout is kept stable; the low level turns off the M3, the loop-in resistance at this time is "R11 + R12", that is, R1 — R11+ R12, and the compensation network structure returns to the original normal mode. Vout in fig. 6 is more stable than Vout in fig. 2, i.e., the fig. 3 circuit of the present invention improves the loop transient response speed compared to the loop transient response speed of the prior art fig. 1.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalent, modified and/or simplified implementations as described above, e.g., implementations using other oscillator regulation circuits, etc., without departing from the spirit of the present invention, are intended to fall within the scope of the present invention.
Claims (10)
1. A circuit for improving the transient response speed of a voltage mode control loop comprises a system loop transient response compensation network, wherein the compensation network comprises a loop access resistor R1, and the circuit is characterized in that the loop access resistor R1 is a series structure of a loop access first resistor R11 and a loop access second resistor R12, the loop access first resistor R11 is connected in parallel with a short-circuit switch, and the control end of the short-circuit switch is connected with a switch control circuit.
2. The circuit of claim 1, wherein the short-circuit switch is a third NMOS transistor, a source of the third NMOS transistor is connected to the feedback output voltage terminal of the first comparator through a loop-in second resistor R12, a drain of the third NMOS transistor is connected to the negative input terminal of the error amplifier, the loop-in first resistor R11 is located between the source and the drain of the third NMOS transistor, and a gate of the third NMOS transistor is connected to the switch control circuit.
3. The circuit of claim 2, wherein the switch control circuit is a loop response speed boost circuit, a control signal output terminal of the loop response speed boost circuit is connected to the gate of the third NMOS transistor, a first input terminal of the loop response speed boost circuit is connected to a second reference voltage terminal, the second reference voltage terminal is connected to the positive input terminal of the error amplifier, and a second input terminal of the loop response speed boost circuit is connected to the feedback output voltage terminal of the first comparator.
4. The circuit for improving transient response speed of a voltage mode control loop according to claim 3, wherein the loop response speed boost circuit comprises a third comparator and a fourth comparator, a positive input terminal of the third comparator and a positive input terminal of the fourth comparator are both connected to the feedback output voltage terminal, a negative input terminal of the third comparator and a negative input terminal of the fourth comparator are both connected to the second reference voltage terminal, an output terminal of the third comparator and an output terminal of the fourth comparator are respectively connected to a nor logic device, and the nor logic device is connected to the gate of the third NMOS transistor through an inverter.
5. The circuit for improving the transient response speed of a voltage mode control loop of claim 1, wherein an outer end of said loop-in first resistor R11 is connected to one end of a second capacitor through a third resistor, and another end of said second capacitor is connected to an outer end of said loop-in second resistor R12.
6. The circuit of claim 2, wherein a third capacitor is connected in parallel between the negative input terminal and the output terminal of the error amplifier, the output terminal of the error amplifier is connected to the negative input terminal of the error amplifier through a second resistor and the first capacitor, the output terminal of the difference amplifier is connected to the positive input terminal of a second comparator, the negative input terminal of the second comparator is connected to a third reference voltage terminal, and the output terminal of the second comparator is connected to the driving circuit.
7. The circuit of claim 2, wherein a negative input terminal of the first comparator is coupled to a first reference voltage terminal and a positive input terminal of the first comparator is coupled to an output voltage feedback node.
8. The circuit of claim 7, wherein the output voltage feedback node is connected to an output voltage terminal through a first feedback resistor, and wherein the output voltage feedback node is connected to ground through a second feedback resistor.
9. The circuit of claim 8, wherein the output voltage terminal is grounded through a load resistor, the output voltage terminal is grounded through a load capacitor, the output voltage terminal is respectively connected to a source of a first NMOS transistor and a drain of a second NMOS transistor through an inductor, a source of the second NMOS transistor is grounded, a gate of the second NMOS transistor is connected to a driving circuit, a drain of the first NMOS transistor is connected to a supply voltage terminal, and a gate of the first NMOS transistor is connected to the driving circuit.
10. The circuit of claim 1 wherein the resistance of the first loop-in resistor R11 is greater than the resistance of the second loop-in resistor R12.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114200190A (en) * | 2021-12-14 | 2022-03-18 | 成都思瑞浦微电子科技有限公司 | Voltage difference value detection circuit |
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