CN111414035A - A Low Dropout Linear Regulator with Wide Input Voltage Range - Google Patents

Abstract

A low dropout linear regulator with a wide input voltage range comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feedforward path, a dynamic sampling module and an output detection module, wherein the source electrode of the power tube is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the power tube generates an output signal of the low dropout linear regulator; the voltage division network divides the output signal of the low dropout linear regulator to obtain a feedback signal; the bias module is used for providing bias; the error amplifier pre-amplifies the difference voltage of the feedback signal and the reference voltage and then transmits the difference voltage to a buffer stage and a feedforward path at the later stage, and the two paths with different speeds of the buffer stage and the feedforward path are converged at the grid end of the power tube to control the grid end voltage of the power tube in a charging and discharging way; the dynamic sampling module can improve the transient response speed of the system; the output detection module is used for detecting whether the output is normal in real time.

Description

A Low Dropout Linear Regulator with Wide Input Voltage Range

technical field

The invention belongs to the technical field of power management, and relates to a low-voltage linear voltage regulator, which can be used for power supply of an internal circuit of a chip.

Background technique

Low dropout linear regulator (Low Dropout Regulator, LDO) is an important type of circuit in power management chips. It has the advantages of low cost, low noise, low power consumption, simple circuit structure and small chip area, and is widely used in consumer electronics, medical electronics, aerospace and other fields.

There is a lot of noise in the voltage input outside the chip, so a stable and low-noise power supply is needed inside the chip to power the internal circuit. LDO is a good choice to power the internal circuit. The LDO controls the power tube by amplifying the error signal obtained by the output feedback to provide the output current to drive the load. As shown in Figure 1, a traditional off-chip large-capacitance LDO includes an error amplifier (EA), a power transistor, a resistor feedback network, and a load capacitor.

The traditional LDO that supplies power to the internal circuit of the chip needs to pre-step down the input voltage V _IN before powering the LDO. In terms of system stability, traditional LDOs use the Equivalent Series Resistance (ESR) of the output capacitor for frequency compensation. The main pole (Po) determined by the output capacitance and output impedance and the secondary pole (P _G ) determined by the parasitic capacitance of the power tube and the output impedance of the error amplifier are usually designed within the bandwidth of the loop, and the existence of ESR will produce a zero ( Z _ESR ), to compensate the phase margin to ensure that the gain curve crosses the 0dB line at -20dB/decade. Due to the large drift of the main pole Po, ESR is difficult to estimate with the change of frequency and temperature, which brings great difficulties to the stability design of the entire LDO, and the introduction of ESR is usually accompanied by large voltage spikes during transients , which deteriorates the transient characteristics of the LDO.

SUMMARY OF THE INVENTION

Aiming at the above-mentioned traditional low dropout linear voltage regulators that require pre-dropping and the stability and transient characteristics problems caused by using ESR for frequency compensation, the present invention proposes a low-dropout linear voltage regulator that does not require pre-dropping It can work directly in a wide input voltage range and the compensation is simple, and the input voltage can reach 5V-42V; the introduction of a feedforward path replaces the ESR zero point in the traditional low-dropout linear regulator, and the sampling load current achieves more Fast transient response, and introduce logic circuit at the output port to judge whether the output is correct.

The technical scheme of the present invention is:

A low-dropout linear regulator with a wide input voltage range includes an error amplifier, a power transistor, a voltage divider network, a bias module, a buffer stage, a feedforward path and a dynamic sampling module,

The power transistor is a PMOS power transistor, the source of which is connected to the input voltage of the low-dropout linear regulator, and the drain of which generates the output signal of the low-dropout linear regulator;

The voltage divider network is used to divide the output signal of the low dropout linear regulator to obtain a feedback signal;

The positive input terminal of the error amplifier is connected to the feedback signal, and the negative input terminal of the error amplifier is connected to the reference voltage;

The bias module is used to provide bias for the error amplifier, the buffer stage, the feedforward path and the dynamic sampling module, and includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a third PMOS transistor. An NMOS transistor, the gate-drain of the first PMOS transistor is short-circuited and connected to the gates of the second and third PMOS transistors and the first external bias signal, and its source is connected to the second PMOS transistor, the third PMOS transistor and the third PMOS transistor. The sources of the four PMOS transistors are connected to the input voltage of the low-dropout linear regulator; the gate-drain of the first NMOS transistor is short-circuited and connected to the drain of the second PMOS transistor, and its source is connected to the negative direction of the error amplifier an output end; the gate of the fourth PMOS transistor is connected to the second external bias signal;

The buffer stage includes a second NMOS transistor and a third NMOS transistor. The source of the second NMOS transistor is connected to the forward output end of the error amplifier, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the second NMOS transistor is connected The gate of the third NMOS transistor and the drain of the third PMOS transistor; the drain of the third NMOS transistor is connected to the input voltage of the low dropout linear regulator, and the source of the third NMOS transistor is connected to the gate of the power transistor and the fourth PMOS transistor the drain;

The feedforward path includes a fourth NMOS transistor and a fifth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, the drain of the fourth NMOS transistor is connected to the gate of the power transistor, and the source of the fourth NMOS transistor is connected to the fifth NMOS transistor. the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the negative output terminal of the error amplifier, and its source is grounded;

The dynamic sampling module includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a fifth PMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the seventh NMOS transistor. The gate and drain of the eighth NMOS transistor and the drain of the eighth NMOS transistor, its source is connected to the source of the seventh NMOS transistor and grounded; the gate of the eighth NMOS transistor is connected to the drain of the power transistor, and its source is connected to the fifth PMOS The drain of the tube; the gate of the fifth PMOS tube is connected to the gate of the power tube, and its source is connected to the input voltage of the low-dropout linear regulator;

The low-dropout linear regulator also includes a first Zener diode and a second Zener diode, the cathode of the first Zener diode is connected to the input voltage of the low-dropout linear regulator, and the anode is connected to the third NMOS transistor. a grid; the cathode of the second Zener diode is connected to the input voltage of the low-dropout linear regulator, and the anode is connected to the grid of the power tube;

The power tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the fourth NMOS tube, the eighth NMOS tube and the fifth PMOS tube are: High voltage device.

Specifically, the low dropout linear regulator further includes an output detection module, the output detection module includes a first inverter, a second inverter, a sixth PMOS transistor, a seventh PMOS transistor, a ninth NMOS transistor, and The tenth NMOS tube,

The gate of the ninth NMOS transistor is connected to the feedback signal, the drain of the ninth NMOS transistor is connected to the gate and drain of the sixth PMOS transistor, the gate of the seventh PMOS transistor and the gate of the tenth NMOS transistor, and the source of the ninth NMOS transistor is connected to the tenth NMOS transistor. The source of the NMOS tube is grounded;

The source of the seventh PMOS transistor is connected to the source of the sixth PMOS transistor and the output signal of the low-dropout linear regulator, and the drain of the seventh PMOS transistor is connected to the drain of the tenth NMOS transistor and the input end of the first inverter;

The input end of the second inverter is connected to the output end of the first inverter, and the output end thereof serves as the output end of the output detection module.

Specifically, the error amplifier includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, wherein the eighth PMOS transistor is a high-voltage device;

The gate of the eighth PMOS transistor is connected to the gate of the first PMOS transistor in the bias module, its source is connected to the input voltage of the low-dropout linear regulator, and its drain is connected to the ninth PMOS transistor and the tenth PMOS transistor the source of the tube;

The gate of the ninth PMOS tube is used as the positive input terminal of the error amplifier, and its drain is connected to the gate and drain of the eleventh NMOS tube and the gate of the twelfth NMOS tube, and serves as the negative terminal of the error amplifier. to the output;

The gate of the tenth PMOS transistor is used as the negative input terminal of the error amplifier, and its drain is connected to the drain of the twelfth NMOS transistor and used as the positive output terminal of the error amplifier;

The sources of the eleventh NMOS transistor and the twelfth NMOS transistor are grounded.

Specifically, the voltage divider network includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a first capacitor, and the gate-drain of the thirteenth NMOS transistor is short-circuited and connected to all The output signal of the low-dropout linear regulator and one end of the first capacitor, the source of which is connected to the gate and drain of the fourteenth NMOS transistor; the gate-drain of the fifteenth NMOS transistor is short-circuited and connected to the fourteenth NMOS transistor. The source of the sixteenth NMOS transistor is connected to the gate and drain of the sixteenth NMOS transistor and the other end of the first capacitor and outputs the feedback signal; the source of the sixteenth NMOS transistor is grounded.

Specifically, the gate of the fourth PMOS transistor in the bias module is connected to the gate of the first PMOS transistor.

The beneficial effects of the present invention are as follows: the low-dropout linear regulator proposed by the present invention does not require pre-step-down, can work under high pressure, and has a wide input voltage range; at the same time, the zero point introduced by the feedforward path replaces the need for the ESR zero point and The bandwidth is expanded; an additional dynamic negative feedback loop is introduced to improve the transient response speed; the output detection module can be set to detect whether the output is normal in real time and improve the system stability.

Description of drawings

Figure 1 is a topology diagram of a traditional off-chip large-capacitance LDO circuit.

FIG. 2 is an equivalent structure diagram of a low dropout linear regulator with a wide input voltage range proposed by the present invention.

3 is a schematic diagram of a transistor-level circuit implementation of a low-dropout linear regulator with a wide input voltage range proposed by the present invention in an embodiment.

4 is a schematic diagram of an AC simulation curve of a low-dropout linear regulator with a wide input voltage range proposed by the present invention.

FIG. 5 is a schematic diagram of a transient response curve of a low-dropout linear regulator with a wide input voltage range proposed by the present invention.

Detailed ways

The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

A low-dropout linear regulator with a wide input voltage V _IN range proposed by the present invention includes an error amplifier, a power tube, a voltage divider network, a bias module, a buffer stage, a feedforward path and a dynamic sampling module, wherein the power The tube MP is a PMOS power tube MP, the source of which is connected to the input voltage V _IN of the low-dropout linear regulator, and the drain of which generates the output signal V _OUT of the low-dropout linear regulator. The voltage divider network is used to divide the output signal of the low-dropout linear regulator to obtain a feedback signal. As shown in Figure 3, an implementation structure of the voltage divider network is given, including the thirteenth NMOS transistor M18, the tenth The gate and drain of the four NMOS transistors M19, the fifteenth NMOS transistor M20, the sixteenth NMOS transistor M21 and the first capacitor C10 are short-circuited and connected to the output signal V _OUT of the low dropout linear regulator and the first capacitor C10. One end of a capacitor C10 has its source connected to the gate and drain of the fourteenth NMOS transistor M19; the gate-drain of the fifteenth NMOS transistor M20 is short-circuited and connected to the source of the fourteenth NMOS transistor M19, and its source is connected to The gate and drain of the sixteenth NMOS transistor M21 and the other end of the first capacitor C10 are connected to the positive input terminal of the error amplifier to output a feedback signal; the source of the sixteenth NMOS transistor M21 is grounded. In this embodiment, the voltage divider network is formed by using four completely equal NMOS transistors in series in the form of gate-drain short-circuiting, which can greatly save the chip area and at the same time achieve high matching of the equivalent four resistors, and accurately divide the In addition, the addition of the first capacitor C10 can improve the transient response speed. With the clamping effect formed by the error amplifier and negative feedback, when the gain of the error amplifier is large enough, the relationship between the output signal V _OUT of the low dropout linear regulator and the input reference voltage V _ref is:

_Vout = _4Vref

That is, the output signal V _OUT has a linear relationship with the input reference voltage V _ref , which is about 4 times the relationship. Of course, this ratio can be adjusted according to the actual composition of the voltage divider network. If the voltage divider network is composed of other numbers of MOS transistors, for example, when the thirteenth NMOS transistor M18 is removed, the output signal V _OUT and the input reference voltage V _ref become about 3 times the relationship.

The error amplifier is used to obtain the difference between the feedback voltage V _FB and the reference voltage V _ref divided by the LDO output, and after pre-amplification, it is transmitted to the buffer stage and the feedforward path of the subsequent stage. In this embodiment, the error amplifier adopts a classic five-tube differential pair structure, and other error amplifiers with dual-output structures can also be used. As shown in FIG. 3, the error amplifier in this embodiment includes an eighth PMOS tube M2 and a ninth PMOS tube M5, the tenth PMOS transistor M6, the eleventh NMOS transistor M7 and the twelfth NMOS transistor M8; the gate of the eighth PMOS transistor M2 is connected to the bias, and its source is connected to the input voltage V _IN of the low-dropout linear regulator, Its drain is connected to the sources of the ninth PMOS transistor M5 and the tenth PMOS transistor M6; the gate of the ninth PMOS transistor M5 is connected to the feedback signal V _FB as the positive input terminal of the error amplifier, and its drain is connected to the eleventh NMOS transistor The gate and drain of M7 and the gate of the twelfth NMOS transistor M8 are used as the negative output terminal of the error amplifier; the gate of the tenth PMOS transistor M6 is used as the negative input terminal of the error amplifier to connect to the reference voltage V _ref , which The drain is connected to the drain of the twelfth NMOS transistor M8 and serves as a forward output terminal of the error amplifier; the sources of the eleventh NMOS transistor M7 and the twelfth NMOS transistor M8 are grounded.

The bias module is used to provide bias for the error amplifier, the buffer stage, the feedforward path and the dynamic sampling module, as shown in Figure 3, including the first PMOS transistor M1, the second PMOS transistor M3, the third PMOS transistor M4, the Four PMOS transistors M26 and the first NMOS transistor M9, the gate-drain of the first PMOS transistor M1 is short-circuited and connected to the gates of the second PMOS transistor M3 and the third PMOS transistor M4 and the first external bias signal L1, the source of which is connected The sources of the second PMOS transistor M3, the third PMOS transistor M4 and the fourth PMOS transistor M26 are connected to the input voltage V _IN of the low dropout linear regulator; the gate-drain of the first NMOS transistor M9 is short-circuited and connected to the second PMOS transistor The drain of M3 is connected to the negative output terminal of the error amplifier; the gate of the fourth PMOS transistor M26 is connected to the second external bias signal L2. As shown in FIG. 3 , the bias current of the LDO overall circuit is introduced from the first external bias signal L1, and is mirrored to the first PMOS transistor M1, the eighth PMOS transistor M2, the second PMOS transistor M3, and the third PMOS transistor M4. The circuit provides current bias and voltage bias. The circuit also sets a fixed bias voltage at the second external bias signal L2, so that the fourth PMOS transistor M26 introduces a fixed bias current, which acts as a shunt for the third NMOS transistor M17 of the auxiliary buffer stage to ensure the third The NMOS transistor M17 works in the saturation region to increase the overall gain of the operational amplifier. In some embodiments, the second external bias signal L2 can also be provided by the first external bias signal L1, that is, the gate of the fourth PMOS transistor M26 can be connected to the gate of the first PMOS transistor M1, and the fourth PMOS transistor M26 can be The width to length ratio of the PMOS transistor M26 is sufficient.

The error amplifier pre-amplifies the difference between the feedback voltage VFB and the reference voltage Vref and transmits it to the buffer stage and feedforward path of the subsequent stage. The MP gate terminal voltage is used to adjust the power tube current to provide the corresponding load current I _LOAD . As shown in FIG. 3, the buffer stage includes a second NMOS transistor M10 and a third NMOS transistor M17. The source of the second NMOS transistor M10 is connected to the forward output terminal of the error amplifier, and the gate of the second NMOS transistor M10 is connected to the first NMOS in the bias module. The gate of the transistor M9 is connected to the gate of the third NMOS transistor M17 and the drain of the third PMOS transistor M4 in the bias module; the drain of the third NMOS transistor M17 is connected to the input voltage of the low dropout linear regulator V _IN , the source of which is connected to the gate of the power transistor MP and the drain of the fourth PMOS transistor M26 in the bias module. The feedforward path includes a fourth NMOS transistor M11 and a fifth NMOS transistor M12. The gate of the fourth NMOS transistor M11 is connected to the gate of the first NMOS transistor M9, its drain is connected to the gate of the power transistor MP, and its source is connected to the first NMOS transistor M9. The drains of the five NMOS transistors M12; the gate of the fourth NMOS transistor M12 is connected to the negative output terminal of the error amplifier, and the source thereof is grounded.

The feedforward fast path and the buffer stage form the fast and slow paths to form the zero point instead of the ESR zero point, which simplifies the LDO system stability design. As shown in FIG. 2 , _GM is the transconductance of the ninth PMOS transistor M5 and the tenth PMOS transistor M6 in the input pair of transistors in the error amplifier, and the transconductances of the twelfth NMOS transistor M8 and the second NMOS transistor M10 are combined together to be equivalent is gm1, the transconductance of the fifth NMOS transistor M12 is gm2, and X1 represents a buffer.

The loop low frequency gain can be calculated as:

A _loop =[g _m5 g _m10 (r _o6 ||r _o8 )(r _o4 ||r _o10 )+K ₁ K ₂ ]g _mp R _out

Wherein K1=gm5/gm7, K2=gm12/ _gm17 , _gm5 , gm7, gm10, gm12, _gm17 , gmp represent the ninth PMOS tube M5, the eleventh NMOS tube M7, the second NMOS tube M10, the fifth The transconductances of the NMOS transistor M12, the third NMOS transistor M17, and the power transistor MP, r _o6 , r _o8 , r _o4 , and r _o10 are the tenth PMOS transistor M6 , the twelfth NMOS transistor M8 , the third PMOS transistor M4 , and the third PMOS transistor M4 , respectively. The small-signal equivalent impedance of the two NMOS transistors M10.

For the stability of the LDO system proposed by the present invention, two poles and one zero need to be considered, namely: the main pole P _OUT at the output end, the secondary pole _PG at the gate end of the power transistor, and the zero Z _O introduced by the feedforward path.

Among them, R _out and C _load are the equivalent impedance and capacitance of the output terminal, g _m17 and g _m11 are the transconductances of the third NMOS transistor M17 and the fourth NMOS transistor M11 respectively, and C _P and C ₁₂ are the power transistors MP and the third NMOS transistors M11 respectively. The equivalent capacitance of the gate terminal of the five NMOS transistor M12, at light load, because the main pole P _OUT is at a very low frequency, only the main pole system is stable within the gain bandwidth product GBW. As the load increases to the heavy load, the GBW is pushed to the high frequency, and the secondary pole _PG enters the GBW. Through reasonable parameter settings, the zero point Z _O can be set within the gain bandwidth product GBW to compensate the phase margin and ensure the system stability. .

In this embodiment, the power transistor MP, the eighth PMOS transistor M2, the first PMOS transistor M1, the second PMOS transistor M3, the third PMOS transistor M4, the fourth PMOS transistor M26, the first NMOS transistor M9, and the second NMOS transistor M10 , the fourth NMOS transistor M11, the eighth NMOS transistor M15 and the fifth PMOS transistor M16 are all high-voltage LDMOSs. When the input voltage V _IN is a high voltage (such as the highest 42V in this embodiment), the LDO proposed by the present invention can The high voltage withstand of each branch from the input voltage V _IN to the ground level GND acts between the drain and source of the LDMOS. In addition, in the present invention, the first Zener diode Z1 is directly connected between the gate terminal of the third NMOS transistor M17 and the input voltage V _IN , and the second Zener diode is directly connected between the gate terminal of the power transistor MP and the input voltage V _IN The diode Z2 ensures that the gate-source voltage VGS of the power transistor MP does not exceed 5V when powered on, thereby protecting the power transistor MP, and ensuring that the gate terminal potential of the third NMOS transistor M17 will not be pulled to a too low potential and shut down The third NMOS transistor M17 ensures the fast transient response speed of the entire loop.

As shown in FIG. 3 , the dynamic sampling module includes a sixth NMOS transistor M13, a seventh NMOS transistor M14, an eighth NMOS transistor M15 and a fifth PMOS transistor M16. The drain of the sixth NMOS transistor M13 is connected to the drain of the fifth NMOS transistor M12. pole, its gate is connected to the gate and drain of the seventh NMOS transistor M14 and the drain of the eighth NMOS transistor M15, and its source is connected to the source of the seventh NMOS transistor M14 and grounded; the gate of the eighth NMOS transistor M15 The drain of the power transistor MP is connected, and its source is connected to the drain of the fifth PMOS transistor M16; the gate of the fifth PMOS transistor M16 is connected to the gate of the power transistor MP, and its source is connected to the input voltage of the low-dropout linear regulator V _IN . When the load jumps rapidly, the gate-source voltage VGS of the eighth NMOS transistor M15 will be quickly adjusted to adjust the current flowing through the seventh NMOS transistor M14 and the sixth NMOS transistor M13, thereby changing the gate terminal voltage of the power transistor MP, which is a A fast and short negative feedback loop achieves performance that accelerates the LDO's transient response.

In some embodiments, an output detection module is also set in the low dropout linear regulator proposed by the present invention. As shown in FIG. 3 , the output detection module includes a first inverter INV1, a second inverter INV2, and a sixth PMOS The transistor M22, the seventh PMOS transistor M23, the ninth NMOS transistor M24 and the tenth NMOS transistor M25, the gate of the ninth NMOS transistor M24 is connected to the feedback signal V _FB , and its drain is connected to the gate and drain of the sixth PMOS transistor M22 , the gate of the seventh PMOS transistor M23 and the gate of the tenth NMOS transistor M25, the source of which is connected to the source of the tenth NMOS transistor M25 and grounded; the source of the seventh PMOS transistor M23 is connected to the source of the sixth PMOS transistor M22 The output signal V _OUT of the polar and low dropout linear regulator, its drain is connected to the drain of the tenth NMOS transistor M25 and the input end of the first inverter INV1; the input end of the second inverter INV2 is connected to the first inverter The output end of the phase device INV1 is used as the output end of the output detection module.

The working principle of the output detection module is: when the output signal V _OUT is normal, the feedback voltage V _FB is enough to turn on the ninth NMOS transistor M24 to make it work normally, and the gate terminal of the tenth NMOS transistor M25 will be pulled down to close, and the output detection module outputs The output of the signal L _OUT is high, indicating that the LDO output voltage is normal; similarly, when the LDO output voltage is insufficient, the feedback voltage V _FB is not enough to turn on the ninth NMOS transistor M24 to work normally, and the gate terminal of the tenth NMOS transistor M25 will be pulled high to turn on , L _OUT output is low, indicating that the LDO output voltage is abnormal.

Figure 4 shows the open-loop gain and its phase margin distribution under light load of 10uA and heavy load of 100mA. The loop gain is 39.9dB and 74.1dB, respectively, and the phase margin is 90° and 53°. It can be seen that the LDO system proposed by the present invention has good performance under different active loads and within a certain frequency range. During the process from light load to heavy load, the main pole moves to high frequency, and the zero point can be well compensated for the phase margin by setting the appropriate parameters. .

Figure 5 shows the transient response curve of the LDO proposed by the present invention, and the load jumps between 500uA and 100mA within 0.1us. It can be seen that the undershoot voltage of the output signal V _OUT is 24mV, and there is almost no overshoot voltage due to the large off-chip capacitor.

To sum up, the present invention proposes a low-dropout linear voltage regulator, the circuit has a wide voltage input range, can work directly under high voltage without pre-stepping down, and can be applied to 5V-42V input voltage through simulation verification , external large capacitor 4.7uF, theoretically it can work beyond 42V. The difference voltage between the feedback voltage VFB and the reference voltage Vref is pre-amplified by the error amplifier and then transmitted to the buffer stage and feedforward path of the subsequent stage. The gate terminal voltage of the power tube MP is controlled by confluence to charge and discharge, so as to adjust the current of the power tube to provide the corresponding load current I _LOAD . The zero point introduced by the feedforward path replaces the need for the ESR zero point and expands the bandwidth. A dynamic negative feedback loop is introduced to improve the transient response speed, and an output detection module is also set to detect whether the output is normal in real time.

Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (5)

1. A low dropout regulator with wide input voltage range comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feedforward path and a dynamic sampling module,

the power tube is a PMOS power tube, the source electrode of the power tube is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the power tube generates the output signal of the low-dropout linear voltage regulator;

the voltage division network is used for dividing the output signal of the low dropout linear regulator to obtain a feedback signal;

the positive input end of the error amplifier is connected with the feedback signal, and the negative input end of the error amplifier is connected with the reference voltage;

the low dropout linear regulator is characterized in that the bias module is used for providing bias for the error amplifier, the buffer stage, the feedforward path and the dynamic sampling module and comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the grid-drain short circuit of the first PMOS tube is connected with the grids of the second PMOS tube and the third PMOS tube and a first external bias signal, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube and is connected with the input voltage of the low dropout linear regulator; the grid drain of the first NMOS tube is in short circuit connection with the drain of the second PMOS tube, and the source of the first NMOS tube is connected with the negative output end of the error amplifier; the grid electrode of the fourth PMOS tube is connected with a second external bias signal;

the buffer stage comprises a second NMOS tube and a third NMOS tube, wherein the source electrode of the second NMOS tube is connected with the positive output end of the error amplifier, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube and the drain electrode of the third PMOS tube; the drain electrode of the third NMOS tube is connected with the input voltage of the low-dropout linear regulator, and the source electrode of the third NMOS tube is connected with the grid electrode of the power tube and the drain electrode of the fourth PMOS tube;

the feed-forward path comprises a fourth NMOS transistor and a fifth NMOS transistor, the grid electrode of the fourth NMOS transistor is connected with the grid electrode of the first NMOS transistor, the drain electrode of the fourth NMOS transistor is connected with the grid electrode of the power transistor, and the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor; the grid electrode of the fourth NMOS tube is connected with the negative output end of the error amplifier, and the source electrode of the fourth NMOS tube is grounded;

the dynamic sampling module comprises a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a fifth PMOS tube, wherein the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the grid electrode and the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube and grounded; the grid electrode of the eighth NMOS tube is connected with the drain electrode of the power tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the power tube, and the source electrode of the fifth PMOS tube is connected with the input voltage of the low dropout linear regulator;

the low dropout linear regulator further comprises a first Zener diode and a second Zener diode, wherein the cathode of the first Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the first Zener diode is connected with the grid electrode of a third NMOS tube; the cathode of the second Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the second Zener diode is connected with the grid electrode of the power tube;

the power tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the fourth NMOS tube, the eighth NMOS tube and the fifth PMOS tube are high-voltage resistant devices.

2. The low dropout regulator according to claim 1, further comprising an output detection module comprising a first inverter, a second inverter, a sixth PMOS transistor, a seventh PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor,

the grid electrode of the ninth NMOS tube is connected with the feedback signal, the drain electrode of the ninth NMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube and the grid electrode of the tenth NMOS tube, and the source electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube and is grounded;

the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube and the output signal of the low dropout linear regulator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the tenth NMOS tube and the input end of the first phase inverter;

the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is used as the output end of the output detection module.

3. The low dropout regulator according to claim 1 or 2, wherein the error amplifier comprises an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor, wherein the eighth PMOS transistor is a high voltage tolerant device;

the grid electrode of the eighth PMOS tube is connected with the grid electrode of the first PMOS tube in the bias module, the source electrode of the eighth PMOS tube is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the eighth PMOS tube is connected with the source electrodes of the ninth PMOS tube and the tenth PMOS tube;

a grid electrode of the ninth PMOS tube is used as a positive input end of the error amplifier, and a drain electrode of the ninth PMOS tube is connected with a grid electrode and a drain electrode of the eleventh NMOS tube and a grid electrode of the twelfth NMOS tube and is used as a negative output end of the error amplifier;

a grid electrode of the tenth PMOS tube is used as a negative input end of the error amplifier, and a drain electrode of the tenth PMOS tube is connected with a drain electrode of the twelfth NMOS tube and is used as a positive output end of the error amplifier;

the source electrodes of the eleventh NMOS tube and the twelfth NMOS tube are grounded.

4. The low dropout regulator according to claim 1 or 2, wherein the voltage divider network comprises a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor and a first capacitor, the gate-drain of the thirteenth NMOS transistor is shorted and connected to the output signal of the low dropout regulator and one end of the first capacitor, and the source of the thirteenth NMOS transistor is connected to the gate and the drain of the fourteenth NMOS transistor; the grid drain of the fifteenth NMOS tube is in short circuit connection with the source of the fourteenth NMOS tube, and the source of the fifteenth NMOS tube is connected with the grid and the drain of the sixteenth NMOS tube and the other end of the first capacitor and outputs the feedback signal; and the source electrode of the sixteenth NMOS tube is grounded.

5. The low dropout regulator of claim 1 wherein the gate of the fourth PMOS transistor of the bias module is connected to the gate of the first PMOS transistor.

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