CN111414035A - Low dropout regulator with wide input voltage range - Google Patents
Low dropout regulator with wide input voltage range Download PDFInfo
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- CN111414035A CN111414035A CN202010427873.6A CN202010427873A CN111414035A CN 111414035 A CN111414035 A CN 111414035A CN 202010427873 A CN202010427873 A CN 202010427873A CN 111414035 A CN111414035 A CN 111414035A
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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Abstract
A low dropout linear regulator with a wide input voltage range comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feedforward path, a dynamic sampling module and an output detection module, wherein the source electrode of the power tube is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the power tube generates an output signal of the low dropout linear regulator; the voltage division network divides the output signal of the low dropout linear regulator to obtain a feedback signal; the bias module is used for providing bias; the error amplifier pre-amplifies the difference voltage of the feedback signal and the reference voltage and then transmits the difference voltage to a buffer stage and a feedforward path at the later stage, and the two paths with different speeds of the buffer stage and the feedforward path are converged at the grid end of the power tube to control the grid end voltage of the power tube in a charging and discharging way; the dynamic sampling module can improve the transient response speed of the system; the output detection module is used for detecting whether the output is normal in real time.
Description
Technical Field
The invention belongs to the technical field of power management, and relates to a low-voltage linear voltage regulator which can be used for supplying power to a circuit inside a chip.
Background
The low Dropout Regulator (L ow drop Regulator, L DO) is an important circuit in a power management chip, has the advantages of low cost, low noise, low power consumption, simple circuit structure, small occupied chip area and the like, and is widely applied to the fields of consumer electronics, medical electronics, aerospace and the like.
The voltage input outside the chip is very noisy, so a stable and low-noise power supply is needed inside the chip to supply power to the internal circuits, L DO is a good choice to supply power to the internal circuits, L DO controls the power tube by amplifying the error signal fed back from the output to provide the output current to drive the load, as shown in FIG. 1, the conventional large off-chip capacitor L DO comprises an Error Amplifier (EA), a power tube, a resistor feedback network and a load capacitor.
The conventional L DO for powering the internal circuit of the chip requires the input voltage V firstINL DO is powered after pre-reduction in system stability, the conventional L DO employs an Equivalent Series Resistance (ESR) of an output capacitor to compensate for frequency, a dominant pole (Po) determined by the output capacitor and output impedance, and a secondary pole (P) determined by the parasitic capacitance of the power tube and the output impedance of the error amplifierG) Usually designed within the bandwidth of the loop, the presence of ESR will produce a zero (Z)ESR) Because the main pole Po drifts by a large amount, ESR changes with frequency and temperature, which is difficult to estimate, and brings great difficulty to design for stability of the whole L DO, and the introduction of ESR is generally accompanied by large voltage spike in transient state, which deteriorates transient characteristics of L DO.
Disclosure of Invention
Aiming at the problems of pre-reduction of voltage and stability and transient characteristics caused by frequency compensation by adopting ESR (equivalent series resistance) in the traditional low-dropout linear regulator, the invention provides the low-dropout linear regulator which does not need pre-reduction of voltage, can directly work in a wider input voltage range and has simple compensation, and the input voltage can reach 5-42V; a feed-forward path is introduced to replace an ESR zero point in a traditional low dropout linear regulator, and meanwhile, the sampling load current realizes faster transient response, and a logic circuit is introduced to an output port to judge whether the output is correct.
The technical scheme of the invention is as follows:
a low dropout regulator with wide input voltage range comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feedforward path and a dynamic sampling module,
the power tube is a PMOS power tube, the source electrode of the power tube is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the power tube generates the output signal of the low-dropout linear voltage regulator;
the voltage division network is used for dividing the output signal of the low dropout linear regulator to obtain a feedback signal;
the positive input end of the error amplifier is connected with the feedback signal, and the negative input end of the error amplifier is connected with the reference voltage;
the bias module is used for providing bias for the error amplifier, the buffer stage, the feedforward path and the dynamic sampling module and comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the grid drain of the first PMOS tube is in short circuit connection with the grids of the second PMOS tube and the third PMOS tube and a first external bias signal, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube and is connected with the input voltage of the low-dropout linear voltage regulator; the grid drain of the first NMOS tube is in short circuit connection with the drain of the second PMOS tube, and the source of the first NMOS tube is connected with the negative output end of the error amplifier; the grid electrode of the fourth PMOS tube is connected with a second external bias signal;
the buffer stage comprises a second NMOS tube and a third NMOS tube, wherein the source electrode of the second NMOS tube is connected with the positive output end of the error amplifier, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube and the drain electrode of the third PMOS tube; the drain electrode of the third NMOS tube is connected with the input voltage of the low-dropout linear regulator, and the source electrode of the third NMOS tube is connected with the grid electrode of the power tube and the drain electrode of the fourth PMOS tube;
the feed-forward path comprises a fourth NMOS transistor and a fifth NMOS transistor, the grid electrode of the fourth NMOS transistor is connected with the grid electrode of the first NMOS transistor, the drain electrode of the fourth NMOS transistor is connected with the grid electrode of the power transistor, and the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor; the grid electrode of the fourth NMOS tube is connected with the negative output end of the error amplifier, and the source electrode of the fourth NMOS tube is grounded;
the dynamic sampling module comprises a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a fifth PMOS tube, wherein the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the grid electrode and the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube and grounded; the grid electrode of the eighth NMOS tube is connected with the drain electrode of the power tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the power tube, and the source electrode of the fifth PMOS tube is connected with the input voltage of the low dropout linear regulator;
the low dropout linear regulator further comprises a first Zener diode and a second Zener diode, wherein the cathode of the first Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the first Zener diode is connected with the grid electrode of a third NMOS tube; the cathode of the second Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the second Zener diode is connected with the grid electrode of the power tube;
the power tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the fourth NMOS tube, the eighth NMOS tube and the fifth PMOS tube are high-voltage resistant devices.
Specifically, the low dropout regulator further comprises an output detection module, wherein the output detection module comprises a first phase inverter, a second phase inverter, a sixth PMOS tube, a seventh PMOS tube, a ninth NMOS tube and a tenth NMOS tube,
the grid electrode of the ninth NMOS tube is connected with the feedback signal, the drain electrode of the ninth NMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube and the grid electrode of the tenth NMOS tube, and the source electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube and is grounded;
the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube and the output signal of the low dropout linear regulator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the tenth NMOS tube and the input end of the first phase inverter;
the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is used as the output end of the output detection module.
Specifically, the error amplifier comprises an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor, wherein the eighth PMOS transistor is a high voltage resistant device;
the grid electrode of the eighth PMOS tube is connected with the grid electrode of the first PMOS tube in the bias module, the source electrode of the eighth PMOS tube is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the eighth PMOS tube is connected with the source electrodes of the ninth PMOS tube and the tenth PMOS tube;
a grid electrode of the ninth PMOS tube is used as a positive input end of the error amplifier, and a drain electrode of the ninth PMOS tube is connected with a grid electrode and a drain electrode of the eleventh NMOS tube and a grid electrode of the twelfth NMOS tube and is used as a negative output end of the error amplifier;
a grid electrode of the tenth PMOS tube is used as a negative input end of the error amplifier, and a drain electrode of the tenth PMOS tube is connected with a drain electrode of the twelfth NMOS tube and is used as a positive output end of the error amplifier;
the source electrodes of the eleventh NMOS tube and the twelfth NMOS tube are grounded.
Specifically, the voltage division network comprises a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a first capacitor, wherein the gate drain of the thirteenth NMOS tube is in short circuit and is connected with the output signal of the low dropout linear regulator and one end of the first capacitor, and the source electrode of the thirteenth NMOS tube is connected with the gate and the drain electrode of the fourteenth NMOS tube; the grid drain of the fifteenth NMOS tube is in short circuit connection with the source of the fourteenth NMOS tube, and the source of the fifteenth NMOS tube is connected with the grid and the drain of the sixteenth NMOS tube and the other end of the first capacitor and outputs the feedback signal; and the source electrode of the sixteenth NMOS tube is grounded.
Specifically, the gate of the fourth PMOS transistor in the bias module is connected to the gate of the first PMOS transistor.
The invention has the beneficial effects that: the low dropout regulator provided by the invention does not need pre-reduction of voltage, can work under high voltage and has wide input voltage range; meanwhile, zero points introduced by the feed-forward path replace the requirement on ESR zero points and the bandwidth is expanded; a dynamic negative feedback loop is additionally introduced, so that the transient response speed is improved; whether output is normal can be detected in real time by setting the output detection module, and the stability of the system is improved.
Drawings
Fig. 1 is a topology diagram of a conventional off-chip large capacitor L DO circuit.
Fig. 2 is an equivalent architecture diagram of a low dropout regulator with a wide input voltage range according to the present invention.
Fig. 3 is a schematic diagram of a transistor-level circuit implementation of a low dropout regulator with a wide input voltage range according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an ac simulation curve of a low dropout regulator with a wide input voltage range according to the present invention.
Fig. 5 is a schematic diagram of a transient response curve of a low dropout linear regulator having a wide input voltage range according to the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following by combining the drawings and the specific embodiment.
The invention provides a wide input voltage VINThe low dropout linear regulator comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feed-forward path and a dynamic sampling module, wherein the power tube MP is a PMOS power tube MP, and the source electrode of the power tube MP is connected with the input voltage V of the low dropout linear regulatorINThe drain electrode of the low dropout linear regulator generates an output signal V of the low dropout linear regulatorOUT. The voltage dividing network is used for dividing the output signal of the low dropout linear regulator to obtain a feedback signal, and as shown in fig. 3, an implementation structure of the voltage dividing network is provided, which includes a thirteenth NMOS transistor M18, a fourteenth NMOS transistor M19, a fifteenth NMOS transistor M20, a sixteenth NMOS transistor M21 and a first capacitor C10, wherein the gate-drain of the thirteenth NMOS transistor M18 is short-circuited and connected with the output signal V of the low dropout linear regulatorOUTAnd one end of a first capacitor C10 with its source connectedThe gate and the drain of the fourteenth NMOS transistor M19; the grid drain of the fifteenth NMOS tube M20 is in short circuit connection with the source of the fourteenth NMOS tube M19, the source of the fifteenth NMOS tube M20 is connected with the grid and the drain of the sixteenth NMOS tube M21 and the other end of the first capacitor C10, and a feedback signal is output and connected with the positive input end of the error amplifier; the source of the sixteenth NMOS transistor M21 is grounded. In the embodiment, the voltage division network is formed by connecting 4 completely equal NMOS tubes in series in a grid-drain short circuit mode, so that the equivalent 4 resistors can be highly matched while the chip area is greatly saved, the voltage division effect is accurately achieved, and in addition, the transient response speed can be increased by adding the first capacitor C10. When the gain of the error amplifier is large enough, the output signal V of the low dropout linear regulator is matched with the clamping effect formed by the error amplifier and the negative feedbackOUTAnd an input reference voltage VrefThe relationship of (1) is:
Vout＝4Vref
i.e. the output signal VOUTAnd an input reference voltage VrefIn a linear relationship, approximately 4 times the relationship. Of course, the ratio can be adjusted according to the actual configuration of the voltage divider network, if the voltage divider network is configured with other number of MOS transistors, such as the output signal V when the thirteenth NMOS transistor M18 is removedOUTAnd an input reference voltage VrefIt becomes about 3 times the relationship.
The error amplifier is used for obtaining a feedback voltage V divided by the L DO output terminalFBAnd a reference voltage VrefAnd pre-amplifying the difference value, and transmitting the amplified difference value to a buffer stage and a feedforward path of a subsequent stage. In this embodiment, the error amplifier is of a classical five-transistor differential pair structure, or an error amplifier of another dual-output structure, as shown in fig. 3, the error amplifier in this embodiment includes an eighth PMOS transistor M2, a ninth PMOS transistor M5, a tenth PMOS transistor M6, an eleventh NMOS transistor M7, and a twelfth NMOS transistor M8; the gate of the eighth PMOS transistor M2 is connected with bias, and the source is connected with the input voltage V of the low dropout linear regulatorINThe drain electrode of the PMOS transistor is connected with the source electrodes of a ninth PMOS transistor M5 and a tenth PMOS transistor M6; the grid of the ninth PMOS pipe M5 is used as the positive input end of the error amplifier and is connected with the feedback signal VFBThe drain electrode thereof is connected with the eleventh NThe grid and the drain of the MOS transistor M7 and the grid of the twelfth NMOS transistor M8 are used as the negative output end of the error amplifier; the grid of the tenth PMOS tube M6 is used as the negative input end of the error amplifier and is connected with the reference voltage VrefThe drain electrode of the error amplifier is connected with the drain electrode of the twelfth NMOS tube M8 and serves as the positive output end of the error amplifier; the sources of the eleventh NMOS transistor M7 and the twelfth NMOS transistor M8 are grounded.
The bias module is used for providing bias for the error amplifier, the buffer stage, the feed-forward path and the dynamic sampling module, and as shown in fig. 3, includes a first PMOS transistor M1, a second PMOS transistor M3, a third PMOS transistor M4, a fourth PMOS transistor M26 and a first NMOS transistor M9, wherein the gate-drain of the first PMOS transistor M1 is shorted and connected to the gates of the second PMOS transistor M3 and the third PMOS transistor M4 and the first external bias signal L1, and the source thereof is connected to the sources of the second PMOS transistor M3, the third PMOS transistor M4 and the fourth PMOS transistor M26 and connected to the input voltage V of the low dropout linear regulatorINThe gate-drain of the first NMOS transistor M9 is shorted and connected with the drain of the second PMOS transistor M3, the source of the first NMOS transistor M9 is connected with the negative output end of the error amplifier, the gate of the fourth PMOS transistor M26 is connected with the second external bias signal L. As shown in FIG. 3, the bias current of the L DO whole circuit is introduced from the first external bias signal L1, and the current bias and the voltage bias are provided to the circuit through the first PMOS transistor M1, the eighth PMOS transistor M2, the second PMOS transistor M3 and the mirror image of the third PMOS transistor M4. the circuit also sets a fixed bias voltage at the second external bias signal L, so that the fixed bias current is introduced into the fourth PMOS transistor M26 and is used for shunting the third NMOS transistor M17 of the auxiliary buffer stage, and ensuring that the third NMOS transistor M17 works in the saturation region to realize the increase of the whole gain of the operational amplifier.
The error amplifier pre-amplifies the difference between the feedback voltage VFB and the reference voltage Vref and transmits the amplified difference to the buffer stage and the feedforward path of the subsequent stage, and the two paths with different speeds are converged at the gate end of the power tube MP to control the voltage of the gate end of the power tube MP by charging and discharging so as to regulate the current of the power tube and provide corresponding load current ILOAD. As shown in fig. 3, the buffer stage includes a second NMOS transistor M10 and a third NMOS transistor M17, the source of the second NMOS transistor M10 is connected to the forward output terminal of the error amplifier, the gate thereof is connected to the gate of the first NMOS transistor M9 in the bias block, and the drain thereof is connected to the gate of the third NMOS transistor M17 and the drain of the third PMOS transistor M4 in the bias block; the drain of the third NMOS transistor M17 is connected with the input voltage V of the low dropout linear regulatorINAnd the source of the transistor is connected with the gate of the power transistor MP and the drain of the fourth PMOS transistor M26 in the bias module. The feed-forward path comprises a fourth NMOS transistor M11 and a fifth NMOS transistor M12, the grid electrode of the fourth NMOS transistor M11 is connected with the grid electrode of the first NMOS transistor M9, the drain electrode of the fourth NMOS transistor M3526 is connected with the grid electrode of the power transistor MP, and the source electrode of the fourth NMOS transistor M3526 is connected with the drain electrode of the fifth NMOS transistor M12; the gate of the fourth NMOS transistor M12 is connected to the negative output terminal of the error amplifier, and the source thereof is grounded.
The feedforward fast path and the buffer stage form fast and slow paths to form zero points instead of ESR zero points, so that the stability design of L DO system is simplified, as shown in figure 2, GMFor the transconductance of the ninth PMOS transistor M5 and the tenth PMOS transistor M6 of the input pair transistor in the error amplifier, the transconductance of the twelfth NMOS transistor M8 and the second NMOS transistor M10 are together equivalent to gm1, the transconductance of the fifth NMOS transistor M12 is gm2, and X1 represents a buffer.
The loop low frequency gain may be calculated as:
Aloop＝[gm5gm10(ro6||ro8)(ro4||ro10)+K1K2]gmpRout
wherein K1 gm5/gm7, K2 gm12/gm17, gm5、gm7、gm10、gm12、gm17、gmpRespectively represent transconductance of a ninth PMOS transistor M5, an eleventh NMOS transistor M7, a second NMOS transistor M10, a fifth NMOS transistor M12, a third NMOS transistor M17 and a power transistor MP, ro6、ro8、ro4、ro10The equivalent impedance of the small signal of the tenth PMOS transistor M6, the twelfth NMOS transistor M8, the third PMOS transistor M4 and the second NMOS transistor M10.
For the L DO system stability provided by the invention, two poles and a zero point are considered, wherein the two poles are respectively a dominant pole P of an output endOUTSub-gate terminal of power tubePole PGZero point Z introduced by feed-forward pathO。
Wherein R isout、CloadIs the equivalent impedance and capacitance of the output terminal, gm17、gm11Transconductance C of the third NMOS transistor M17 and the fourth NMOS transistor M11P、C12The equivalent capacitances of the gate ends of the power tube MP and the fifth NMOS tube M12 are respectively, and the dominant pole P is caused during light loadOUTAt very low frequencies, only the dominant pole system is stable within the gain-bandwidth product GBW. The secondary pole P pushes high frequency as the load increases to heavy load GBWGEntering GBW, through reasonable parameter setting, zero point Z can be enabledOThe gain bandwidth is set within the GBW product to compensate the phase margin, and the stability of the system is ensured.
In this embodiment, the power transistor MP, the eighth PMOS transistor M2, the first PMOS transistor M1, the second PMOS transistor M3, the third PMOS transistor M4, the fourth PMOS transistor M26, the first NMOS transistor M9, the second NMOS transistor M10, the fourth NMOS transistor M11, the eighth NMOS transistor M15, and the fifth PMOS transistor M16 are all high voltage resistant L DMOS, when the input voltage V is inputINFor high voltage (e.g. up to 42V in this embodiment), the proposed L DO can be derived from the input voltage VINThe high voltage of each branch to the ground level GND is applied between the drain and the source of L DMOS, and the invention is applied to the input voltage V from the gate terminal of the third NMOS transistor M17INA first Zener diode Z1 is directly connected between the gate terminal of the power tube MP and the input voltage VINThe second Zener diode Z2 is directly connected between the power supply and the power supply, so that the gate-source voltage VGS of the power tube MP is ensured not to exceed 5V when the power supply is powered on, the power tube MP is protected, and the potential of the gate end of the third NMOS tube M17 is ensured not to beThe third NMOS transistor M17 is pulled to a low potential to be turned off, so that the fast transient response speed of the whole loop is ensured.
As shown in fig. 3, the dynamic sampling module includes a sixth NMOS transistor M13, a seventh NMOS transistor M14, an eighth NMOS transistor M15, and a fifth PMOS transistor M16, wherein a drain of the sixth NMOS transistor M13 is connected to a drain of the fifth NMOS transistor M12, a gate thereof is connected to a gate and a drain of the seventh NMOS transistor M14 and a drain of the eighth NMOS transistor M15, and a source thereof is connected to a source of the seventh NMOS transistor M14 and grounded; the gate of the eighth NMOS transistor M15 is connected to the drain of the power transistor MP, and the source thereof is connected to the drain of the fifth PMOS transistor M16; the grid electrode of the fifth PMOS pipe M16 is connected with the grid electrode of the power pipe MP, and the source electrode of the fifth PMOS pipe M16 is connected with the input voltage V of the low dropout linear regulatorINWhen the load jumps rapidly, the gate-source voltage VGS of the eighth NMOS transistor M15 is adjusted rapidly to regulate the current flowing through the seventh NMOS transistor M14 and the sixth NMOS transistor M13, so as to change the gate terminal voltage of the power transistor MP, which is a fast and short negative feedback loop to accelerate the L DO transient response.
In some embodiments, an output detection module is further disposed in the low dropout linear regulator according to the present invention, as shown in fig. 3, the output detection module includes a first inverter INV1, a second inverter INV2, a sixth PMOS transistor M22, a seventh PMOS transistor M23, a ninth NMOS transistor M24, and a tenth NMOS transistor M25, and a gate of the ninth NMOS transistor M24 is connected to the feedback signal VFBThe drain electrode of the PMOS transistor is connected with the grid electrode and the drain electrode of the sixth PMOS transistor M22, the grid electrode of the seventh PMOS transistor M23 and the grid electrode of the tenth NMOS transistor M25, and the source electrode of the PMOS transistor is connected with the source electrode of the tenth NMOS transistor M25 and is grounded; the source electrode of the seventh PMOS tube M23 is connected with the source electrode of the sixth PMOS tube M22 and the output signal V of the low dropout linear regulatorOUTA drain thereof is connected to the drain of the tenth NMOS transistor M25 and the input of the first inverter INV 1; the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, and the output end thereof is used as the output end of the output detection module.
The working principle of the output detection module is as follows: when outputting the signal VOUTAt normal time, the feedback voltage VFBWhen the ninth NMOS transistor M24 is turned on enough to operate normally, the gate of the tenth NMOS transistor M25 is pulled low and turned off, outputting the output signal L of the detection moduleOUTThe output is high, which means that L DO output voltage is normal, and similarly, when L DO output voltage is insufficient, the feedback voltage V isFBUnder the condition that the ninth NMOS transistor M24 is not opened enough to work normally, the gate terminal of the tenth NMOS transistor M25 is pulled high to be opened, LOUTThe output is low indicating L a DO output voltage anomaly.
As shown in fig. 4, the distribution diagram of the open loop gain and the phase margin thereof under light load of 10uA and heavy load of 100mA is shown, the loop gain is 39.9dB and 74.1dB respectively, and the phase margin is 90 ° and 53 ° respectively.
As shown in FIG. 5, which shows the L DO transient response curve proposed by the present invention, a load jump is made between 500uA and 100mA within 0.1usOUTThe undershoot voltage undershoot of (1) is at 24mV because of the fact that the off-chip large capacitor almost has no overshoot voltage overthot.
In summary, the present invention provides a low dropout regulator, which has a wide voltage input range, can directly operate at high voltage without pre-voltage reduction, and is verified by simulation to be suitable for input voltages of 5V to 42V, and can operate with an external large capacitor of 4.7uF, which theoretically exceeds 42V. The difference voltage of the feedback voltage VFB and the reference voltage Vref is pre-amplified by an error amplifier and then transmitted to a buffer stage and a feedforward path at the later stage, and the two paths with different speeds of the buffer stage and the feedforward path are converged at the gate end of the power tube MP to control the voltage at the gate end of the power tube MP by charging and discharging so as to adjust the current of the power tube and provide corresponding load current ILOADIn addition, a dynamic negative feedback loop is additionally introduced through dynamic sampling, so that the transient response speed is improved, and an output detection module is arranged to detect whether the output is normal in real time.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (5)
1. A low dropout regulator with wide input voltage range comprises an error amplifier, a power tube, a voltage division network, a bias module, a buffer stage, a feedforward path and a dynamic sampling module,
the power tube is a PMOS power tube, the source electrode of the power tube is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the power tube generates the output signal of the low-dropout linear voltage regulator;
the voltage division network is used for dividing the output signal of the low dropout linear regulator to obtain a feedback signal;
the positive input end of the error amplifier is connected with the feedback signal, and the negative input end of the error amplifier is connected with the reference voltage;
the low dropout linear regulator is characterized in that the bias module is used for providing bias for the error amplifier, the buffer stage, the feedforward path and the dynamic sampling module and comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the grid-drain short circuit of the first PMOS tube is connected with the grids of the second PMOS tube and the third PMOS tube and a first external bias signal, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube and is connected with the input voltage of the low dropout linear regulator; the grid drain of the first NMOS tube is in short circuit connection with the drain of the second PMOS tube, and the source of the first NMOS tube is connected with the negative output end of the error amplifier; the grid electrode of the fourth PMOS tube is connected with a second external bias signal;
the buffer stage comprises a second NMOS tube and a third NMOS tube, wherein the source electrode of the second NMOS tube is connected with the positive output end of the error amplifier, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube and the drain electrode of the third PMOS tube; the drain electrode of the third NMOS tube is connected with the input voltage of the low-dropout linear regulator, and the source electrode of the third NMOS tube is connected with the grid electrode of the power tube and the drain electrode of the fourth PMOS tube;
the feed-forward path comprises a fourth NMOS transistor and a fifth NMOS transistor, the grid electrode of the fourth NMOS transistor is connected with the grid electrode of the first NMOS transistor, the drain electrode of the fourth NMOS transistor is connected with the grid electrode of the power transistor, and the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor; the grid electrode of the fourth NMOS tube is connected with the negative output end of the error amplifier, and the source electrode of the fourth NMOS tube is grounded;
the dynamic sampling module comprises a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a fifth PMOS tube, wherein the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the grid electrode and the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube and grounded; the grid electrode of the eighth NMOS tube is connected with the drain electrode of the power tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the power tube, and the source electrode of the fifth PMOS tube is connected with the input voltage of the low dropout linear regulator;
the low dropout linear regulator further comprises a first Zener diode and a second Zener diode, wherein the cathode of the first Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the first Zener diode is connected with the grid electrode of a third NMOS tube; the cathode of the second Zener diode is connected with the input voltage of the low dropout linear regulator, and the anode of the second Zener diode is connected with the grid electrode of the power tube;
the power tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the fourth NMOS tube, the eighth NMOS tube and the fifth PMOS tube are high-voltage resistant devices.
2. The low dropout regulator according to claim 1, further comprising an output detection module comprising a first inverter, a second inverter, a sixth PMOS transistor, a seventh PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor,
the grid electrode of the ninth NMOS tube is connected with the feedback signal, the drain electrode of the ninth NMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube and the grid electrode of the tenth NMOS tube, and the source electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube and is grounded;
the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube and the output signal of the low dropout linear regulator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the tenth NMOS tube and the input end of the first phase inverter;
the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is used as the output end of the output detection module.
3. The low dropout regulator according to claim 1 or 2, wherein the error amplifier comprises an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor, wherein the eighth PMOS transistor is a high voltage tolerant device;
the grid electrode of the eighth PMOS tube is connected with the grid electrode of the first PMOS tube in the bias module, the source electrode of the eighth PMOS tube is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the eighth PMOS tube is connected with the source electrodes of the ninth PMOS tube and the tenth PMOS tube;
a grid electrode of the ninth PMOS tube is used as a positive input end of the error amplifier, and a drain electrode of the ninth PMOS tube is connected with a grid electrode and a drain electrode of the eleventh NMOS tube and a grid electrode of the twelfth NMOS tube and is used as a negative output end of the error amplifier;
a grid electrode of the tenth PMOS tube is used as a negative input end of the error amplifier, and a drain electrode of the tenth PMOS tube is connected with a drain electrode of the twelfth NMOS tube and is used as a positive output end of the error amplifier;
the source electrodes of the eleventh NMOS tube and the twelfth NMOS tube are grounded.
4. The low dropout regulator according to claim 1 or 2, wherein the voltage divider network comprises a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor and a first capacitor, the gate-drain of the thirteenth NMOS transistor is shorted and connected to the output signal of the low dropout regulator and one end of the first capacitor, and the source of the thirteenth NMOS transistor is connected to the gate and the drain of the fourteenth NMOS transistor; the grid drain of the fifteenth NMOS tube is in short circuit connection with the source of the fourteenth NMOS tube, and the source of the fifteenth NMOS tube is connected with the grid and the drain of the sixteenth NMOS tube and the other end of the first capacitor and outputs the feedback signal; and the source electrode of the sixteenth NMOS tube is grounded.
5. The low dropout regulator of claim 1 wherein the gate of the fourth PMOS transistor of the bias module is connected to the gate of the first PMOS transistor.
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| CN112162588A (en) * | 2020-10-14 | 2021-01-01 | 珠海海奇半导体有限公司 | High-stability low-dropout linear voltage regulator |
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