CN116505934B - Forward and reverse phase input stage circuit - Google Patents
Forward and reverse phase input stage circuit Download PDFInfo
- Publication number
- CN116505934B CN116505934B CN202310587468.4A CN202310587468A CN116505934B CN 116505934 B CN116505934 B CN 116505934B CN 202310587468 A CN202310587468 A CN 202310587468A CN 116505934 B CN116505934 B CN 116505934B
- Authority
- CN
- China
- Prior art keywords
- transistor
- port
- drain
- electrode
- phase input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a positive and negative phase input stage circuit, which comprises a positive phase input port, an inverted input port, a power supply port, a grounding port, a pull-up and pull-down module, a positive phase channel module, an inverted channel module and an output port, wherein the pull-up and pull-down module can pull up the non-input positive phase input port and pull down the non-input inverted input port, and the positive phase channel module comprises a fifth transistor and a ninth transistor respectively; a fourth transistor, an eleventh transistor; three inverters composed of a sixth transistor and a tenth transistor; the inverting path module comprises a second transistor and an eighth transistor; a third transistor, a twelfth transistor; and three inverters composed of a sixth transistor and a tenth transistor. The waveform of the output end is in phase with the normal phase input port and is connected with the reverse phase input port, and the waveform of the output end is reverse to the reverse phase input port. The invention can realize positive or reverse phase output on the same chip or the same channel of the chip.
Description
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to a positive and negative phase input stage circuit.
Background
In digital-to-analog circuits, it is often the case that the input is in phase or in phase with the output, for example, a TTL square wave signal is input, and the output may need to output a control signal in phase or in phase. In a conventional digital die core, input and output are usually used as a chip or a channel in the chip in the same phase, and input and output are used as a chip or a channel in the opposite phase, so that various problems exist in terms of chip cost, area and integration convenience.
Disclosure of Invention
The invention aims to provide a positive and negative phase input stage circuit which can realize positive or negative phase output on the same chip or the same channel of the chip.
One aspect of the invention provides a positive and negative phase input stage circuit, comprising a positive phase input port, a negative phase input port, a power supply port, a ground port, a pull-up and pull-down module, a positive phase channel module, a negative phase channel module and an output port,
the pull-up and pull-down module comprises a first transistor and a seventh transistor, wherein the first transistor is a PMOS (P-channel metal oxide semiconductor) transistor, the seventh transistor is an NMOS (N-channel metal oxide semiconductor) transistor, the grid electrode of the first transistor is connected with the grounding port, the drain electrode of the first transistor is connected with the normal phase input port, and the source electrode of the first transistor is connected with the power supply port; a grid electrode of the seventh transistor is connected with the power supply port, a drain electrode of the seventh transistor is connected with the inverting input port, and a source electrode of the seventh transistor is connected with the grounding port;
the positive-phase circuit module comprises a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein the fourth transistor, the fifth transistor and the sixth transistor are PMOS transistors, and the ninth transistor, the tenth transistor and the eleventh transistor are NMOS transistors;
the inverting path module comprises a second transistor, a third transistor, a sixth transistor, an eighth transistor, a tenth transistor and a twelfth transistor, wherein the second transistor and the third transistor are PMOS transistors, and the eighth transistor and the twelfth transistor are NMOS transistors;
the positive input port is connected with the gates of the fifth transistor, the ninth transistor, the fourth transistor and the eleventh transistor; the source electrode of the fifth transistor is connected with the drain electrode of the second transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the ninth transistor, the source electrode of the ninth transistor is connected with the grounding port, the source electrode of the fourth transistor is connected with the power supply port, the drain electrode of the fourth transistor is connected with the source electrode of the sixth transistor, the drain electrode of the eleventh transistor is connected with the output port, and the source electrode of the eleventh transistor is connected with the drain electrode of the twelfth transistor; the drain of the fifth transistor and the drain of the ninth transistor are connected with the gate of the sixth transistor and the gate of the tenth transistor, and the drain of the sixth transistor is connected with the drain of the tenth transistor and with the output port;
the inverting input port is connected with the gates of the second transistor, the eighth transistor, the third transistor and the twelfth transistor; the source electrode of the second transistor is connected with the power supply port, the drain electrode of the second transistor is connected with the source electrode of the fifth transistor, the drain electrode of the eighth transistor is connected with the grid electrode of the sixth transistor and the grid electrode of the tenth transistor, and the source electrode of the eighth transistor is connected with the grounding port; the source of the third transistor is connected to the power supply port, the drain is connected to the source of the sixth transistor, the source of the twelfth transistor is connected to the ground port, and the drain is connected to the source of the eleventh transistor.
Preferably, in the forward circuit module, the fifth transistor and the ninth transistor, the fourth transistor and the eleventh transistor, and the sixth transistor and the tenth transistor constitute three inverters, respectively.
Preferably, in the inverting path module, the second transistor and the eighth transistor, the third transistor and the twelfth transistor, and the sixth transistor and the tenth transistor constitute three inverters, respectively.
According to the forward and reverse phase input stage circuit, forward or reverse phase output can be realized on the same chip or the same channel of the chip.
Drawings
For a clearer description of the technical solutions of the present invention, the following description will be given with reference to the attached drawings used in the description of the embodiments of the present invention, it being obvious that the attached drawings in the following description are only some embodiments of the present invention, and that other attached drawings can be obtained by those skilled in the art without the need of inventive effort:
fig. 1 is a circuit diagram of a forward and reverse phase input stage circuit according to one embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a normal-reverse phase input stage circuit, and fig. 1 is a circuit diagram of the normal-reverse phase input stage circuit according to one embodiment of the invention. As shown IN fig. 1, the normal-reverse input stage circuit according to the embodiment of the present invention includes a normal-phase input port IN, an inverted-phase input port in_anti, a power supply port VDD, a ground port VSS, a pull-up and pull-down module, a normal-phase channel module, an inverted-phase channel module, and an output port OUT, where the two input ports one forward and one reverse can be directly used as two input PADs (PADs) of a circuit chip, the output port OUT can be connected to a next stage circuit, the power supply port VDD is connected to a power supply, and the ground port VSS is grounded.
The pull-up and pull-down module includes a first transistor M1 and a seventh transistor M7, wherein the first transistor M1 is a PMOS transistor (P-channel metal oxide semiconductor transistor), a gate thereof is connected to the ground port VSS, a drain thereof is connected to the normal phase input port IN, and a source thereof is connected to the power supply port VDD, so that the normal phase input port IN without input can be pulled up. The seventh transistor M7 is an NMOS (N-channel metal oxide semiconductor transistor) having a gate connected to the power supply port VDD, a drain connected to the inverting input port in_anti, and a source connected to the ground port VSS, and is capable of pulling down the inverting input port in_anti without input.
The positive-phase circuit module comprises a fifth transistor M5 and a ninth transistor M9; a fourth transistor M4, an eleventh transistor M11; the third inverter is composed of a sixth transistor M6 and a tenth transistor M10, wherein the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are PMOS transistors, and the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are NMOS transistors.
The inverting path module comprises a second transistor M2 and an eighth transistor M8; a third transistor M3, a twelfth transistor M12; three inverters including a sixth transistor M6 and a tenth transistor M10. The second transistor M2 and the third transistor M3 are PMOS transistors, and the eighth transistor M8 and the twelfth transistor M12 are NMOS transistors.
IN the forward circuit module, the non-inverting input port IN is connected to the gates of the fifth transistor M5, the ninth transistor M9, the fourth transistor M4, and the eleventh transistor M11. The source of the fifth transistor M5 is connected to the drain of the second transistor M2, and the drain of the fifth transistor M5 is connected to the drain of the ninth transistor M9, forming an inverter. And the source of the ninth transistor M9 is connected to the ground port VSS.
The fourth transistor M4 has a source connected to the power supply port VDD, a drain connected to the source of the sixth transistor M6, a drain connected to the output port OUT, and a source connected to the drain of the twelfth transistor M12.
The drain of the fifth transistor M5 and the drain output of the ninth transistor M9 are connected to the gates of the sixth transistor M6 and the tenth transistor M10, and the drain of the sixth transistor M6 is connected to the drain of the tenth transistor M10 to form an inverter, and the output thereof is the output of the output port OUT.
IN the inverting path module, an inverting input port in_anti and the second transistor M2, the eighth transistor M8; the gates of the third transistor M3 and the twelfth transistor M12 are connected. The source of the second transistor M2 is connected to the power supply port VDD, the drain is connected to the source of the fifth transistor M5, the drain of the eighth transistor M8 is connected to the gates of the sixth transistor M6 and the tenth transistor M10, and the source is connected to the ground port VSS. The source of the third transistor M3 is connected to the power supply port VDD, the drain is connected to the source of the sixth transistor M6, the source of the twelfth transistor M12 is connected to the ground port VSS, and the drain is connected to the source of the eleventh transistor M11. The drain of the sixth transistor M6 is connected to the drain of the tenth transistor M10 to form an inverter, and the output thereof is the output port OUT.
When the normal phase input is used, the normal phase input port IN is connected to suspend the reverse phase input port in_anti, and the seventh transistor M7 is a pull-down transistor, so that the reverse phase input port in_anti is connected to the ground port VSS. At this time, the eighth transistor M8 and the twelfth transistor M12 are both turned off, the second transistor M2 is turned on, the first inverter formed by the fifth transistor M5 and the ninth transistor M9 operates normally, the third transistor M3 is turned on, and the inverter formed by the sixth transistor M6 and the tenth transistor M10 operates normally, so that the output signal is IN phase with the signal of the normal phase input port IN.
When the inverting input is used, the inverting input port in_anti is connected, and the non-inverting input port IN is suspended, and the first transistor M1 is a pull-up tube, so that the non-inverting input port IN is connected to the power supply port VDD. At this time, the fourth transistor M4 and the fifth transistor M5 are both turned off, the ninth transistor M9 and the eleventh transistor M11 are turned on, and the third transistor M3 and the twelfth transistor M12 form a first-stage inverter, so that the output signal is inverted with respect to the signal of the inverting input port in_anti.
According to the forward and reverse phase input stage circuit, the forward and reverse phase input stage circuit is connected with the forward phase input port IN, the waveform of the output end is IN phase with the forward phase input port IN, the reverse phase input port IN_anti of the input end is connected, and the waveform of the output end is IN reverse phase with the reverse phase input port IN_anti. Therefore, the forward/reverse phase input stage circuit of the embodiment of the invention can be used as a general-purpose front stage input module, and the in-phase or reverse-phase output can be selected at the input end by adding the circuit module to a certain channel input end of the digital-analog chip.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.
Claims (3)
1. A positive and negative phase input stage circuit is characterized by comprising a positive phase input port, a negative phase input port, a power supply port, a grounding port, a pull-up and pull-down module, a positive phase channel module, a negative phase channel module and an output port,
the pull-up and pull-down module comprises a first transistor and a seventh transistor, wherein the first transistor is a PMOS (P-channel metal oxide semiconductor) transistor, the seventh transistor is an NMOS (N-channel metal oxide semiconductor) transistor, the grid electrode of the first transistor is connected with the grounding port, the drain electrode of the first transistor is connected with the normal phase input port, and the source electrode of the first transistor is connected with the power supply port; a grid electrode of the seventh transistor is connected with the power supply port, a drain electrode of the seventh transistor is connected with the inverting input port, and a source electrode of the seventh transistor is connected with the grounding port;
the positive-phase circuit module comprises a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein the fourth transistor, the fifth transistor and the sixth transistor are PMOS transistors, and the ninth transistor, the tenth transistor and the eleventh transistor are NMOS transistors;
the inverting path module comprises a second transistor, a third transistor, a sixth transistor, an eighth transistor, a tenth transistor and a twelfth transistor, wherein the second transistor and the third transistor are PMOS transistors, and the eighth transistor and the twelfth transistor are NMOS transistors;
the positive input port is connected with the gates of the fifth transistor, the ninth transistor, the fourth transistor and the eleventh transistor; the source electrode of the fifth transistor is connected with the drain electrode of the second transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the ninth transistor, the source electrode of the ninth transistor is connected with the grounding port, the source electrode of the fourth transistor is connected with the power supply port, the drain electrode of the fourth transistor is connected with the source electrode of the sixth transistor, the drain electrode of the eleventh transistor is connected with the output port, and the source electrode of the eleventh transistor is connected with the drain electrode of the twelfth transistor; the drain of the fifth transistor and the drain of the ninth transistor are connected with the gate of the sixth transistor and the gate of the tenth transistor, and the drain of the sixth transistor is connected with the drain of the tenth transistor and with the output port;
the inverting input port is connected with the gates of the second transistor, the eighth transistor, the third transistor and the twelfth transistor; the source electrode of the second transistor is connected with the power supply port, the drain electrode of the second transistor is connected with the source electrode of the fifth transistor, the drain electrode of the eighth transistor is connected with the grid electrode of the sixth transistor and the grid electrode of the tenth transistor, and the source electrode of the eighth transistor is connected with the grounding port; the source of the third transistor is connected to the power supply port, the drain is connected to the source of the sixth transistor, the source of the twelfth transistor is connected to the ground port, and the drain is connected to the source of the eleventh transistor.
2. The forward and reverse phase input stage circuit according to claim 1, wherein in the forward pass module, the fifth transistor and the ninth transistor, the fourth transistor and the eleventh transistor, and the sixth transistor and the tenth transistor constitute three inverters, respectively.
3. The forward and reverse phase input stage circuit according to claim 1 or 2, wherein in the inverting path module, the second transistor and the eighth transistor, the third transistor and the twelfth transistor, and the sixth transistor and the tenth transistor constitute three inverters, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310587468.4A CN116505934B (en) | 2023-05-24 | 2023-05-24 | Forward and reverse phase input stage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310587468.4A CN116505934B (en) | 2023-05-24 | 2023-05-24 | Forward and reverse phase input stage circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116505934A CN116505934A (en) | 2023-07-28 |
| CN116505934B true CN116505934B (en) | 2024-02-02 |
Family
ID=87316544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310587468.4A Active CN116505934B (en) | 2023-05-24 | 2023-05-24 | Forward and reverse phase input stage circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116505934B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191636B1 (en) * | 1999-09-22 | 2001-02-20 | Cypress Semiconductor Corp. | Input buffer/level shifter |
| CN103312309A (en) * | 2013-05-14 | 2013-09-18 | 无锡华润矽科微电子有限公司 | Analog switch control circuit structure |
| CN105446923A (en) * | 2014-09-23 | 2016-03-30 | 德克萨斯仪器股份有限公司 | Differential driver with pull up and pull down boosters |
| CN107134983A (en) * | 2017-05-18 | 2017-09-05 | 华南理工大学 | A kind of operational amplifier |
| CN113691249A (en) * | 2020-05-18 | 2021-11-23 | 瑞昱半导体股份有限公司 | Duty cycle correction circuit and method |
| WO2022110697A1 (en) * | 2020-11-25 | 2022-06-02 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN115913214A (en) * | 2023-01-09 | 2023-04-04 | 上海芯楷集成电路有限责任公司 | Positive and negative high voltage level switching circuit |
-
2023
- 2023-05-24 CN CN202310587468.4A patent/CN116505934B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191636B1 (en) * | 1999-09-22 | 2001-02-20 | Cypress Semiconductor Corp. | Input buffer/level shifter |
| CN103312309A (en) * | 2013-05-14 | 2013-09-18 | 无锡华润矽科微电子有限公司 | Analog switch control circuit structure |
| CN105446923A (en) * | 2014-09-23 | 2016-03-30 | 德克萨斯仪器股份有限公司 | Differential driver with pull up and pull down boosters |
| CN107134983A (en) * | 2017-05-18 | 2017-09-05 | 华南理工大学 | A kind of operational amplifier |
| CN113691249A (en) * | 2020-05-18 | 2021-11-23 | 瑞昱半导体股份有限公司 | Duty cycle correction circuit and method |
| WO2022110697A1 (en) * | 2020-11-25 | 2022-06-02 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN115913214A (en) * | 2023-01-09 | 2023-04-04 | 上海芯楷集成电路有限责任公司 | Positive and negative high voltage level switching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116505934A (en) | 2023-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7167027B2 (en) | Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage | |
| US20040178828A1 (en) | Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption | |
| US6791391B2 (en) | Level shifting circuit | |
| KR960027337A (en) | Positive logic circuit with improved output signal level | |
| US5900745A (en) | Semiconductor device including input buffer circuit capable of amplifying input signal with low amplitude in high speed and under low current consumption | |
| CN108233917B (en) | Level conversion circuit | |
| US6661274B1 (en) | Level converter circuit | |
| US7365569B1 (en) | High-speed level shifter | |
| TW202215781A (en) | A hysteresis circuit, a receiver and a chip | |
| KR100416625B1 (en) | Input/output buffer of differential type for reducing variation of reference voltage | |
| CN116505934B (en) | Forward and reverse phase input stage circuit | |
| US8570091B2 (en) | Level shifter | |
| US11239842B1 (en) | Level down shifter | |
| KR100310883B1 (en) | Input circuit | |
| US20040051563A1 (en) | Symmetric differential logic circuits | |
| US20040056681A1 (en) | SSTL voltage translator with dynamic biasing | |
| CN113114173A (en) | Schmitt trigger | |
| JP3055230B2 (en) | Level shifter circuit | |
| US20030179013A1 (en) | Pseudo-NMOS logic having a feedback controller | |
| EP4072015A1 (en) | Level shifter | |
| US7737734B1 (en) | Adaptive output driver | |
| JPS63302622A (en) | Interface circuit | |
| JPH05259893A (en) | Semiconductor integrated circuit | |
| US7236030B2 (en) | Method to implement hysteresis in a MOSFET differential pair input stage | |
| TWM643204U (en) | Level conversion circuit for converting a small-amplitude input signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |