CN110995242A - High-speed level shifter - Google Patents
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
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Abstract
The high-speed level shifter provided by the invention comprises: the grid electrode of the first transistor is connected with IN, the source electrode of the first transistor is connected with the source electrode of the second transistor, and the drain electrode of the first transistor is connected with the source electrode of the fifth transistor; the grid electrode of the second transistor is connected with the output end of the first inverter, the source electrode of the second transistor is connected with the source electrode of the first transistor M1, the drain electrode of the second transistor is connected with the source electrode of the sixth transistor, the input end of the first inverter is connected with IN, and the power supply end of the first inverter is connected with VDDL; the grid electrode of the third transistor is connected with an input signal IN, the drain electrode of the third transistor is connected with VA, and the source electrode of the third transistor is connected with VDDL; the grid electrode of the fourth transistor is connected with the output end of the first inverter, the drain electrode of the fourth transistor is connected with VB, and the source electrode of the fourth transistor is connected with VDDL; the grid electrodes of the fifth transistor and the sixth transistor are connected with Vbias; the seventh transistor and the eighth transistor are cross-coupled; the grid electrode of the ninth transistor is connected with INNE, the source electrode of the ninth transistor is connected with the source electrode of the seventh transistor, and the drain electrode of the ninth transistor is connected with the drain electrode of the seventh transistor; the tenth transistor has a gate connected to the INPE, a drain connected to the drain of the eighth transistor, and a source connected to the source of the eighth transistor. The invention can shift the level of the high-speed signal under the condition of larger pressure difference, and the signal edge conversion rate is high.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed level shifter.
Background
A Phase-locked Loop (PLL) can generate a clock that is consistent in frequency and Phase with an input reference clock, and is widely used in synchronization and synchronization applications. Charge pump phase-locked loops (CPLLs) are widely used by virtue of their high speed, low power consumption, wide frequency capture range, and low cost. As shown in fig. 1, the charge pump phase-locked loop is composed of five parts, namely, a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop filter (LPF), a Voltage Controlled Oscillator (VCO), and a frequency Divider (Divider). A phase-locked loop generally requires two power supplies, such as a frequency Divider (Divider), a Phase Frequency Detector (PFD) and a Charge Pump (CP), to operate in a low voltage domain, and a high voltage domain. However, for level shifters, the voltage difference to be converted is larger and larger, such as 0.8V, which is commonly used in the 16nm process. When the Phase Frequency Detector (PFD) works under the voltage of 0.8V and the Charge Pump (CP) works under the power supply of 1.8V, the output signals UP and DN of the Phase Frequency Detector (PFD) need to be subjected to level conversion from 0.8V to 1.8V, and the output signals of the Phase Frequency Detector (PFD) are periodical narrow pulses, and the pulse width of the output signals is small and is often between 100ps and 200 ps. At this time, the conventional level shifter cannot achieve normal functions under different process angles, and signals are easily lost. In addition, the level shifter is also an indispensable part of the transceiver, and is widely applied to interface circuits such as DDR, USB, PCI, etc., wherein high-speed signals also need to be converted by the level shifter.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a level shifter with a quiescent current as is conventional in the prior art. IN fig. 2, M1, M2, M3 and M4 are all high voltage domain MOS transistors, IN is a low voltage output, VDDH is a high voltage power supply, and input low voltage signals are directly connected to high voltage transistors M1 and M2 to control the switching of the input transistors. M3 and M4 are current mirror loads, the circuit has DC current and DC power consumption, and the frequency of an input signal is limited because an input MOS tube is a high-voltage MOS.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a level shifter without a quiescent current according to the prior art. IN fig. 3, M1, M2, M3 and M4 are all high voltage domain MOS transistors, IN is a low voltage output, VDDH is a high voltage power supply, and input low voltage signals are directly connected to high voltage transistors M1 and M2 to control the switching of the input transistors. M3, M4 cross-coupling, fast locking output, this circuit does not have DC current, the power consumption is lower, but its input MOS pipe is high-voltage MOS too, the input signal rate supported is also lower.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a high-speed level shifter in the prior art. In fig. 4, M1 and M2 are low-voltage domain MOS, M5, M6, M7 and M8 are high-voltage domain MOS transistors, Vbias is an intermediate voltage, VA is limited on the gate of M5 and M6, VB does not exceed a low-voltage power supply, and the parasitic capacitance of VA and VB is larger because M5 and M6 are high-voltage MOS transistors and are larger in size. M7, M8 cross-coupled, fast locking the output. When the input signal IN is high, INN is low, M1 is turned on reversely, M2 is turned off, VA is pulled low, M2 is turned off, the parasitic voltage of VB point is large, VB voltage can only be slowly increased, M5 and M6 are normally turned on, the voltages of VA and VB are transmitted to VC and VD, and because the voltage change of VD point is slow, when the input pulse IN is narrow, the VD point possibly does not reach a stable state, and the level of the input signal is changed. Similarly, when the input signal IN is low, INN is high, M1 is turned off, M2 is turned back on, VB is pulled low, M1 is turned off, the parasitic voltage at the VA point is large, the VA voltage can only be slowly increased, M5 and M6 are always turned on, the voltages at VA and VB are transmitted to VC, VD, and the voltage at the VC point can be changed slowly. When the VC or VD voltage changes slowly, the M7 and M8 have limited effect, and when the input signal pulse is narrow, the signal edge is greatly attenuated, and the signal transmission may even go wrong.
In the prior art, when a level shifter carries out level shifting on a high-speed signal under the condition of large differential pressure, the problems of low conversion rate or signal attenuation exist.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a high-speed level shifter which can improve the edge transition rate of a signal and reserve the high-frequency energy of the signal when the high-speed level shifter carries out level shift on a high-speed signal under the condition of larger voltage difference.
In order to achieve the above purposes, the invention adopts the technical scheme that: a high speed level shifter, comprising:
low-voltage MOS tube: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a high voltage MOS transistor: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10,
the gate of the first transistor M1 is connected to the input signal IN, the source is connected to the source of the second transistor M2, and the drain is connected to the source of the fifth transistor M5; the gate of the second transistor M2 is connected to the output end of the first inverter INV1, the source is connected to the source of the first transistor M1, and the drain is connected to the source of the sixth transistor M6; the input end of the first inverter INV1 is connected with the input signal IN, and the power supply end is connected with VDDL voltage; the gate of the third transistor M3 is connected to the input signal IN, the drain is connected to the intermediate node VA, and the source is connected to the VDDL voltage; the gate of the fourth transistor M4 is connected to the output end of the first inverter INV1, the drain is connected to the intermediate node VB, and the source is connected to VDDL voltage;
the grid electrode of the fifth transistor M5 is connected with the intermediate voltage Vbias, and the drain electrode is connected with the drain electrode of the seventh transistor M7; the gate of the sixth transistor M6 is connected to the intermediate voltage Vbias, and the drain is connected to the drain of the eighth transistor M8; the source electrode of the seventh transistor M7 is connected with the source electrode of the eighth transistor M8, the grid electrode is connected with the middle node VD, and the drain electrode is connected with the drain electrode of the fifth transistor M5; the eighth transistor M8 has a gate connected to the intermediate node VC, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the sixth transistor M6; the ninth transistor M9 has a gate connected to the INNE voltage, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the seventh transistor M7; the tenth transistor M10 has a gate connected to the inp voltage, a drain connected to the drain of the eighth transistor M8, and a source connected to the source of the eighth transistor M8.
Further, the third transistor M3, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are PMOS transistors.
Further, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors.
Further, the high speed level shifter further includes a second inverter INV2 and a third inverter INV3 connected before the output terminal out, and power supply terminals of the second inverter INV2 and the third inverter INV3 are both connected to the VDDH voltage.
Further, the voltage of VDDH is 1.8v, the voltage of VDDL is 0.8v, and the voltage of Vbias is 1.1 v.
Further, the first inverter INV1, the second inverter INV2, and the third inverter INV3 are CMOS inverters or nor gates.
The high-speed level shifter has the advantages that the high-speed level shifter can shift the level of a high-speed signal under the condition of larger pressure difference, the edge conversion rate of the signal is improved, and the high-frequency energy of the signal is reserved.
Drawings
FIG. 1 is a circuit diagram of a charge pump phase locked loop of the prior art;
FIG. 2 is a schematic circuit diagram of a level shifter with quiescent current as is common in the prior art;
FIG. 3 is a circuit schematic of a conventional quiescent current free level shifter of the prior art;
FIG. 4 is a circuit schematic of a high speed level shifter of the prior art;
FIG. 5 is a schematic circuit diagram of a high speed level shifter according to the present invention;
FIG. 6 is a circuit schematic of an edge extraction circuit used in the present invention;
fig. 7 is a schematic diagram comparing waveforms of the high speed level shifter according to the present invention and a conventional level shifter.
Detailed Description
In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be further described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a high speed level shifter according to the present invention. The high-speed level shifter of the present invention comprises: low-voltage MOS tube: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a high voltage MOS transistor: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
The specific connection relationship of the high-speed level shifter provided by the invention is as follows: the gate of the first transistor M1 is connected to the input signal IN, the source is connected to the source of the second transistor M2, and the drain is connected to the source of the fifth transistor M5; the gate of the second transistor M2 is connected to the output end of the first inverter INV1, the source is connected to the source of the first transistor M1, and the drain is connected to the source of the sixth transistor M6; the input end of the first inverter INV1 is connected with the input signal IN, and the power supply end is connected with VDDL voltage; the gate of the third transistor M3 is connected to the input signal IN, the drain is connected to the intermediate node VA, and the source is connected to the VDDL voltage; the fourth transistor M4 has a gate connected to the output terminal of the first inverter INV1, a drain connected to the intermediate node VB, and a source connected to the VDDL voltage.
The grid electrode of the fifth transistor M5 is connected with the intermediate voltage Vbias, and the drain electrode is connected with the drain electrode of the seventh transistor M7; the gate of the sixth transistor M6 is connected to the intermediate voltage Vbias, and the drain is connected to the drain of the eighth transistor M8; the source electrode of the seventh transistor M7 is connected with the source electrode of the eighth transistor M8, the grid electrode is connected with the middle node VD, and the drain electrode is connected with the drain electrode of the fifth transistor M5; the eighth transistor M8 has a gate connected to the intermediate node VC, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the sixth transistor M6; the ninth transistor M9 has a gate connected to the INNE voltage, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the seventh transistor M7; the tenth transistor M10 has a gate connected to the inp voltage, a drain connected to the drain of the eighth transistor M8, and a source connected to the source of the eighth transistor M8.
In a specific embodiment, the third transistor M3, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are PMOS transistors.
In a specific embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors.
The high-speed level shifter further comprises a second inverter INV2 and a third inverter INV3 which are connected before the output end out, wherein power supply ends of the second inverter INV2 and the third inverter INV3 are both connected with the VDDH voltage. The first inverter INV1, the second inverter INV2 and the third inverter INV3 are CMOS inverters or nor gates. The second inverter INV2 and the third inverter INV3 function to output a digital signal with a full swing from the power supply to the ground.
It should also be noted that IN the present embodiment, three voltage supplies VDDL voltage, VDDH voltage, and the intermediate voltage Vbias are included IN addition to the input signal IN. The VDDL voltage is less than the VDDH voltage and the intermediate voltage Vbias is between the VDDL voltage and the VDDH voltage. In one specific implementation, the VDDH voltage is 1.8v, the VDDL voltage is 0.8v, and the Vbias voltage is 1.1 v.
The principle of the high-speed level shifter provided by the invention is as follows:
when IN is high level, INN is low level, M1 and M4 are conducted, VA and VB are respectively pulled down and pulled up, M5 and M6 are IN conducting state, VC and VD are respectively pulled down and pulled up, M7 and M8 quickly lock VD to high level, and finally OUT outputs high.
When IN is low level, INN is high level, M3 and M2 are conducted, VA and VB are respectively pulled high and low, M5 and M6 are IN conducting state, VC and VD are respectively pulled high and low, M7 and M8 are locked quickly, VD is low level, and finally OUT output is low.
When the input signal IN is at the rising edge and the falling edge, INPE and INNE can respectively generate a low pulse at the rising edge and the falling edge of IN, extract the information of the rising edge and the falling edge, pull up or pull down VD more quickly and reserve the high-frequency energy of the signal. The generation principle of the INNE and the INPE is shown in FIG. 6, and FIG. 6 is a circuit diagram of an edge extraction circuit used in the present invention. The input signal IN and the own inverted signal are not and to obtain the output OUT, and because the IN and the own inverted signal have time delay, the output OUT can generate a short low pulse at the rising edge transition of the IN, and the pulse width is equal to the time delay of the IN and the inverted signal. When IN IN FIG. 5 is used as input IN IN FIG. 6, the output OUT of FIG. 6 can be used as INPE; when INN IN FIG. 5 is used as input IN IN FIG. 6, the output OUT of FIG. 6 can be used as INNE. Where INN is the output of IN through the first inverter and INN is the inverted signal of IN.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating a comparison between waveforms of the high speed level shifter and a conventional level shifter according to the present invention. The solid line graph IN fig. 7 is the waveform of the high-speed level shifter (as shown IN fig. 5) proposed by the present invention, and the dotted line graph is the waveform of the conventional level shifter (as shown IN fig. 4), both input signals IN, INB are completely identical, and the pulse width is about 100 ps. The level shifter provided by the invention has the advantages that under the same input, the edges of the intermediate nodes VA, VB, VC and VD are steeper, the edge transition rate is closer to the edge transition rate of an input signal, and under the condition of adopting the same output driving, the pulse width of an output point OUT is also closer to the pulse width of the input signal IN.
In the embodiment shown in fig. 7, the ratio (W/L) of the width to the length of the MOS transistor is: (W/L) _ M1 ═ 2.152/0.016, (W/L) _ M2 ═ 2.152/0.016, (W/L) _ M3 ═ 2.152/0.016, (W/L) _ M4 ═ 2.152/0.016, (W/L) _ M5 ═ 3.46/0.134, (W/L) _ M6 ═ 3.46/0.134, (W/L) _ M7 ═ 0.616/0.134, (W/L) _ M8 ═ 0.616/0.134, (W/L) _ M9 ═ 0.616/0.134, (W/L) _ M10 ═ 0.616/0.134.
Different from the prior art, the high-speed level shifter provided by the invention can shift the level of a high-speed signal under the condition of larger pressure difference, improve the edge conversion rate of the signal and reserve the high-frequency energy of the signal.
It will be understood by those skilled in the art that the high speed level shifter of the present invention is not limited to the embodiments described in the detailed description, and the above detailed description is for the purpose of illustrating the invention and is not intended to limit the invention. Other embodiments will be apparent to those skilled in the art from the following detailed description, which is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A high speed level shifter, comprising:
low-voltage MOS tube: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a high voltage MOS transistor: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10,
the gate of the first transistor M1 is connected to the input signal IN, the source is connected to the source of the second transistor M2, and the drain is connected to the source of the fifth transistor M5; the gate of the second transistor M2 is connected to the output end of the first inverter INV1, the source is connected to the source of the first transistor M1, and the drain is connected to the source of the sixth transistor M6; the input end of the first inverter INV1 is connected with the input signal IN, and the power supply end is connected with VDDL voltage; the gate of the third transistor M3 is connected to the input signal IN, the drain is connected to the intermediate node VA, and the source is connected to the VDDL voltage; the gate of the fourth transistor M4 is connected to the output end of the first inverter INV1, the drain is connected to the intermediate node VB, and the source is connected to VDDL voltage;
the grid electrode of the fifth transistor M5 is connected with the intermediate voltage Vbias, and the drain electrode is connected with the drain electrode of the seventh transistor M7; the gate of the sixth transistor M6 is connected to the intermediate voltage Vbias, and the drain is connected to the drain of the eighth transistor M8; the source electrode of the seventh transistor M7 is connected with the source electrode of the eighth transistor M8, the grid electrode is connected with the middle node VD, and the drain electrode is connected with the drain electrode of the fifth transistor M5; the eighth transistor M8 has a gate connected to the intermediate node VC, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the sixth transistor M6; the ninth transistor M9 has a gate connected to the INNE voltage, a source connected to the source of the seventh transistor M7, and a drain connected to the drain of the seventh transistor M7; the tenth transistor M10 has a gate connected to the inp voltage, a drain connected to the drain of the eighth transistor M8, and a source connected to the source of the eighth transistor M8.
2. The high speed level shifter of claim 1, wherein the third, fourth, seventh, eighth, ninth, and tenth transistors M3, M4, M7, M8, M9, and M10 are PMOS transistors.
3. The high speed level shifter of claim 1, wherein the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors.
4. The high speed level shifter of claim 1, further comprising a second inverter INV2 and a third inverter INV3 connected before the output terminal out, wherein power source terminals of the second inverter INV2 and the third inverter INV3 are both connected to the VDDH voltage.
5. The high speed level shifter of claim 4, wherein the VDDH voltage is 1.8v, the VDDL voltage is 0.8v, and the Vbias voltage is 1.1 v.
6. The high speed level shifter of claim 1, wherein the first, second and third inverters INV1, INV2 and INV3 are CMOS inverters or NOR gates.
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| CN201910949011.7A CN110995242A (en) | 2019-10-08 | 2019-10-08 | High-speed level shifter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910949011.7A CN110995242A (en) | 2019-10-08 | 2019-10-08 | High-speed level shifter |
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| CN110995242A true CN110995242A (en) | 2020-04-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115913214A (en) * | 2023-01-09 | 2023-04-04 | 上海芯楷集成电路有限责任公司 | Positive and negative high voltage level switching circuit |
| TWI817389B (en) * | 2022-03-15 | 2023-10-01 | 智原科技股份有限公司 | Level shifter and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741376A (en) * | 2008-11-18 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Ultra-low voltage level shifting circuit |
| CN101908880A (en) * | 2009-06-02 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Level shifter |
| CN108599755A (en) * | 2018-02-02 | 2018-09-28 | 豪威科技(上海)有限公司 | Level shift circuit |
-
2019
- 2019-10-08 CN CN201910949011.7A patent/CN110995242A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741376A (en) * | 2008-11-18 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Ultra-low voltage level shifting circuit |
| CN101908880A (en) * | 2009-06-02 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Level shifter |
| CN108599755A (en) * | 2018-02-02 | 2018-09-28 | 豪威科技(上海)有限公司 | Level shift circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI817389B (en) * | 2022-03-15 | 2023-10-01 | 智原科技股份有限公司 | Level shifter and electronic device |
| CN115913214A (en) * | 2023-01-09 | 2023-04-04 | 上海芯楷集成电路有限责任公司 | Positive and negative high voltage level switching circuit |
| CN115913214B (en) * | 2023-01-09 | 2023-06-27 | 上海芯楷集成电路有限责任公司 | Positive and negative high voltage level conversion circuit |
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Application publication date: 20200410 |