CN109672439A - Pressure-resistant level shifting circuit - Google Patents
Pressure-resistant level shifting circuit Download PDFInfo
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- CN109672439A CN109672439A CN201910043120.2A CN201910043120A CN109672439A CN 109672439 A CN109672439 A CN 109672439A CN 201910043120 A CN201910043120 A CN 201910043120A CN 109672439 A CN109672439 A CN 109672439A
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- level
- pmos tube
- phase inverter
- tube
- nmos
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a kind of pressure-resistant level shifting circuits, which includes level conversion unit, two-stage phase inverter and two output pmos fets；Level conversion unit and two-stage phase inverter are powered by high level and are equipped with two bias voltages of low level and mid-level；Level-one phase inverter is given in output after level conversion unit is converted incoming level, and level conversion unit is connected with level-one phase inverter, and second level phase inverter is connect with level-one phase inverter, for driving output PMOS tube to export switching levels.The circuit raises pressure-resistant performance of PMOS tube so that metal-oxide-semiconductor be pressed also to have preferable pressure-resistant effect in use, while having quick responding ability and lower temperature rise, and reduce circuit cost.
Description
Technical field
The present invention relates to press MOSFET (metal-oxygen in a kind of pressure-resistant level shifting circuit more particularly to a kind of all uses
Compound semiconductor field effect transistor) pressure-resistant level shifting circuit.
Background technique
In design of electronic circuits of new generation, as the digital IC of different operating voltage is continued to bring out, low logic voltage
Introducing so that the necessity of logic level transition is more prominent.For example, working as the digital circuit of 1.8V and working in the mould of 3.3V
When quasi- circuit is communicated, needs to solve the transfer problem of two kinds of level first, at this moment just need level conversion.Meanwhile in order to
Electronic product power consumption demand is reduced, many electronic systems continue to shift to lower level voltage signal.Faster commutating speed
Designer is both facilitated with the progress for reducing signal noise etc., new challenge is also proposed to them.Microprocessor to
Lower voltage level is taken the lead during marching.Processor I/O voltage is just transferred to 1.5V from 1.8V, and core voltage
1V can be lower than.Future generation microprocessors even will use lower voltage.Although the voltage of peripheral device component is also reducing,
But it is horizontal usually to lag behind processor generation or so.The development unevenness that voltage reduces aspect, which brings system designer, to be solved
Key problem, i.e., how reliably to be converted between signal level.Correct signal level can guarantee system
Reliably working, they can prevent sensitive IC to be damaged because of excessively high or too low voltage conditions.
Important original part in level shifting circuit is Metal-Oxide Semiconductor field effect transistor
(MOSFET), high-voltage MOS pipe as described herein refers to the resistance to MOSFET for being pressed in 20V or more, ability to bear of the middle pressure metal-oxide-semiconductor to high pressure
Want lower, generally between 3~6v, the case where low pressure MOS is then mainly used for resistance to low pressure.Traditional pressure-resistant level conversion electricity
Road generallys use high-voltage MOS pipe design, has the advantages that circuit structure is compact, stability is good.But the sound of high-voltage MOS pipe
Answer speed slow compared to mesolow metal-oxide-semiconductor, Ron is bigger, Wen Shenggao when working under high pressure.Moreover, level shifting circuit
A variety of metal-oxide-semiconductors can generally be used, using the different metal-oxide-semiconductor Mixed Design of a variety of pressure-resistant performances, in price from the point of view of than only making
With the high several times of design of middle pressure metal-oxide-semiconductor.
Summary of the invention
Goal of the invention: in view of the above problems, the present invention proposes that a kind of pressure-resistant level shifting circuit, the circuit can either be born
Biggish supply voltage has quick responding ability and lower temperature rise, while being also greatly reduced circuit cost.
Technical solution: the technical scheme adopted by the invention is that a kind of pressure resistance level shifting circuit, which includes level
Pmos fet is used in converting unit, two-stage phase inverter and two outputs；Level conversion unit and two-stage phase inverter by
High level powers and is equipped with two bias voltages of low level and mid-level；Level conversion unit is connected with level-one phase inverter, electricity
Level-one phase inverter is given in output after flat converting unit is converted incoming level, and level-one phase inverter is used to drive the first PMOS tube,
Second level phase inverter is connected with level-one phase inverter and is used to drive the second PMOS tube；First PMOS tube and the output conversion of the second PMOS tube
Level afterwards.
Further, the level conversion unit includes 4 PMOS tube, 4 NMOS tubes and third phase inverter；With low level
Two PMOS tube of connection are respectively used to raise the drain voltage of the third PMOS tube and the 4th PMOS tube that are connected with high level, with
Two NMOS tubes of mid-level connection are used to clamp down on the drain voltage of third NMOS tube and the 4th NMOS tube；4th PMOS tube
Drain electrode and the drain electrode of the 4th NMOS tube are respectively two output ends of level conversion unit.The third PMOS tube and the 4th PMOS
Pipe, the source electrode of the two connect high level, and the drain electrode of the grid of third PMOS tube and the 4th PMOS tube is connected, the grid of the 4th PMOS tube
Pole is connected with the drain electrode of third PMOS tube.By power at very low levels, input terminal is connect the third phase inverter with incoming level, defeated
Outlet is connected with the grid of the 4th NMOS tube, for providing and the opposite polarity signal of incoming level to the 4th NMOS tube.
Further, the level-one phase inverter is composed in series by four metal-oxide-semiconductors, and the 8th PMOS tube connecting with low level is used
In the drain voltage for raising the 7th PMOS tube being connected with high level, the 7th NMOS tube that connect with mid-level is for clamping down on the
The voltage that the drain voltage of eight NMOS tubes, the drain electrode of the 7th PMOS tube and the drain electrode of the 8th NMOS tube are exported is anti-as next stage
The input of phase device, output end of the drain electrode of the 8th PMOS tube as level-one phase inverter.
Further, the second level phase inverter is composed in series by four metal-oxide-semiconductors, and the tenth PMOS tube connecting with low level is used
In the drain voltage for raising the 9th PMOS tube being connected with high level, the 9th NMOS tube that connect with mid-level is for clamping down on the
The drain voltage of ten NMOS tubes, output end of the drain electrode of the tenth PMOS tube as second level phase inverter.Wherein, the tenth NMOS tube
Source electrode connect low level.
The utility model has the advantages that it is of the present invention pressure resistance level shifting circuit compared with prior art, have the advantage that (1) with
The PMOS tube of low level connection has raised the drain voltage for the PMOS tube being connected with high level, avoids the PMOS tube for bearing high voltage
Occur because VDS voltage it is excessive caused by puncture；The NMOS tube connecting with mid-level can clamp down on the NMOS tube of source electrode ground connection
Drain voltage, avoid it from bearing excessively high voltage and puncture；By designing above, the pressure-resistant performance of PMOS tube is improved, from
And press metal-oxide-semiconductor that also there is preferable pressure-resistant effect in use；(2) pressure MOSFET replaces the design of high pressure resistant MOSFET in using,
Greatly reduce circuit cost.
Detailed description of the invention
Fig. 1 is the structure chart of pressure-resistant level shifting circuit of the present invention；
Fig. 2 is the partial timing diagram of pressure-resistant level shifting circuit of the present invention.
Specific embodiment
Further description of the technical solution of the present invention with reference to the accompanying drawings and examples.
A kind of pressure-resistant level shifting circuit of the present invention, as shown in Figure 1, including level conversion unit, two-stage reverse phase
Pmos fet (the first PMOS tube MP1 and the second PMOS tube MP2) is used in device and two outputs；Level conversion unit and two
Grade phase inverter is powered by high level VH and is equipped with two bias voltages of low level VL and mid-level VM；Level conversion unit with
Level-one phase inverter is connected, and level-one phase inverter is given in output after level conversion unit is converted incoming level, and level-one phase inverter is used
In driving the first PMOS tube MP1, second level phase inverter is connected with level-one phase inverter and is used to drive the second PMOS tube MP2；First
Level VOUT after PMOS tube MP1 and the second PMOS tube MP2 output conversion.
The specific structure of each unit described below:
The level conversion unit includes 4 PMOS tube, 4 NMOS tubes and third phase inverter.Third NMOS tube and the 4th
The source electrode of NMOS tube is grounded, and the grid of the 5th NMOS tube and the 6th NMOS tube is connect with mid-level VM, the drain electrode difference of the two
It is connected with the drain electrode of third NMOS tube and the 4th NMOS tube, for clamping down on the drain voltage of third NMOS tube and the 4th NMOS tube.
The source electrode of third PMOS tube and the source electrode of the 4th PMOS tube connect high level VH, the grid company of the 5th PMOS tube and the 6th PMOS tube
Low level VL is met, the drain electrode of the two is connected with the drain electrode of third NMOS tube and the 4th NMOS tube respectively, for raising the 3rd PMOS
The drain voltage of pipe and the 4th PMOS tube.The drain electrode of the grid of third PMOS tube and the 4th PMOS tube is connected, the 4th PMOS tube
Grid is connected with the drain electrode of third PMOS tube.The drain electrode of 4th PMOS tube and the drain electrode of the 4th NMOS tube are respectively level conversion list
Two output ends (yh0, yl0) of member.The third phase inverter is powered by low level VL, to two of its input terminal and output end
NMOS provides two opposite polarity signals, and (for example, input is 0, output is VL；Or input is VL, 0) output is.
The level-one phase inverter is composed in series by four metal-oxide-semiconductors, the 8th PMOS tube being connect with low level for raise with
The drain voltage of the 7th connected PMOS tube of high level, the 7th NMOS tube connecting with mid-level is for clamping down on the 8th NMOS tube
Drain voltage, the 7th PMOS tube drain electrode and the 8th NMOS tube drain electrode output (yh1, yl1) be used as next stage phase inverter
Input, output end (y1) of the drain electrode as level-one phase inverter of the 8th PMOS tube.There are two input terminals for level-one phase inverter, respectively
Connect two output ends (yh0, yl0) of level conversion unit.The polarity of two output end yh0 and yl0 is identical, be all high level or
Person's low level is intended merely to solve the problems, such as device pressure resistance, cannot expire amplitude of oscillation work, with one PMOS and NMOS of two inputs plus series connection
Pressure limiting circuit it is pressure-resistant to solve the problems, such as.
The structure of the second level phase inverter is identical with level-one phase inverter, is composed in series by four metal-oxide-semiconductors, is connect with low level
The tenth PMOS tube be used to raise the drain voltage of the 9th PMOS tube being connected with high level, the 9th connect with mid-level
NMOS tube is used to clamp down on the drain voltage of the tenth NMOS tube, output end of the drain electrode of the tenth PMOS tube as second level phase inverter
(y2), the source electrode of the tenth NMOS tube meets low level VL.
Analyze how the circuit meets pressure-resistant condition in detail below:
It presses PMOS tube that can clamp down on the drain voltage of 4 PMOS tube above in 4 of low level VL connection, avoids seeing 0v
Ground, so that the range of the drain voltage of 4 PMOS tube above is VH~VL+ | VT |, VDS range is VS-VD=(VH-VH~VH-
VL- | VT |)=(0~VH-VL- | VT |), as long as VDS=VH-VL- | VT | it is out of question as long as the pressure-resistant range of middle pressure mos.Example
Such as: VH=7.5v, VL=1.5v, in the case that middle pressure metal-oxide-semiconductor is 6v element, 7.5-1.5- | VT |=6- | VT | < 6V.Grid
Also it is added in here, so VGS is also met the requirements.It is (VH-VH)~VL+ that pmos, VDS are pressed in 4 that low level VL is connected | VT
| -0, as long as i.e. 0~VL+ | VT | < VM (VM is medium pressure element pressure voltage), pressure resistance is able to satisfy requirement.The VM is both pressure resistance
Value and added bias voltage, the pressure resistance of NMOS can be guaranteed by doing bias voltage with pressure voltage.
The pmos, V (yh0)-VL >=Vt that level-one phase inverter is used to that the first PMOS tube MP1, yh0 to be driven to have gate to meet VL below
Available VH >=V (yh0) >=VL+Vt, so | Vgs |=VH-V (yh0)≤VH-VL-Vt, similarly | and Vds |=VH-V (yh1)
≤ VH-VL-Vt, meeting voltage as long as the pressure-resistant range that the voltage range is not above the device of first order phase inverter pmos can
By property problem；The similarly direction nmos, VM-V (yl0) >=Vt can obtain Vgs=V (yl0)≤VM-Vt, similarly Vds=V (yl1)≤
VM-Vt.To sum up, first order phase inverter meets pressure-resistant condition, and the range of output point y1 is: VH >=y1 >=0.Second level phase inverter is used for
The second PMOS tube MP2 is driven, second level phase inverter can be similarly obtained and also meet pressure resistance adjusting.But because of the source of the second PMOS tube MP2
VH is terminated, if the low level of y2 is 0 to will lead to | Vgs |=VH-0=VH is more than device pressure resistance, so second level phase inverter
Low level meets VL, so that | Vgs |=VH-VL, within the scope of device pressure resistance.
It presses NMOS tube to clamp down on the drain voltage of 4 following NMOS tubes in 4 of mid-level VM connection, avoids seeing
VH, so that the range of the drain voltage of following 4 NMOS tubes is the < of VM-VT~0 VM.The VDS of NMOS is pressed in 4 of VM connection
Are as follows: VH-VM+VT~0, as long as VH-VM+VT < VM (pressure voltage that VM is medium pressure element), meets resistance to pressure request, such as at this
7.5-6+VT=1.5-VT < 6 in example.
Middle pressure pipe natively can be used in first PMOS tube MP1, because while gate voltage range is VH~0, but VS
=VL, VD:VL~VH, so the working range of VGS and VDS is not above the working range of middle pressure pipe in instances.First
The Vgs:VH-VL of PMOS tube MP1 >=| Vgs | >=VL, because of Vout:VH >=Vout >=VL, Vds:VH-VL >=| Vds | >=0.Therefore
First PMOS tube MP1 meets pressure-resistant condition.Second PMOS tube MP2 is also middle pressure pipe, but if gate voltage range is constant also
It is VH~0, has been more than that the pressure resistance of middle pressure pipe just has integrity problem, so the low level of second level phase inverter cannot connect 0, and
It is to be connected to VL, so that gate voltage range is VH~VL, the range of VGS is exactly that VH-VG is VH-VH=0~VH-VL, and VH-VL exists
7.5-1.5=6≤6 are in the pressure-resistant range of middle pressure pipe in example, and the range of VDS is identical, so pressure resistance is met the requirements.
Substrate problem need not specified otherwise, be because general VDB pressure resistance it is all more high pressure resistant than other both ends, therefore, generally
NMOS can be grounded, and PMOS can connect high level.But if VDB pressure resistance is not enough, technique, which provides substrate, can not connect unified ground
NMOS or substrate do not meet the PMOS of unified power supply, it is certainly safer that substrate connects source.
As shown in Fig. 2, for the timing diagram (part) of pressure-resistant level shifting circuit of the present invention, when input voltage rising edge
When arrival, level-one phase inverter exports low level 0, and driving the first PMOS tube output Vout is low level VL, realizes level conversion
Function.When input voltage is reduced to 0, second level phase inverter exports low level VL, and driving the second PMOS tube output Vout is high level
VH。
Claims (7)
1. a kind of pressure resistance level shifting circuit, it is characterised in that: the circuit includes level conversion unit, two-stage phase inverter and two
Pmos fet (MP1, MP2) is used in output；Level conversion unit and two-stage phase inverter are powered simultaneously by high level (VH)
Equipped with two bias voltages of low level (VL) and mid-level (VM)；Level conversion unit is connected with level-one phase inverter, and level turns
It changes output after unit is converted incoming level (VIN) and gives level-one phase inverter, level-one phase inverter is for driving the first PMOS tube
(MP1), second level phase inverter is connected with level-one phase inverter and is used to drive the second PMOS tube (MP2)；First PMOS tube (MP1) and
Level after two PMOS tube (MP2) output conversion.
2. pressure resistance level shifting circuit according to claim 1, it is characterised in that: the level conversion unit includes 4
PMOS tube, 4 NMOS tubes and third phase inverter；Two PMOS tube (MP5, MP6) connecting with low level (VL) are respectively used to lift
The drain voltage of third PMOS tube (MP3) and the 4th PMOS tube (MP4) that height is connected with high level (VH), with mid-level (VM)
Two NMOS tubes (MN5, MN6) of connection are used to clamp down on the drain voltage of third NMOS tube (MN3) and the 4th NMOS tube (MN4)；
The drain electrode of 4th PMOS tube (MP4) and the drain electrode of the 4th NMOS tube (MN4) are respectively two output ends of level conversion unit.
3. pressure resistance level shifting circuit according to claim 2, it is characterised in that: the third PMOS tube (MP3) and the
The source electrode of four PMOS tube (MP4), the two connects high level (VH), the grid of third PMOS tube (MP3) and the 4th PMOS tube (MP4)
Drain electrode be connected, the grid of the 4th PMOS tube (MP3) is connected with the drain electrode of third PMOS tube (MP4).
4. pressure resistance level shifting circuit according to claim 2, it is characterised in that: the third phase inverter is by low level
(VL) power, input terminal connect with incoming level (VIN), and output end is connected with the grid of the 4th NMOS tube, be used for
4th NMOS tube provides and incoming level (VIN) opposite polarity signal.
5. pressure resistance level shifting circuit according to claim 1, it is characterised in that: the level-one phase inverter is by four MOS
Pipe is composed in series, and the 8th PMOS tube (MP8) connecting with low level (VL) is for raising the 7th to be connected with high level (VH)
The drain voltage of PMOS tube (MP7), the 7th NMOS tube (MN7) connecting with mid-level (VM) is for clamping down on the 8th NMOS tube
(MN8) the voltage conduct that drain voltage, the drain electrode of the 7th PMOS tube (MP7) and the drain electrode of the 8th NMOS tube (MN8) are exported
The input of next stage phase inverter, output end of the drain electrode of the 8th PMOS tube (MP8) as level-one phase inverter.
6. pressure resistance level shifting circuit according to claim 1, it is characterised in that: the second level phase inverter is by four MOS
Pipe is composed in series, and the tenth PMOS tube (MP10) connecting with low level (VL) is for raising the 9th to be connected with high level (VH)
The drain voltage of PMOS tube (MP9), the 9th NMOS tube (MN9) connecting with mid-level (VM) is for clamping down on the tenth NMOS tube
(MN10) drain voltage, output end of the drain electrode of the tenth PMOS tube (MP10) as second level phase inverter.
7. pressure resistance level shifting circuit according to claim 6, it is characterised in that: the source of the tenth NMOS tube (MN10)
Pole meets low level (VL).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910043120.2A CN109672439A (en) | 2019-01-17 | 2019-01-17 | Pressure-resistant level shifting circuit |
| PCT/CN2019/100234 WO2020147306A1 (en) | 2019-01-17 | 2019-08-12 | Withstand voltage level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910043120.2A CN109672439A (en) | 2019-01-17 | 2019-01-17 | Pressure-resistant level shifting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109672439A true CN109672439A (en) | 2019-04-23 |
Family
ID=66149458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910043120.2A Pending CN109672439A (en) | 2019-01-17 | 2019-01-17 | Pressure-resistant level shifting circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109672439A (en) |
| WO (1) | WO2020147306A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020147306A1 (en) * | 2019-01-17 | 2020-07-23 | 南京观海微电子有限公司 | Withstand voltage level conversion circuit |
| CN114421950A (en) * | 2022-01-17 | 2022-04-29 | 北京奕斯伟计算技术有限公司 | Level conversion circuit, chip and display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422601B (en) * | 2021-08-23 | 2021-11-16 | 上海灵动微电子股份有限公司 | Voltage conversion high-level isolation unit based on magnetic tunnel junction |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559464A (en) * | 1993-07-06 | 1996-09-24 | Seiko Epson Corporation | Signal voltage level conversion circuit and output buffer circuit |
| CN201323560Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | High-capacity switch driving circuit |
| CN102270984A (en) * | 2011-07-01 | 2011-12-07 | 清华大学 | Positive high voltage level conversion circuit |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
| CN103178829A (en) * | 2011-12-20 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Level shifting circuit |
| CN103825599A (en) * | 2014-03-10 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Level switching circuit |
| CN203851128U (en) * | 2014-05-13 | 2014-09-24 | 湖南进芯电子科技有限公司 | High-sped wide-region low-to-high double-end output level converting circuit |
| CN104901681A (en) * | 2015-06-12 | 2015-09-09 | 长沙景嘉微电子股份有限公司 | 2VDD level switching circuit of VDD voltage-withstand CMOS |
| CN106505988A (en) * | 2016-11-10 | 2017-03-15 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuits |
| CN108155903A (en) * | 2017-11-22 | 2018-06-12 | 中山大学 | High speed and high pressure level shifting circuit applied to GaN gate drivings |
| CN108233917A (en) * | 2016-12-15 | 2018-06-29 | 江苏安其威微电子科技有限公司 | Level shifting circuit |
| CN209517097U (en) * | 2019-01-17 | 2019-10-18 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4471226B2 (en) * | 2007-07-23 | 2010-06-02 | 統寶光電股▲ふん▼有限公司 | Semiconductor integrated circuit |
| US8362803B2 (en) * | 2011-02-18 | 2013-01-29 | Lsi Corporation | Mode latching buffer circuit |
| CN104601164A (en) * | 2015-02-04 | 2015-05-06 | 苏州大学 | Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit |
| CN108134601B (en) * | 2016-11-30 | 2021-08-06 | 上海复旦微电子集团股份有限公司 | Interface circuit |
| CN109672439A (en) * | 2019-01-17 | 2019-04-23 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
-
2019
- 2019-01-17 CN CN201910043120.2A patent/CN109672439A/en active Pending
- 2019-08-12 WO PCT/CN2019/100234 patent/WO2020147306A1/en active Application Filing
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559464A (en) * | 1993-07-06 | 1996-09-24 | Seiko Epson Corporation | Signal voltage level conversion circuit and output buffer circuit |
| CN201323560Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | High-capacity switch driving circuit |
| CN102270984A (en) * | 2011-07-01 | 2011-12-07 | 清华大学 | Positive high voltage level conversion circuit |
| CN103178829A (en) * | 2011-12-20 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Level shifting circuit |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
| CN103825599A (en) * | 2014-03-10 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Level switching circuit |
| CN203851128U (en) * | 2014-05-13 | 2014-09-24 | 湖南进芯电子科技有限公司 | High-sped wide-region low-to-high double-end output level converting circuit |
| CN104901681A (en) * | 2015-06-12 | 2015-09-09 | 长沙景嘉微电子股份有限公司 | 2VDD level switching circuit of VDD voltage-withstand CMOS |
| CN106505988A (en) * | 2016-11-10 | 2017-03-15 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuits |
| CN108233917A (en) * | 2016-12-15 | 2018-06-29 | 江苏安其威微电子科技有限公司 | Level shifting circuit |
| CN108155903A (en) * | 2017-11-22 | 2018-06-12 | 中山大学 | High speed and high pressure level shifting circuit applied to GaN gate drivings |
| CN209517097U (en) * | 2019-01-17 | 2019-10-18 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020147306A1 (en) * | 2019-01-17 | 2020-07-23 | 南京观海微电子有限公司 | Withstand voltage level conversion circuit |
| CN114421950A (en) * | 2022-01-17 | 2022-04-29 | 北京奕斯伟计算技术有限公司 | Level conversion circuit, chip and display device |
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| Publication number | Publication date |
|---|---|
| WO2020147306A1 (en) | 2020-07-23 |
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