CN113422601B - Voltage conversion high-level isolation unit based on magnetic tunnel junction - Google Patents
Voltage conversion high-level isolation unit based on magnetic tunnel junction Download PDFInfo
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- CN113422601B CN113422601B CN202110964930.9A CN202110964930A CN113422601B CN 113422601 B CN113422601 B CN 113422601B CN 202110964930 A CN202110964930 A CN 202110964930A CN 113422601 B CN113422601 B CN 113422601B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Abstract
The application provides a voltage conversion high level isolation unit based on magnetic tunnel junction includes: the high-level isolation circuit comprises a first inverter, a transmission gate, a fourth inverter, a second inverter, a third inverter and a high-level isolation unit, wherein the first inverter, the transmission gate and the fourth inverter are connected between a high-voltage source and a ground terminal, the second inverter and the third inverter are connected between a low-voltage source and the ground terminal, and the high-level isolation unit is based on a magnetic tunnel junction. The high-level isolation unit includes a first PMOS transistor, first and second NMOS transistors, a fifth inverter, a resistor, and a magnetic tunnel junction. After two groups of voltage sources are powered down, signals of the magnetic tunnel junction can be always kept and read by an external reading circuit, and therefore the effect of isolating and latching high level is achieved.
Description
Technical Field
The present application relates to the field of integrated circuits, and more particularly to a magnetic tunnel junction based voltage conversion high level isolation unit.
Background
Modern electronic devices, which usually rely on battery power, often have low power consumption designs, and enter a sleep state when they are inactive, and when they enter a standby mode, the internal chip circuitry still consumes power to retain data. The traditional CMOS circuit uses isolation unit devices to isolate and hold data, and most of standby current is consumed in leakage because the CMOS circuit cannot be completely turned off. The conventional isolated cell device is implemented by providing two power supplies, one for holding data when the chip enters a standby mode, and one that can be turned off to save power consumption. With the reduction of process nodes, the electric leakage is higher and higher, the problem of the electric leakage is more and more difficult to solve by the traditional technology, and how to reduce the electric leakage becomes a main target.
The low-voltage to high-voltage conversion high-level isolation unit is a unit for performing voltage conversion of signals between low voltage and high voltage, and as shown IN fig. 1, the circuit structure is composed of two voltage sources VDDH, VDDL, and an input signal DATA _ IN is inputted through the voltage conversion, and the unit can not only perform voltage conversion, but also isolate an output signal to a fixed high level through a SLEEP signal IN case that the input voltage domain VDDL is powered down. When SLEEP is 0, DATA _ IN goes from low to high voltage signal, DATA _ OUT = DATA _ IN. When SLEEP is 1, the output DATA _ OUT of the nand gate is 1 when SLEEP is 0, and VDDL can be powered off at this time, so that the function of latching DATA _ OUT to be high level is realized.
In the existing circuit structure, a NAND gate is used for realizing the function of isolating high level, the NAND gate has electric leakage and is supplied with power at high voltage, the electric leakage of the NAND gate is large, about 60 pA, and in order to isolate boundary signals of low voltage and high voltage in the chip design, a plurality of units are often adopted, so that the chip also has large electric leakage after entering a low power consumption mode.
Disclosure of Invention
The application aims to provide a voltage conversion high-level isolation unit based on a magnetic tunnel junction, which realizes isolation and latching of high level and reduces electric leakage.
The application discloses voltage conversion high level isolation unit based on magnetic tunnel junction includes: the high-level isolation circuit comprises a first inverter, a transmission gate, a fourth inverter, a second inverter, a third inverter and a high-level isolation unit, wherein the first inverter, the transmission gate and the fourth inverter are connected between a high-voltage source and a ground terminal;
wherein the input end of the first inverter is connected with a sleep signal, the input end of the second inverter is connected with a data signal, the output end of the first inverter is connected with the input end of the third inverter, the transmission gate comprises a second PMOS transistor and a third PMOS transistor, and a third NMOS transistor to a sixth NMOS transistor, the sources of the second PMOS transistor and the third PMOS transistor are both connected with the high voltage source, the grid of the second PMOS transistor, the drain of the third PMOS transistor, the source of the fourth NMOS transistor are connected with the input end of the fourth inverter, the grid of the third PMOS transistor, the drain of the second PMOS transistor are connected with the source of the third NMOS transistor, the grids of the third NMOS transistor and the fourth NMOS transistor are connected with the output end of the first inverter, the drain of the third NMOS transistor is connected with the drain of the fifth NMOS transistor, and the grid of the fifth NMOS transistor is connected with the output end of the third inverter, the drain electrode of the fourth NMOS transistor is connected with the drain electrode of the sixth NMOS transistor, and the grid electrode of the sixth NMOS transistor is connected with the input end of the third inverter;
wherein the magnetic tunnel junction-based high-level isolation unit comprises a first PMOS transistor, first and second NMOS transistors, a fifth inverter, a resistor and a magnetic tunnel junction, wherein the input end of the fifth inverter and the gate of the first NMOS transistor are connected with the sleep signal, the output end of the fifth inverter is connected with the gate of the first PMOS transistor and the gate of the second NMOS transistor, the source of the first PMOS transistor is connected with the high-voltage source, the source of the second NMOS transistor is connected with the output end of the fourth inverter, the drain of the first PMOS transistor is connected with the drain of the second NMOS transistor, one end of the resistor is connected with the gate of the second NMOS transistor, the other end of the resistor is connected with the ground, one end of the magnetic tunnel junction is connected with the drains of the first PMOS transistor and the second NMOS transistor, the other end of the first NMOS transistor is connected with the drain electrode of the first NMOS transistor, and the source electrode of the first NMOS transistor is connected with the ground end.
In one preferred embodiment, the magnetic tunnel junction includes a free layer connecting the drain of the first PMOS transistor, a barrier layer, and a reference layer connecting the drain of the first NMOS transistor.
In a preferred embodiment, the first inverter includes a fourth PMOS transistor and a seventh NMOS transistor, wherein gates of the fourth PMOS transistor and the seventh NMOS transistor are connected to the sleep signal, a source of the fourth PMOS transistor is connected to the high voltage source, a source of the seventh NMOS transistor is connected to the ground, and drains of the fourth PMOS transistor and the seventh NMOS transistor are connected to gates of the third and fourth NMOS transistors.
In a preferred example, the second inverter includes a fifth PMOS transistor and an eighth NMOS transistor, the third inverter includes a sixth PMOS transistor and a ninth NMOS transistor, wherein sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the low voltage source, gates of the fifth PMOS transistor and the eighth NMOS transistor are connected to the data signal, drains of the fifth PMOS transistor and the eighth NMOS transistor are connected to gates of the sixth PMOS transistor and the ninth NMOS transistor, and a gate of the sixth NMOS transistor, and sources of the eighth NMOS transistor and the ninth NMOS transistor are connected to the ground terminal.
In a preferred example, the fourth inverter includes a seventh PMOS transistor and a tenth NMOS transistor, wherein a source of the seventh PMOS transistor is connected to the high voltage source, gates of the seventh PMOS transistor and the tenth NMOS transistor are connected to a drain of the third PMOS transistor, a source of the tenth NMOS transistor is connected to the ground, and drains of the seventh PMOS transistor and the tenth NMOS transistor are connected to a source of the second NMOS transistor.
In a preferred embodiment, when the sleep signal is at a high level, the first PMOS transistor and the first NMOS transistor are turned on, and the magnetic tunnel junction is written with a high level; when both the high voltage source and the low voltage source are powered down, the high level of the magnetic tunnel junction is maintained and read.
In a preferred embodiment, when the sleep signal is at a low level, the data signal is converted from a low voltage to a high voltage, the second NMOS transistor is turned on, and the converted signal is read out through an output terminal signal of the fourth inverter; when the low voltage source is powered down, the resistor enables the grid voltage of the second NMOS transistor to be reduced, and the second NMOS transistor is closed.
In a preferred embodiment, the method further comprises the following steps: a readout circuit connected to a drain of the second NMOS transistor.
Compared with the prior art, the method has the following beneficial effects:
according to the traditional low-voltage to high-voltage conversion high-level isolation unit, when an input power supply is powered off, high voltage must be kept to maintain high level, so that certain electric leakage is caused.
The invention selects the magnetic tunnel junction MTJ as a device for storing high level to replace the NAND gate, and the MTJ has the advantages that data is still kept when power is off, and the structure ensures that two groups of power supplies can be powered off, thereby achieving the purpose of reducing electric leakage.
A large number of technical features are described in the specification, and are distributed in various technical solutions, so that the specification is too long if all possible combinations of the technical features (namely, the technical solutions) in the application are listed. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present specification, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
Fig. 1 is a schematic diagram of a low-voltage to high-voltage conversion high-level isolation unit according to an embodiment of the present application.
FIG. 2 is a diagram of a magnetic tunnel junction based voltage transition high level isolation cell according to an embodiment of the present application.
FIG. 3 is a diagram illustrating a magnetic tunnel junction structure according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application discloses a voltage conversion high-level isolation unit based on a magnetic tunnel junction, and fig. 2 shows a structural schematic diagram of the voltage conversion high-level isolation unit based on the magnetic tunnel junction. The voltage conversion high-level isolation unit based on the magnetic tunnel junction comprises: a first inverter 20, a transmission gate 60 and a fourth inverter 50 connected between a high voltage source VDDH and a ground terminal GND, a second inverter 30 and a third inverter 40 connected between a low voltage source VDDL and the ground terminal GND, and a magnetic tunnel junction (MJT) -based high-level isolation unit 10.
In one embodiment, the voltage domain of the high voltage source is higher than the voltage domain of the low voltage source, for example, the voltage range of the high voltage source is 0-3.3V or 5.5V. The voltage range of the low voltage source is 0-1.2V or 1.5V.
The input terminal of the first inverter 20 is connected to the SLEEP signal SLEEP, the input terminal of the second inverter 30 is connected to the DATA signal DATA _ IN, and the output terminal is connected to the input terminal of the third inverter 40. The transmission gate 60 includes a second PMOS transistor P2, a third PMOS transistor P3, and third through sixth NMOS transistors N3-N6. The sources of the second PMOS transistor P2 and the third PMOS transistor P3 are both connected to the high voltage source VDDH, and the gate of the second PMOS transistor P2, the drain of the third PMOS transistor P3, the source of the fourth NMOS transistor N4 are connected to the input of the fourth inverter 50. The gate of the third PMOS transistor P3, the drain of the second PMOS transistor P2, and the source of the third NMOS transistor N3 are connected. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are both connected to the slepb output by the output terminal of the first inverter 20. The drain of the third NMOS transistor N3 is connected to the drain of the fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is connected to the output terminal of the third inverter 40, the drain of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N6 is connected to the input terminal of the third inverter 40;
in one embodiment, the first inverter 20 includes a fourth PMOS transistor P4 and a seventh NMOS transistor N7. Wherein the gates of the fourth PMOS transistor P4 and the seventh NMOS transistor N7 are connected to the SLEEP signal SLEEP, the source of the fourth PMOS transistor P4 is connected to the high voltage source VDDH, the source of the seventh NMOS transistor N7 is connected to the ground terminal GND, and the drains of the fourth PMOS transistor P4 and the seventh NMOS transistor N7 are connected to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4.
In one embodiment, the second inverter 30 includes a fifth PMOS transistor P5 and an eighth NMOS transistor N8, and the third inverter 40 includes a sixth PMOS transistor P6 and a ninth NMOS transistor N9. Wherein sources of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are connected to the low voltage source VDDH, gates of the fifth PMOS transistor P5 and the eighth NMOS transistor N8 are connected to the DATA signal DATA _ IN, drains of the fifth PMOS transistor P5 and the eighth NMOS transistor N8 are connected to gates of the sixth PMOS transistor P6 and the ninth NMOS transistor N9, and a gate of the sixth NMOS transistor N6, and sources of the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are connected to a ground terminal GND.
In one embodiment, the fourth inverter 50 includes a seventh PMOS transistor P7 and a tenth NMOS transistor N10, wherein a source of the seventh PMOS transistor P7 is connected to the high voltage source VDDH, gates of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are connected to a drain of the third PMOS transistor P3, a source of the tenth NMOS transistor N10 is connected to the ground GND, and drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are connected to a source of the second NMOS transistor N2.
With continued reference to fig. 2, the high-level isolation unit 10 includes a first PMOS transistor P1, a first NMOS transistor N1, a second NMOS transistor N2, a fifth inverter 11, a resistor R, and a magnetic tunnel junction 12. The input end of the fifth inverter 11 and the gate of the first NMOS transistor N1 are connected to the SLEEP signal SLEEP, the output end of the fifth inverter 11 is connected to the gate of the first PMOS transistor P2 and the gate of the second NMOS transistor N2, the source of the first PMOS transistor P1 is connected to the high voltage source VDDH, the source of the second NMOS transistor N2 is connected to the output end of the fourth inverter 50, the drain of the first PMOS transistor P1 is connected to the drain of the second NMOS transistor N2, one end of the resistor R is connected to the gate of the second NMOS transistor N2, the other end of the resistor R is connected to the ground GND, one end of the magnetic tunnel junction 12 is connected to the drains of the first PMOS transistor P1 and the second NMOS transistor N2, the other end of the resistor R is connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is connected to the ground.
In one embodiment, the voltage conversion high-level isolation unit further comprises: and a readout circuit 70, wherein the readout circuit 20 is connected to the drain of the second NMOS transistor N2.
In one embodiment, referring to the illustration of FIG. 3, the magnetic tunnel junction 12 includes a free layer 121, a barrier layer 122, and a reference layer 123, the free layer 121 connecting the drain of the first PMOS transistor P1, the reference layer 123 connecting the drain of the first NMOS transistor N1.
The MTJ is mainly composed of a fixed layer, a barrier layer, and a free layer. Both the fixed layer and the free layer are formed of magnetic materials, e.g., CoFeB, CoFe, etc. The barrier layer is generally made of MgO. The fixed layer, also referred to as the reference layer, has its magnetization direction held constant and only the magnetization direction of the free layer is changed to be either in the same direction or in the opposite direction as the reference layer. MTJ devices rely on quantum tunneling effects to pass electrons through a barrier layer. The tunneling effect of the polarized electrons and the fixed layer are related to the relative magnetization direction of the free layer. When the magnetization directions of the fixed layer and the free layer are the same, the tunneling probability of polarized electrons is high, and at this time, a low resistance state (Rp) is represented during the MTJ, and this state is called a parallel state; when the magnetization directions of the fixed layer and the free layer are opposite, the tunneling probability of polarized electrons is low, and the MTJ device shows a high resistance state (Rap), which is called an anti-parallel state. The MTJ device represents a logic state "1" or "0" with Rp and Rap states, thereby realizing storage of data.
MTJ writing is essentially a phenomenon in which a current passes through a barrier layer, and a polarity current interacts with electrons to apply a torque to the magnetic barrier layer tending to be in the same direction as the spin-polarized current, a phenomenon known as spin transfer torque effect (STT effect). When the intensity of the polarization current exceeds a certain threshold value, the magnetic moment of the barrier layer can be reversed. The magnetization direction of the free layer of the MTJ device can be made parallel or antiparallel to the magnetization direction of the reference layer by using the spin transfer torque effect, thereby realizing the write operation.
In one embodiment, when the SLEEP signal SLEEP is high, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on, and the magnetic tunnel junction 12 is written with a high level. When both the high voltage source VDDH and the low voltage source VDDL are powered down, the high level of the magnetic tunnel junction 12 is maintained and read out.
When the SLEEP signal SLEEP is high, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on simultaneously, and the current flows from the free layer of the magnetic tunnel junction 12 through the reference layer, the magnetic tunnel junction 12 is turned to a parallel state, and a high level 1 is written into the magnetic tunnel junction. After both voltage sources VDDL and VDDH are powered down, the signal of the magnetic tunnel junction can be maintained and read by an external sensing circuit, thereby achieving the effect of isolating latch 1.
IN one embodiment, when the SLEEP signal SLEEP is at a low level, the DATA signal DATA _ IN is converted from a low voltage to a high voltage, the second NMOS transistor N2 is turned on, and the converted signal is read out through the output terminal signal of the fourth inverter 50. When the low voltage source VDDL is powered down, the resistor R causes the gate voltage of the second NMOS transistor N2 to drop, and the second NMOS transistor N2 is turned off.
When the SLEEP signal SLEEP is low, the voltage conversion circuit converts the input DATA signal DATA _ IN from low voltage VDDL to high voltage VDDH, the second NMOS transistor N2 is turned on, the converted DATA signal is output to DATA _ OUT through the second NMOS transistor N2, and when the low voltage VDDL is powered down, the pull-down resistor R pulls the gate of the second NMOS transistor N2 to 0, turning off the second NMOS transistor N2.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of this specification so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (6)
1. A magnetic tunnel junction based voltage translation high level isolation cell, comprising: the high-level isolation circuit comprises a first inverter, a transmission gate, a fourth inverter, a second inverter, a third inverter and a high-level isolation unit, wherein the first inverter, the transmission gate and the fourth inverter are connected between a high-voltage source and a ground terminal;
wherein the input end of the first inverter is connected with a sleep signal, the input end of the second inverter is connected with a data signal, the output end of the first inverter is connected with the input end of the third inverter, the transmission gate comprises a second PMOS transistor and a third PMOS transistor, and a third NMOS transistor to a sixth NMOS transistor, the sources of the second PMOS transistor and the third PMOS transistor are both connected with the high voltage source, the grid of the second PMOS transistor, the drain of the third PMOS transistor, the source of the fourth NMOS transistor are connected with the input end of the fourth inverter, the grid of the third PMOS transistor, the drain of the second PMOS transistor are connected with the source of the third NMOS transistor, the grids of the third NMOS transistor and the fourth NMOS transistor are connected with the output end of the first inverter, the drain of the third NMOS transistor is connected with the drain of the fifth NMOS transistor, and the grid of the fifth NMOS transistor is connected with the output end of the third inverter, the drain electrode of the fourth NMOS transistor is connected with the drain electrode of the sixth NMOS transistor, and the grid electrode of the sixth NMOS transistor is connected with the input end of the third inverter;
wherein the magnetic tunnel junction-based high-level isolation unit comprises a first PMOS transistor, first and second NMOS transistors, a fifth inverter, a resistor and a magnetic tunnel junction, wherein the input end of the fifth inverter and the gate of the first NMOS transistor are connected with the sleep signal, the output end of the fifth inverter is connected with the gate of the first PMOS transistor and the gate of the second NMOS transistor, the source of the first PMOS transistor is connected with the high-voltage source, the source of the second NMOS transistor is connected with the output end of the fourth inverter, the drain of the first PMOS transistor is connected with the drain of the second NMOS transistor, one end of the resistor is connected with the gate of the second NMOS transistor, the other end of the resistor is connected with the ground, one end of the magnetic tunnel junction is connected with the drains of the first PMOS transistor and the second NMOS transistor, the drain electrode of the first NMOS transistor is arranged at the other end, and the source electrode of the first NMOS transistor is connected with the ground end;
when the sleep signal is at a high level, the first PMOS transistor and the first NMOS transistor are conducted, and the magnetic tunnel junction is written into the high level; when the high voltage source and the low voltage source are both powered down, the high level of the magnetic tunnel junction is maintained and read out; when the sleep signal is at a low level, the data signal is converted from a low voltage to a high voltage, the second NMOS transistor is turned on, and the converted signal is read out through an output end signal of the fourth inverter; when the low voltage source is powered down, the resistor enables the grid voltage of the second NMOS transistor to be reduced, and the second NMOS transistor is closed.
2. The magnetic tunnel junction based voltage-switching high-level isolation cell of claim 1, wherein the magnetic tunnel junction comprises a free layer, a barrier layer, and a reference layer, the free layer connecting the drain of the first PMOS transistor, the reference layer connecting the drain of the first NMOS transistor.
3. The magnetic tunnel junction based voltage-converting high-level isolation cell of claim 1, wherein the first inverter comprises a fourth PMOS transistor and a seventh NMOS transistor, wherein gates of the fourth PMOS transistor and the seventh NMOS transistor are connected to the sleep signal, a source of the fourth PMOS transistor is connected to the high voltage source, a source of the seventh NMOS transistor is connected to the ground, and drains of the fourth PMOS transistor and the seventh NMOS transistor are connected to gates of the third and fourth NMOS transistors.
4. The magnetic tunnel junction based voltage-converting high-level isolation cell of claim 1, wherein the second inverter comprises a fifth PMOS transistor and an eighth NMOS transistor, and the third inverter comprises a sixth PMOS transistor and a ninth NMOS transistor, wherein the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the low voltage source, the gates of the fifth PMOS transistor and the eighth NMOS transistor are connected to the data signal, the drains of the fifth PMOS transistor and the eighth NMOS transistor are connected to the gates of the sixth PMOS transistor and the ninth NMOS transistor, and the gate of the sixth NMOS transistor, and the sources of the eighth NMOS transistor and the ninth NMOS transistor are connected to ground.
5. The magnetic tunnel junction based voltage-converting high-level isolation cell of claim 1, wherein the fourth inverter comprises a seventh PMOS transistor and a tenth NMOS transistor, wherein the source of the seventh PMOS transistor is connected to the high voltage source, the gates of the seventh PMOS transistor and the tenth NMOS transistor are connected to the drain of the third PMOS transistor, the source of the tenth NMOS transistor is connected to the ground, and the drains of the seventh PMOS transistor and the tenth NMOS transistor are connected to the source of the second NMOS transistor.
6. The magnetic tunnel junction-based voltage-switching high-level isolation cell of claim 1, further comprising: a readout circuit connected to a drain of the second NMOS transistor.
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| US5541546A (en) * | 1994-02-18 | 1996-07-30 | Nec Corporation | Signal level conversion circuit for converting a level of an input voltage into a larger level |
| CN108055033A (en) * | 2018-01-09 | 2018-05-18 | 上海顺久电子科技有限公司 | Level shifting circuit, IC chip and electronic equipment |
| WO2020147306A1 (en) * | 2019-01-17 | 2020-07-23 | 南京观海微电子有限公司 | Withstand voltage level conversion circuit |
| CN110752843A (en) * | 2019-11-26 | 2020-02-04 | 上海华力微电子有限公司 | Level conversion circuit |
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