CN113114194A

CN113114194A - Gate drive circuit of gallium nitride power device

Info

Publication number: CN113114194A
Application number: CN202110281925.8A
Authority: CN
Inventors: 张允武; 陆扬扬
Original assignee: State Silicon Integrated Circuit Technology Wuxi Co ltd
Current assignee: State Silicon Integrated Circuit Technology Wuxi Co ltd
Priority date: 2021-03-16
Filing date: 2021-03-16
Publication date: 2021-07-13

Abstract

The application discloses gallium nitride power device gate drive circuit belongs to high-voltage power integrated circuit technical field. The circuit comprises: the circuit comprises a narrow pulse generating circuit, a high-voltage level shifting circuit, a dynamic asymmetric state generating circuit, common mode shielding logic, an RS trigger and a buffer stage which are connected in sequence; the high-voltage level shift circuit also comprises a latch, the dynamic asymmetric state generating circuit is used for dynamically changing the balance point of the latch during the transient of the power supply voltage, and the latch is shifted to an upper stable state when the balance point is changed so as to control the output signal of the gate driving circuit of the gallium nitride power device to be kept unchanged. The anti-noise interference capability of the chip can be improved while the transmission delay is reduced.

Description

Gate drive circuit of gallium nitride power device

Technical Field

The embodiment of the application relates to the technical field of high-voltage power integrated circuits, in particular to a gate driving circuit of a gallium nitride power device.

Background

In a Buck-type DC (Direct Current) -DC converter, two series-connected power devices are generally used to be connected between an input high voltage and ground. Since N-type power devices have lower on-resistance and smaller parasitic capacitance than P-type power devices, two N-type power devices are generally used in high voltage applications above 300V to 600V, as shown in fig. 1, M_HIs a high-side switching device, M, in the above DC-DC converter_LIs a low side switching device in the DC-DC converter described above. Floating gate driver chips are typically used for efficient drivingHigh-side switching device M_HThe floating gate driving chip comprises low-voltage input logic, a high-voltage area gate driving circuit and a low-voltage area gate driving circuit, LIN is an input signal of a low-side channel, HIN is an input signal of a high-side channel, both LIN and HIN are connected to the low-voltage input logic, the low-voltage input logic outputs two signals of IN _ L and IN _ H, wherein IN _ L is output to the low-voltage area gate driving circuit, and IN _ H is output to the high-voltage area gate driving circuit. LO is the output signal of the low-side channel, connected to M_LHO is the output signal of the high-side channel, connected to M_HA gate electrode of (1). VCC-to-GND voltage domain supplies power to the low voltage region circuit, VB-to-VS floating voltage domain supplies power to the high voltage region circuit, and VS terminal is connected to M_HSource and M_LOf the substrate. Using bootstrap diodes D_BAnd a bootstrap capacitor C_BSupply power to VB, when M_LWhen turned on, VCC passes through D_BIs a bootstrap capacitor C_BCharging and supplying power for the high-voltage area gate driving circuit; when M is_HAt turn-on, bootstrap capacitor C_BAnd the task of supplying power to the high-voltage area gate driving circuit is carried out, and the steps are repeated. An inductor L with one end connected to the VS end and the other end connected to the output voltage Vout, a capacitor C and a resistor R₀And one end of the parallel connection is connected to Vout, and the other end is connected to GND. In the high-voltage floating gate driving chip, it is necessary to transmit the low-voltage domain signal from VCC to GND to the high-voltage domain between VB to VS, and therefore a high-voltage level shift circuit is needed to achieve the above purpose.

The level shift circuit shown in fig. 2 includes an N type Laterally Diffused Metal Oxide Semiconductor (NLDMOS) N_LD1Zener diode D₁Resistance R₁And an NMOS (N-Metal-Oxide-Semiconductor) tube M₂And a PMOS (P-Metal-Oxide-Semiconductor) tube M₁Zener diode D1 is used to clamp the voltage at E so that the voltage at E is not too much lower than VS, and N is_LD1The grid of the grid is connected with an input signal, the source is grounded, the drain is connected with D₁Positive electrode of (2), R₁And M₁And M₂Are commonly connected to point E, D₁Negative electrode of (1), M₁Source and R of₁Is connected to and is connected to VB, M₁And M₂Is connected to the output port, M₂Is connected to the floating ground VS terminal. D₁Has the function of ensuring M₁And M₂Is not broken down. When the level shift circuit is turned on, N is enabled_LD1The long-time conduction has extremely high requirement on the reliability of the integrated high-voltage transverse field effect transistor, and the maximum working voltage of the chip is limited while the maximum power consumption is caused.

In order to solve the above problem, a level shift circuit using a two-way LDMOS may be designed, as shown in fig. 3, which includes a pulse generation circuit, a two-way level shift circuit, an RS flip-flop, and a buffer stage. Wherein the level shift circuit is LDMOS N_LD2、N_LD3Resistance R₂、R₃And a diode D₂And D₃The RS flip-flop is composed of two NAND gates NAND₁And NAND₂And (4) forming. The input signal is connected to the input of a pulse generating circuit which outputs two narrow pulse signals, SET and Reset, SET acts on N_LD2Is applied to N_LD3A gate electrode of (1). N is a radical of_LD2And N_LD3Source of (2) is connected to GND, N_LD2Drain electrode of (1) and resistor R₂One end of (A) is connected to point A, N_LD3Drain electrode of (1) and resistor R₃One end of which is connected to point B and resistor R₂And R₃Is connected to terminal VB, diode D₂And D₃Is connected to the VS point, D₂Is connected to point B, D₃Is linked to point a. NAND in RS flip-flop₁One input terminal of the first and second transistors is connected to the point A, and the other input terminal is connected to the NAND₂Output terminal of, NAND₂One input terminal of the first and second transistors is connected to the point B, and the other input terminal is connected to the NAND₁Output terminal of, NAND₁Is connected to the input of the buffer stage, i.e. the output port of the high-side channel. The RS flip-flop and the buffer stage are both connected between the high-side power supply VB and the low-side power supply VS. The pulse generating circuit respectively outputs rising and falling edges of the input signalConverted into two paths of narrow pulse signals, and the N-type LDMOS N is shortened_LD2And N_LD3The on-time greatly reduces the power consumption of the chip and simultaneously promotes the maximum working voltage of the chip. The RS flip-flop restores the narrow pulse signal of A, B two points to a wide pulse signal to the output port. Diode D₂And D₃The function of the protection circuit is to clamp A, B two-point voltage and protect the grid of the post-stage circuit. In fig. 4, a waveform diagram of the circuit shown in fig. 3 interfered by dV/dt transient noise signals is shown, when the voltage at the VS terminal rises sharply, a displacement current flows through two level shift branches, and a voltage drop is formed on a resistor, and the voltage drop makes the voltages at A, B two points lower than the response threshold of the RS flip-flop, and the RS flip-flop enters an indefinite state due to the same zero signal, which affects the normal output of the chip. For this reason, on the basis of fig. 3, RC filter circuits may be inserted between the input terminal of the RS flip-flop and point A, B, respectively, to solve this problem, as shown in fig. 5.

In the face of the rise of the current third generation power semiconductors, gallium nitride power devices and the like have made higher requirements on the transmission speed and the anti-interference capability of the floating gate driving chip, and therefore a high-voltage level shift circuit with strong anti-interference capability and high transmission speed is desired. As shown in fig. 6, a level shift circuit using a digital common mode protection circuit is proposed in the prior art, which includes a pulse generation circuit, a two-way level shift circuit, a protection circuit, an RS flip-flop and a buffer stage, wherein the level shift circuit is an LDMOS N_LD6、N_LD7Resistance R₆、R₇And a diode D₆And D₇The RS flip-flop is composed of two NAND gates NAND₁And NAND₂The protection circuit is composed of INV₁To INV₇、NAND₅、NAND₆And NOR₁And (4) forming. The input signal is connected to the input end of a pulse generating circuit, the pulse generating circuit outputs two narrow pulse signals of SET and Reset, the SET acts on NLD₆Acting on NLD₇A gate electrode of (1). NLD₆And NLD₇Is connected to GND, NLD₆Drain electrode of (1) and resistor R₆Is connected at one end to A₂Dot, NLD₇Drain electrode of (1) and resistor R₇One end of is connected to B₂Point, resistance R₆And R₇Is connected to terminal VB, diode D₆And D₇Is connected to the VS point, D₆Negative electrode and INV₁Is connected to B₂Dot, D₇Negative electrode and INV₄Is connected to A₂And (4) point. INV₁Is connected with INV₂Input end of INV₄Is connected with INV₅Input end of INV₂Output ends of the first and second transistors are respectively connected to INV₃And NOR₁An input terminal of INV₅Output ends of the first and second transistors are respectively connected to INV₆And NOR₁To the other input terminal, NOR₁Is connected to INV₇Input terminal of, NAND₅And NAND₆Is connected to the INV₇Output terminal of, NAND₅Another input end of the input end is connected to the INV₃Output terminal of, NAND₆Another input end of the input end is connected to the INV₆To the output terminal of (a). NAND₅And NAND₇Is connected to R_e1Dot, NAND₆And NAND₈Is connected to S_e1And (4) point. NAND₇Is connected to the NAND₈Output terminal of, NAND₈Is connected to the NAND₇Output terminal of, NAND₈Is connected to the input of the buffer stage, i.e. the output port of the high-side channel. And the power supply ends of the protection circuit, the RS trigger and the buffer stage are all connected with VB, and the ground end is all connected with VS. When dV/dt transient noise signal generates displacement current in high-voltage level shift branch circuit to cause A₂And B₂When the terminals are at logic low level simultaneously, the protection circuit can well eliminate the influence of common mode dV/dt noise on the level shift circuit, but the high matching of layout and process is required, and when the loads are not matched (NLD)₆And R₆The parasitics of the branches are large), the waveform of the effect of the dV/dt transient noise signal on the circuit shown in fig. 6 is shown in fig. 7. When at VSWhen the voltage changes instantaneously, A is caused by parasitic mismatch₂The voltage drop speed of the point is faster than that of B₂Point, and A after VS signal transient₂The voltage recovery speed of the point is obviously slower than that of B₂The voltage recovery speed of the point, therefore, at t₁To t₂Time t and₃to t₄At any moment, the common mode protection circuit cannot finish the identification of the common mode signal, and the signal is released to the position end of the RS trigger by mistake, so that the RS trigger is opened by mistake. Also, when NLD₇And R₇When the parasitics of the branches are larger, the dV/dt transient noise signal also causes the signal of the error turn-off output from the high-voltage side, which seriously affects the normal operation of the chip. Therefore, although the level shift circuit adopting the digital common mode protection circuit can remove the RC filter circuit in the traditional level shift circuit scheme, the level shift circuit does not have good interference resistance.

Disclosure of Invention

The embodiment of the application provides a gate driving circuit of a gallium nitride power device, which is used for solving the problem that a level shift circuit adopting a digital common mode protection circuit does not have good anti-interference capability. The technical scheme is as follows:

in one aspect, a gate driving circuit of a gallium nitride power device is provided, which includes: the circuit comprises a narrow pulse generating circuit, a high-voltage level shifting circuit, a dynamic asymmetric state generating circuit, common mode shielding logic, an RS trigger and a buffer stage;

the input end of the narrow pulse generating circuit is used as the input end of the gallium nitride power device gate driving circuit, the first output end of the narrow pulse generating circuit is connected with the first input end of the high-voltage level shifting circuit, the second output end of the narrow pulse generating circuit is connected with the second input end of the high-voltage level shifting circuit, the power supply end of the narrow pulse generating circuit is connected with a low-voltage side power supply, and the logic ground end of the narrow pulse generating circuit is connected with the chip ground; a first output end of the high-voltage level shift circuit is respectively connected with a first output end of the dynamic asymmetric state generation circuit and a first input end of the common mode shielding logic, and a second output end of the high-voltage level shift circuit is respectively connected with a second output end of the dynamic asymmetric state generation circuit and a second input end of the common mode shielding logic; a first output end of the common mode shielding logic is connected with a reset input end of the RS trigger, and a second output end of the common mode shielding logic is connected with a set input end of the RS trigger; the in-phase output end of the RS trigger is respectively connected with the input end of the buffer stage and the first input end of the dynamic asymmetric state generating circuit; the reverse phase output end of the RS trigger is connected with the second input end of the dynamic asymmetric state generating circuit; the output end of the buffer stage is used as the output end of the gallium nitride power device gate drive circuit; the power ends of the common mode shielding logic, the RS trigger and the buffer stage are respectively connected with a high-voltage side power supply, and the logic grounds of the common mode shielding logic, the RS trigger and the buffer stage are respectively connected with a high-voltage area in a floating mode;

the high-voltage level shift circuit also comprises a latch, the dynamic asymmetric state generating circuit is used for dynamically changing the balance point of the latch during the transient of the power supply voltage, and the latch is shifted to an upper stable state when the balance point is changed so as to control the output signal of the gate driving circuit of the gallium nitride power device to be kept unchanged.

In one possible implementation, the high voltage level shifting circuit includes: the latch comprises a first switch, a second switch, a first diode, a second diode and a latch, wherein the latch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube;

the grid electrode of the first switch is used as a first input end of the high-voltage level shifting circuit, and the grid electrode of the second switch is used as a second input end of the high-voltage level shifting circuit; the source electrode and the substrate of the first switch and the second switch are grounded; the drain electrode of the first switch, the cathode of the second diode, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are interconnected and then serve as a first output end of the high-voltage level shift circuit; the drain electrode of the second switch, the cathode of the first diode, the drain electrode of the second PMOS tube and the grid electrode of the first PMOS tube are interconnected and then serve as a second output end of the high-voltage level shift circuit; the source electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the high-voltage side power supply; anodes of the first diode and the second diode are respectively connected with the high-voltage area in a floating mode.

In one possible implementation, the dynamic asymmetric state generating circuit includes: the first NMOS tube and the second NMOS tube;

the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the high-voltage area in a floating mode after being interconnected; the drain electrode of the first NMOS tube is used as a first output end of the dynamic asymmetric state generating circuit; the drain electrode of the second NMOS tube is used as a second output end of the dynamic asymmetric state generating circuit; the grid electrode of the first NMOS tube is used as a first input end of the dynamic asymmetric state generating circuit; and the grid electrode of the second NMOS tube is used as a second input end of the dynamic asymmetric state generating circuit.

In one possible implementation, the common mode mask logic includes: the first inverter, the second inverter, the first NAND gate, the second NAND gate and the third NAND gate;

the input end of the first inverter is used as the second input end of the common mode shielding logic, and the input end of the second inverter is used as the first input end of the common mode shielding logic; the output end of the first inverter is respectively connected with the first input end of the first NAND gate and the first input end of the second NAND gate; the output end of the second inverter is respectively connected with the second input end of the first NAND gate and the first input end of the third NAND gate; the output end of the first NAND gate is respectively connected with the second input end of the second NAND gate and the second input end of the third NAND gate; the output end of the second nand gate is used as the first output end of the common mode shielding logic, and the output end of the third nand gate is used as the second output end of the common mode shielding logic.

In one possible implementation, the RS flip-flop includes: a fourth NAND gate and a fifth NAND gate;

a first input end of the fourth nand gate is used as a reset input end of the RS flip-flop, and a first input end of the fifth nand gate is used as a set input end of the RS flip-flop; a second input end of the fourth NAND gate and an output end of the fifth NAND gate are interconnected and then serve as a non-inverting output end of the RS trigger; and a second input end of the fifth NAND gate and an output end of the fourth NAND gate are interconnected and then serve as an inverted output end of the RS trigger.

In one possible implementation, the gallium nitride power device gate driving circuit further includes a preamplifier;

a first output end of the high-voltage level shift circuit is respectively connected with a first output end of the dynamic asymmetric state generating circuit and a first input end of the preamplifier, and a second output end of the high-voltage level shift circuit is respectively connected with a second output end of the dynamic asymmetric state generating circuit and a second input end of the preamplifier; a first output of the preamplifier is connected to a first input of the common mode mask logic; a second output of the preamplifier is connected to a second input of the common mode shield logic.

In one possible implementation, the preamplifier includes: the circuit comprises a first P-type switch, a second P-type switch, a first resistor and a second resistor;

the grid electrode of the first P-type switch is used as a first input end of the preamplifier, and the grid electrode of the second P-type switch is used as a second input end of the preamplifier; the drain electrode of the first P-type switch and the first end of the first resistor are interconnected to be used as a first output end of the preamplifier; the drain electrode of the second P-type switch and the first end of the second resistor are interconnected and then used as a second output end of the preamplifier; the second end of the first resistor and the second end of the second resistor are connected with the high-voltage area in a floating mode after being interconnected; and the source electrode of the first P-type switch and the source electrode of the second P-type switch are connected with the high-voltage side power supply after being interconnected.

In one possible implementation, the dynamic asymmetric state generating circuit includes: the third NMOS tube, the fourth NMOS tube, the third resistor and the fourth resistor;

the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected with the high-voltage area in a floating mode after being interconnected; a first end of the third resistor is connected with a drain electrode of the third NMOS tube, and a second end of the third resistor is used as a first output end of the dynamic asymmetric state generating circuit; a first end of the fourth resistor is connected with a drain electrode of the fourth NMOS tube, and a second end of the fourth resistor is used as a second output end of the dynamic asymmetric state generating circuit; the grid electrode of the third NMOS tube is used as a first input end of the dynamic asymmetric state generating circuit; and the grid electrode of the fourth NMOS tube is used as a second input end of the dynamic asymmetric state generating circuit.

In one possible implementation, the common mode mask logic includes: a sixth nand gate, a seventh nand gate and an eighth nand gate;

a first input end of the sixth nand gate and a first input end of the seventh nand gate are interconnected and then serve as a second input end of the common mode shielding logic; a second input end of the sixth nand gate is interconnected with a first input end of the eighth nand gate and then serves as a first input end of the common mode shielding logic; the output end of the sixth nand gate is connected with the second input end of the seventh nand gate and the second input end of the eighth nand gate respectively; the output end of the seventh nand gate is used as the first output end of the common mode shielding logic, and the output end of the eighth nand gate is used as the second output end of the common mode shielding logic.

In a possible implementation manner, the current capacities of the first NMOS transistor and the second NMOS transistor are lower than the current capacities of the first PMOS transistor and the second PMOS transistor in the latch.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

1. the anti-noise interference capability of the chip is improved while the transmission delay is reduced, and the high-voltage floating gate driving chip is not only suitable for a traditional high-voltage floating gate driving chip, but also suitable for a driving chip of a third-generation semiconductor power device.

2. The static power consumption is small, and the structure basically has no static power consumption except for a switching process.

3. The negative pressure working capacity of the floating ground is improved.

4. Simple structure avoids bringing extra cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a DC-DC power supply topology structure employing a high voltage floating gate driver chip;

FIG. 2 is a schematic diagram of a prior art high voltage level shift circuit employing a single-way LDMOS;

FIG. 3 is a schematic diagram of a prior art high voltage level shifting circuit employing a dual-path LDMOS;

FIG. 4 is a waveform of the effect of dV/dt transient noise on a high voltage level shifting circuit employing a dual path LDMOS;

FIG. 5 is a schematic diagram of a noise filtering circuit added to a high voltage level shifter circuit using a dual-path LDMOS;

FIG. 6 is a diagram of a prior art level shift circuit using a digital common mode protection circuit;

FIG. 7 is a waveform diagram showing the response of dV/dt transient noise to a level shift circuit using a digital common mode protection circuit when the load is not matched;

fig. 8 is a schematic diagram of a gate driving circuit of a first gan power device proposed in the present application;

FIG. 9 is a schematic diagram of a basic operation model of a first gallium nitride power device gate driving circuit;

FIG. 10 is a diagram of an operation model of a latch in the circuit proposed in the present application;

FIG. 11 is a schematic diagram of waveforms affected by dV/dt transient noise when the output of the gate driving circuit of the GaN power device is at a low level;

FIG. 12 is a schematic diagram of waveforms affected by dV/dt transient noise when the output of the gate driving circuit of the GaN power device is at a high level;

fig. 13 is a schematic diagram of a gate driving circuit of a second gan power device proposed in the present application.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.

Referring to fig. 8, a flow chart of a structure of a gate driving circuit of a gan power device according to an embodiment of the present application is shown. The gate driving circuit of the gallium nitride power device can comprise: a narrow pulse generation circuit 810, a high voltage level shift circuit 820, a dynamic asymmetric state generation circuit 830, common mode shield logic 840, an RS flip-flop 850, and a buffer stage 860.

As shown IN fig. 8, an input terminal of the narrow pulse generating circuit 810 is used as an input terminal IN _ H of the gate driving circuit of the gan power device, a first output terminal SET of the narrow pulse generating circuit 810 is connected to a first input terminal of the high voltage level shifting circuit 820, a second output terminal RESET of the narrow pulse generating circuit 810 is connected to a second input terminal of the high voltage level shifting circuit 820, a power supply terminal of the narrow pulse generating circuit 810 is connected to the low voltage side power supply VCC, and a logic ground terminal of the narrow pulse generating circuit 810 is connected to the chip ground; first output terminal A of high voltage level shift circuit 820₃A second output terminal B of the high voltage level shift circuit 820 connected to the first output terminal of the dynamic asymmetric state generator 830 and the first input terminal of the common mode mask logic 840₃Respectively coupled to a second output of the dynamic asymmetric state generator circuit 830 and a second input of the common mode mask logic 840; a first output terminal of the common mode shielding logic 840 and a reset input terminal R of the RS flip-flop 850_E2A second output terminal of the common mode shielding logic 840 is connected to a set input terminal S of the RS flip-flop 850_E2Connecting; the non-inverting output terminal Q of the RS flip-flop 850 is connected to the input terminal of the buffer stage 860 and the first input terminal of the dynamic asymmetric state generating circuitConnecting; an inverted output end QB of the RS flip-flop 850 is connected with a second input end of the dynamic asymmetric state generating circuit; the output end of the buffer stage is used as the output end HO of the gate drive circuit of the gallium nitride power device; the power supply ends of the common mode shielding logic 840, the RS trigger 850 and the buffer stage 860 are respectively connected with a high-voltage side power supply VB, and the logic grounds of the common mode shielding logic 840, the RS trigger 850 and the buffer stage 860 are respectively connected with a high-voltage region floating ground VS; the high voltage level shift circuit 820 further comprises a latch, and the dynamic asymmetric state generating circuit 830 is configured to dynamically change an equilibrium point of the latch during a transient of the power supply voltage, and the latch shifts to an upper stable state when the equilibrium point changes, so as to control the output signal of the gate driving circuit of the gan power device to remain unchanged.

The circuit structures of the high voltage level shifting circuit 820, the dynamic asymmetric state generating circuit 830, the common mode shielding logic 840 and the RS flip-flop 850 are described below.

1) A high voltage level shifting circuit 820;

the high voltage level shifting circuit 820 may include: first switch N_LD10A second switch N_LD11A first diode D₁₁A second diode D₁₂And a latch including a first PMOS transistor P₁And a second PMOS transistor P₂. Wherein, the first switch N_LD10A gate of the high voltage level shift circuit 820 is connected to the SET as a first input terminal, and a second switch N_LD11The gate of which is connected to RESET as the second input of the high voltage level shift circuit 820; first switch N_LD10And a second switch N_LD11The source and the substrate of (1) are both grounded GND; first switch N_LD10Drain electrode of the first diode D₁₂Negative electrode of (1), first PMOS tube P₁Drain electrode of and a second PMOS transistor P₂As the first output terminal a of the high voltage level shift circuit 820 after being interconnected₃(ii) a Second switch N_LD11Drain electrode of (1), first diode D₁₁Negative electrode of (1), second PMOS tube P₂Drain electrode of and the first PMOS transistor P₁As a second output terminal B of the high voltage level shift circuit 820₃(ii) a First PMOS tube P₁And a second PMOS transistor P₂Source electrode ofAre respectively connected with a high-voltage side power supply VB; first diode D₁₁And a second diode D₁₂Are respectively connected to the high voltage region floating ground VS.

The first point to be noted is that the first switch and the second switch may be NLDMOS devices, LDMOS devices, or other power devices, such as IGBTs, JFETs, etc.

The second point to be noted is that the first diode and the second diode may be diodes, or may be base-emitter diodes of a triode or body diodes of a MOS transistor, and their functions are to clamp a₃And B₃The voltage of the point can also adopt a Zener diode to be connected in parallel with the first PMOS tube P₁And a second PMOS transistor P₂The source and drain ends.

The third point to be noted is that the first PMOS tube P₁And a second PMOS transistor P₂The width-to-length ratios of (A) and (B) may be uniform or nonuniform.

2) A dynamic asymmetric state generation circuit 830;

the dynamic asymmetric state generating circuit 830 may include: first NMOS transistor N₃And a second NMOS transistor N₄. Wherein, the first NMOS transistor N₃Source electrode and second NMOS transistor N₄Is connected with the floating ground VS of the high-voltage area after being interconnected; first NMOS transistor N₃As the first output terminal of the dynamic asymmetric state generating circuit 830 and A₃Connecting; second NMOS transistor N₄As the second output terminal of the dynamic asymmetric state generating circuit 830 and B₃Connecting; first NMOS transistor N₃The gate of which is connected to Q as a first input of the dynamic asymmetric state generating circuit 830; second NMOS transistor N₄Is coupled to QB as a second input of the dynamic asymmetric state generating circuit 830.

It should be noted that the latch may be a latch formed by PMOS transistors, or may be another latch for turning on devices with negative gate-source voltage or negative base-emitter voltage, as long as the first NMOS transistor N is ensured₃And a second NMOS transistor N₄Has much lower current capability than the first PMOS transistor P in the latch₁And a second PMOS transistor P₂The current capability of (2).

3) Common mode mask logic 840;

common mode shield logic 840 may include: first inverter INV₇A second inverter INV₈A first NAND gate NAND₉A second NAND gate NAND₁₀And a third NAND gate NAND₁₁. Wherein, the first inverter INV₇As a second input of common mode shield logic 840 and B₃Connected, second inverter INV₈As the first input of common mode mask logic 840 and a₃Connecting; first inverter INV₇Respectively with the first NAND gate₉And a second NAND gate NAND₁₀Is connected with the first input end of the first input end; second inverter INV₈Respectively with the first NAND gate₉And a third NAND gate NAND₁₀Is connected with the first input end of the first input end; first NAND gate NAND₉Respectively with the second NAND gate₁₀And a third NAND gate NAND₁₁Is connected with the second input end; second NAND gate NAND₁₀As the first output of the common mode mask logic 840 and R_E2Connected, a third NAND gate NAND₁₁As a second output of the common mode mask logic 840 and S_E2Are connected.

4) An RS flip-flop 850;

the RS flip-flop 850 may include: the fourth NAND gate NAND₁₂And a fifth NAND gate NAND₁₃. Wherein the fourth NAND gate NAND₁₂As the reset input R of the RS flip-flop 850_E2The fifth NAND gate NAND₁₃As the set input S of the RS flip-flop 850_E2(ii) a The fourth NAND gate NAND₁₂Second input terminal and fifth NAND gate NAND₁₃The output terminals of which are interconnected to serve as the in-phase output terminal Q of the RS flip-flop 850; the fifth NAND gate NAND₁₃Second input terminal and fourth NAND gate NAND₁₂And is interconnected to serve as the inverting output QB of the RS flip-flop 850.

Following nitridation as shown in FIG. 8The working flow of the gate driving circuit of the gallium power device is introduced. Referring to fig. 9, the input signal IN _ H is a wider pulse signal, and IN order to reduce the conduction loss and the reliability requirement of the high voltage switch device, the rising edge and the falling edge of IN _ H are respectively converted into two narrow pulse signals, i.e. SET and RESET, by the narrow pulse generating circuit 810, and N is driven by SET_LD10Driving N with RESET_LD11. Assuming that the initial state is determined by undervoltage and power-on reset circuits together, the initial state of the RS trigger is determined so that HO is low level, P₂And N₃Off, P₁And N₄Opening, A₃The initial state is logic high, B₃The initial state is a logic low level. At t₁Time of day, SET signal is active, N_LD10Is turned on so that A₃Becomes a logic low level, resulting in P₂Is turned on and P₁Off, B₃Becomes a logic high level, and passes through the common mode shielding circuit 840, S_E2Becomes a logic low level and R_E2Becomes a logic high level, so that the in-phase output end Q of the RS trigger outputs 850 a high level signal, and the output signals of the two output ends of the RS trigger 850 are fed back to N₃And N₄So that N is₃Is turned on and N₄And (6) turning off. At t₂After the moment, the SET signal is no longer active, under the control of the feedback signal, A₃Continues to maintain a logic low level, and B₃Continues to remain at a logic high level. At t₃Time, RESET signal active, N_LD11Is turned on so that B₃Becomes a logic low level, resulting in P₁Is turned on and P₂Off, A₃Becomes a logic high level, and passes through the common mode shielding circuit 840, S_E2Becomes a logic high level and R_E2Becomes a logic low level, so that the non-inverting output terminal Q of the RS flip-flop 850 outputs a low level signal, and the output signals of the two output terminals of the RS flip-flop 850 are fed back to N₃And N₄So that N is₃Off and N₄And (4) opening. After time t4, the RESET signal is no longer active, and A is controlled by the feedback signal₃Continues to maintain a logic high level, and B₃Continues to remain at a logic low level.

When a dV/dt transient noise signal is applied to VS and VB, A₃And B₃The voltage of the node is slightly behind the rising speed of VB, so that P₁And P₂Are simultaneously conducted to be A₃And B₃Providing a displacement current, the latch will cause A₃And B₃The voltage of (2) rises rapidly. When the dV/dt speed is too high, the displacement current still passes through D₁₁And D₁₂So that A is₃And B₃Appears logic low with respect to the VS terminal, and this state is masked by the common mode mask logic 840. But now the fully symmetric latch is in its non-steady state, as shown by the position of the filled circles in fig. 10, after a transient for VS and VB, the latch cannot determine whether to transition towards a state with an output high or a state with an output low, at N₃And N₄Under the action of (B), P₁And P₂The latch structure is constructed to exhibit an asymmetrical state, referred to herein as an asymmetrical latch, i.e., when the initial state of the output is high, the state of the asymmetrical latch during the dV/dt period is shown as the five-pointed star position in fig. 10, and when dV/dt has elapsed, the state of the latch must return to the output high state. Similarly, when the initial state of the output is low, the state of the asymmetric latch is as described in the triangle position of fig. 10, and after dV/dt has passed, the state of the latch will necessarily return to the low state of the output. The asymmetric latch eliminates A from the source₃And B₃The problem that the differential mode noise at the common mode stage is difficult to filter due to the fact that parasitic parameters of the nodes are not matched is solved, and an additional RC (Resistor-capacitor) filter circuit is not needed, so that the transient noise interference resistance of the chip is greatly improved on the basis of reducing channel transmission delay.

FIG. 11 shows a simulated waveform diagram of the gate driver circuit of a GaN power device under the influence of dV/dt transient noise when the output is at low level, and it can be seen from FIG. 11 that, in the initial state, the reset input of the RS flip-flop 850 is at logic low level and the set input is at logic low levelHigh level is edited; during dV/dt transient noise, A₃And B₃The same zero signal is filtered out after passing through the common mode cancellation logic 840, and then the state of the latch is gradually restored. Due to the same zero time period P₁And P₂On at the same time, so there is a small co-rising process following the dV/dt transient noise, followed by B₃Gradually decreases to VS (logic low level) and A₃Gradually rises to VB (logic high level). In this process, the input state of the RS flip-flop 850 is always unaffected, and therefore, the output remains at a logic low level.

Fig. 12 shows a simulated waveform diagram of the gate driving circuit of the gan power device under the influence of dV/dt transient noise when the output is at a high level, and it can be seen from fig. 12 that, in the initial state, the reset input of the RS flip-flop 850 is at a logic high level and the set input is at a logic low level; during dV/dt transient noise, A₃And B₃The same zero signal is filtered out after passing through the common mode cancellation logic 840, and then the state of the latch is gradually restored. Due to the same zero time period P₁And P₂On at the same time, so there is a small co-rising process following the dV/dt transient noise, followed by a₃Gradually decreases to VS (logic ground level) and B₃Gradually rises to VB (logic high level). In this process, the input state of the RS flip-flop 850 is always unaffected, and therefore, the output remains at a logic high level.

Referring to fig. 13, a flow chart of a structure of a gate driving circuit of a gan power device according to an embodiment of the present application is shown. The gate driving circuit of the gallium nitride power device can comprise: a narrow pulse generation circuit 1310, a high voltage level shift circuit 1320, a dynamic asymmetric state generation circuit 1330, a preamplifier 1340, common mode mask logic 1350, an RS flip-flop 1360, and a buffer stage 1370.

As shown IN FIG. 13, the input terminal of the narrow pulse generation circuit 1310 is used as the input terminal IN _ H of the GaN power device gate driving circuit, and the first output terminal SE of the narrow pulse generation circuit 1310T is connected to a first input terminal of the high voltage level shift circuit 1320, a second output terminal RESET of the narrow pulse generating circuit 1310 is connected to a second input terminal of the high voltage level shift circuit 1320, a power supply terminal of the narrow pulse generating circuit 1310 is connected to a low voltage side power supply VCC, and a logic ground terminal of the narrow pulse generating circuit 1310 is connected to a chip ground; first output terminal A of the high voltage level shift circuit 1320₄A second output terminal B of the high voltage level shift circuit 1320 connected to the first output terminal of the dynamic asymmetric state generator 1330 and the first input terminal of the preamplifier 1340₄A second output terminal of the dynamic asymmetric state generator 1330 and a second input terminal of the preamplifier 1340 are connected, respectively; a first output E of preamplifier 1340 is connected to a first input of common mode mask logic 1350; a second output T of the preamplifier 1340 is connected to a second input of the common mode mask logic 1350; a first output of the common mode mask logic 1350 and a reset input R of the RS flip-flop 1360_E3A second output of the common mode mask logic 1350 is connected to a set input S of the RS flip-flop 1360_E3Connecting; the in-phase output end Q of the RS flip-flop 1360 is connected to the input end of the buffer stage 1370 and the first input end of the dynamic asymmetric state generating circuit, respectively; an inverted output end QB of the RS trigger 1360 is connected with a second input end of the dynamic asymmetric state generating circuit; the output end of the buffer stage is used as the output end HO of the gate drive circuit of the gallium nitride power device; the power terminals of the common mode shielding logic 1350, the RS flip-flop 1360 and the buffer 1370 are respectively connected to the high voltage side power source VB, and the logic grounds of the common mode shielding logic 1350, the RS flip-flop 1360 and the buffer 1370 are respectively connected to the high voltage region floating ground VS. The high voltage level shift circuit 1320 further includes a latch, and the dynamic asymmetric state generating circuit 1330 is configured to dynamically change a balance point of the latch when the power supply voltage is in a transient state, and the latch is shifted to an upper stable state when the balance point is changed, so as to control the output signal of the gate driving circuit of the gan power device to remain unchanged.

The circuit structures of the high voltage level shifter 1320, the dynamic asymmetric state generator 1330, the preamplifier 1340, the common mode mask logic 1350 and the RS flip-flop 1360 are described below.

1) A high voltage level shift circuit 1320;

the high voltage level shifting circuit 1320 may include: first switch N_LD12A second switch N_LD13A first diode D₁₃A second diode D₁₄And a latch including a first PMOS transistor P₃And a second PMOS transistor P₄. Wherein, the first switch N_LD12A gate of the high voltage level shift circuit 1320 as a first input terminal connected to the SET, and a second switch N_LD13As a second input terminal of the high voltage level shift circuit 1320, to the RESET; first switch N_LD12And a second switch N_LD13The source and the substrate of (1) are both grounded GND; first switch N_LD12Drain electrode of the first diode D₁₄Negative electrode of (1), first PMOS tube P₃Drain electrode of and a second PMOS transistor P₄As the first output terminal a of the high voltage level shift circuit 1320 after being interconnected₄(ii) a Second switch N_LD13Drain electrode of (1), first diode D₁₃Negative electrode of (1), second PMOS tube P₄Drain electrode of and the first PMOS transistor P₃As a second output terminal B of the high voltage level shift circuit 1320 after being interconnected₄(ii) a First PMOS tube P₃And a second PMOS transistor P₄The source electrodes of the two are respectively connected with a high-voltage side power supply VB; first diode D₁₃And a second diode D₁₄Are respectively connected to the high voltage region floating ground VS.

The second point to be noted is that the first diode and the second diode may be diodes, or may be base-emitter diodes of a triode or body diodes of a MOS transistor, and their functions are to clamp a₄And B₄The voltage of the point can also adopt a Zener diode to be connected in parallel with the first PMOS tube P₃And a second PMOS transistor P₄The source and drain ends.

The third point to be noted is that the first PMOS tube P₃And a second PMOS transistor P₄The width-to-length ratios of (A) and (B) may be uniform or nonuniform.

2) A dynamic asymmetric state generation circuit 1330;

the dynamic asymmetric state generation circuit 1330 may include: third NMOS transistor N₅And a fourth NMOS transistor N₆A third resistor R₈And a fourth resistor R₉. Wherein, the third NMOS transistor N₅Source electrode and fourth NMOS transistor N₆Is connected with the floating ground VS of the high-voltage area after being interconnected; third resistor R₈First end of and third NMOS tube N₅Is connected to the drain of the first resistor R, and a third resistor R₈As the first output terminal of the dynamic asymmetric state generation circuit 1330 and A₄Connecting; a fourth resistor R₉First end of and fourth NMOS tube N₆Is connected to the drain of the fourth resistor R₉As the second output terminal of the dynamic asymmetric state generation circuit 1330 and B₄Connecting; third NMOS transistor N₅The gate of which is connected to Q as a first input of the dynamic asymmetric state generating circuit 1330; fourth NMOS transistor N₆Is coupled to QB as a second input of the dynamic asymmetric state generating circuit 1330.

It should be noted that the latch may be a latch formed by PMOS transistors, or may be another latch for turning on devices with negative gate-source voltage or negative base-emitter voltage, as long as the third NMOS transistor N is ensured₅And a fourth NMOS transistor N₆Has much lower current capability than the first PMOS transistor P in the latch₃And a second PMOS transistor P₄The current capability of (2).

3) A preamplifier 1340;

the preamplifier 1340 may include: first P-type switch P₅A second P-type switch P₆A first resistor R₁₀And a second resistor R₁₁. Wherein the first P-type switch P₅As a first input of the preamplifier 1340, a second P-type switch P₆As a second input of preamplifier 1340; first P-type switch P₅Drain electrode of (1), first resistor R₁₀As a first output E of the preamplifier 1340; second P-type switch P₆Drain electrode of (1), second resistor R₁₁As a second output T of the preamplifier 1340; a first resistor R₁₀Second terminal and second resistor R₁₁Are interconnected and then connected to the high voltage region floating ground VS; first P-type switch P₅And a second P-type switch P₆Is interconnected to a high side power supply VB.

4) Common mode mask logic 1350;

common mode shield logic 1350 may include: the sixth NAND gate NAND₁₄NAND gate₁₅And an eighth NAND gate NAND₁₆. Wherein the sixth NAND gate NAND₁₄First input terminal and seventh NAND gate NAND₁₅The first input ends of the common mode shielding logic are connected with T as the second input end of the common mode shielding logic after being interconnected; the sixth NAND gate NAND₁₄Second input terminal and eighth NAND gate NAND₁₆The first input ends of the common mode shielding logic are connected with E as the first input end of the common mode shielding logic after being interconnected; the sixth NAND gate NAND₁₄Respectively with a seventh NAND gate₁₅And an eighth NAND gate NAND₁₆Is connected with the second input end; the seventh NAND gate NAND₁₅The output terminal of the logic circuit is used as a first output terminal of the common mode shielding logic and R_E3Connected, eighth NAND gate NAND₁₆The output terminal of the first logic is used as a second output terminal of the common mode shielding logic and S_E3Are connected.

5) RS flip-flop 1360;

the RS trigger 1360 may include: the fourth NAND gate NAND₁₇And a fifth NAND gate NAND₁₈. Wherein the fourth NAND gate NAND₁₇As the reset input R of the RS flip-flop 1360_E3The fifth NAND gate NAND₁₈As the set input S of the RS flip-flop 1360_E3(ii) a The fourth NAND gate NAND₁₇Second input terminal and fifth NAND gate NAND₁₈The output terminals of which are interconnected to serve as the in-phase output terminal Q of the RS flip-flop 1360; the fifth NAND gate NAND₁₈Second input terminal and fourth NAND gate NAND₁₇Is interconnected to serve as the inverting output QB of the RS flip-flop 1360.

In this embodiment, the logic function of the preamplifier 1340 is the same as that of the inverter in the common mode mask logic 1350, and the response threshold is much lower than that of the inverter, so that the response range of the signal is widened, and the VS negative bias capability of the chip can be improved.

The working flow of the gate driving circuit of the gallium nitride power device shown in fig. 13 is the same as that of the gate driving circuit of the gallium nitride power device shown in fig. 8, and is not described again.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims

1. A gate driving circuit of a gallium nitride power device, the gate driving circuit comprising: the circuit comprises a narrow pulse generating circuit, a high-voltage level shifting circuit, a dynamic asymmetric state generating circuit, common mode shielding logic, an RS trigger and a buffer stage;

2. The gan power device gate driver circuit of claim 1, wherein the high voltage level shifter circuit comprises: the latch comprises a first switch, a second switch, a first diode, a second diode and a latch, wherein the latch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube;

3. The gallium nitride power device gate drive circuit of claim 2, wherein the dynamic asymmetric state generating circuit comprises: the first NMOS tube and the second NMOS tube;

4. The gallium nitride power device gate drive circuit of claim 3, wherein the common mode shield logic comprises: the first inverter, the second inverter, the first NAND gate, the second NAND gate and the third NAND gate;

5. The gallium nitride power device gate drive circuit of claim 1, wherein the RS flip-flop comprises: a fourth NAND gate and a fifth NAND gate;

6. The gallium nitride power device gate drive circuit according to claim 1, further comprising a preamplifier;

7. The GaN power device gate drive circuit of claim 6, wherein the preamplifier comprises: the circuit comprises a first P-type switch, a second P-type switch, a first resistor and a second resistor;

8. The GaN power device gate driver circuit of claim 6, wherein the dynamic asymmetric-state generation circuit comprises: the third NMOS tube, the fourth NMOS tube, the third resistor and the fourth resistor;

9. The gallium nitride power device gate drive circuit of claim 6, wherein the common mode shield logic comprises: a sixth nand gate, a seventh nand gate and an eighth nand gate;

10. The GaN power device gate driving circuit of claim 3, wherein the current capability of the first NMOS transistor and the second NMOS transistor is lower than the current capability of the first PMOS transistor and the second PMOS transistor in the latch.