CN103066833B - Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree - Google Patents
Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree Download PDFInfo
- Publication number
- CN103066833B CN103066833B CN201210594578.5A CN201210594578A CN103066833B CN 103066833 B CN103066833 B CN 103066833B CN 201210594578 A CN201210594578 A CN 201210594578A CN 103066833 B CN103066833 B CN 103066833B
- Authority
- CN
- China
- Prior art keywords
- current
- switch
- array
- cycle switching
- switching array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a switching power supply converter and a circuit capable of improving charge pump charge-discharge current match degree. The circuit capable of improving charge pump charge-discharge current match degree comprises a first current mirror array which divides a reference current into two first image currents which are equal to the reference current in a mirror image mode, a first current circulation switchover array which enables the two first image currents be circularly switched, a second current mirror array which comprises a plurality of current sources, a second current circulation switchover array, a third current circulation switchover array and a charge-discharge switch which charges or discharges an electric capacity. The second current circulation switchover array enables the plurality of current sources in the second current mirror array to be circularly switched, thereby enabling the plurality of the current sources to alternately serve as a reference source and an output source of a current mirror. The third current circulation switchover array enables two circulating current output ends of the second current circulation switchover array to be circularly switched, thereby enabling the two circulating current output ends to alternately serve as an input end and an output end of the current mirror. The witching power supply converter and the circuit capable of improving charge pump charge-discharge current match degree are capable of solving the problem of mismatch of a charge current and a discharge current caused by deviation between transistors.
Description
Technical field
The present invention relates to charge pumping technique, particularly relate to the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree.
Background technology
At present, in switch power converter circuit, extensively by controlling, charge pump charges, the proportionate relationship of discharge current controls constant current output.
Fig. 1 is a kind of CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of multiple cascade.Wherein, reference current I0 is mirrored as charging reference current I1 and discharge current Idisch, and charging reference current I1 again mirror image is charging current Ich.Because the matching degree of cmos device is poor, charging current Ich, between discharge current Idisch and reference current Iin, there is larger mismatch.
Fig. 2 is a kind of cyclic switching CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of multiple cascade.Reference current I0 is mirrored as the charging reference current I1 and M equal with this reference current I0 discharges reference current, wherein M be greater than 1 integer, M electric discharge reference current circulates selection one electric discharge reference current as discharge current Idisch through the first current cycle switching array 201, charging reference current I1 mirror image is that the N number of mirror image equal with described charging reference current I1 charges reference current, wherein N be greater than 1 integer, N number of mirror image charging reference current circulates selection mirror image charging reference current as charging current Ich through the second current cycle switching array 202.
First current cycle switching array 201 comprises M image current input and a current cycle array output end, second current cycle array 202 comprises N number of image current input and a current cycle array output end, has a gauge tap between each image current input and current cycle array output end.By selecting a discharge current Idisch from the circulation of M electric discharge reference current and selecting a charging current Ich from the circulation of N number of mirror image charging reference current, M electric discharge reference current and N number of mirror image charging reference current is equivalent to average respectively, mismatch is declined to some extent, but still there is comparatively big error from the process that reference current I0 mirror image is the charging reference current I1 equal with described reference current I0.
Summary of the invention
The technical problem to be solved in the present invention is to provide the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree, can solve the problem of charging current that the deviation between transistor causes and discharge current mismatch.
For solving the problems of the technologies described above, the invention provides a kind of circuit improving charge pump charging and discharging currents matching degree, comprising:
First current lens array, for by reference current mirror image being 2 first image currents equal with this reference current;
First current cycle switching array, there are 2 current input terminals and 2 circulating current outputs, 2 current input terminals of described first current cycle switching array receive 2 the first image currents of described first current lens array output respectively, described first current cycle switching array carries out cyclic switching to described 2 the first image currents, makes the two alternate conduction to 2 circulating current outputs of described first current cycle switching array;
Second current lens array, comprises N number of current source, for by described reference current mirror image being the second image current that N-1 is equal with this reference current, wherein N be greater than 1 integer;
Second current cycle switching array, there are N number of current input terminal and 2 circulating current outputs, N number of current input terminal of described second current cycle switching array connects the N number of current source in described second current lens array respectively, described second current cycle switching array carries out cyclic switching to described N number of current source, make one of them reference source as current mirror of described N number of current source and other N-1 current source as the output source of current mirror, 2 circulating current outputs of described second current cycle array are connected to described reference source and one of them output source respectively;
3rd current cycle switching array, there are 2 current input terminals and 2 circulating current outputs, 2 current input terminals of described 3rd current cycle switching array connect 2 circulating current outputs of described second current cycle switching array respectively, 2 the circulating current outputs of described 3rd current cycle switching array to described second cyclic switching array carry out cyclic switching, make 2 circulating current outputs of described second current cycle switching array alternately as input and the output of current mirror;
Charging and discharging switch, there is 2 inputs and 1 output, these 2 inputs be connected respectively to 2 circulating current outputs one of them and the described 3rd current cycle switching array of described first current cycle switching array 2 circulating current outputs one of them, this output is connected to external capacitive to carry out charge or discharge to it.
According to one embodiment of present invention, described first current cycle switching array comprises:
First switch, its first end receives first image current that described first current lens array exports, and its second end is as a circulating current output of described first current cycle switching array;
Second switch, its first end receives another first image current that described first current lens array exports, and its second end connects the second end of described first switch;
3rd switch, its first end connects the first end of described second switch, and its second end is as another circulating current output of described first current cycle switching array;
4th switch, its first end connects the first end of described first switch, and its second end connects the second end of described 3rd switch;
Wherein, the control end of described first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described second current cycle switching array comprises N number of switch, the first end of this N number of switch connects described N number of current source respectively, second end of described N number of one of them switch of switch connects a circulating current output of described second current cycle switching array and constant conduction, second end of another N-1 switch in described N number of switch connects another circulating current output of described second current cycle switching array, and have in a described another N-1 switch in the clock cycle in office and only have a conducting, and each conducting of a described another N-1 switch is once within N-1 clock cycle.
According to one embodiment of present invention, described 3rd current cycle switching array comprises:
5th switch, its first end connects a circulating current output of described second current cycle switching array, its second end as described 3rd current cycle switching array a circulating current output and be connected to the control end of N number of current source of described second current lens array;
6th switch, its first end connects another circulating current output of described second current cycle switching array, and its second end connects the second end of described 5th switch;
7th switch, its first end connects the first end of described 6th switch, and its second end is as another circulating current output of described 3rd current cycle switching array;
8th switch, its first end connects the first end of described 5th switch, and its second end connects the second end of described 7th switch;
Wherein, the control end of described 5th switch and the 7th switch receives same control signal, and the control end of described 6th switch and the 8th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described charging and discharging switch comprises:
9th switch, its first end connects a circulating current output of described first current cycle switching array, and its second end connects described external capacitive;
Tenth switch, its first end connects a circulating current output of described 3rd current cycle switching array, and its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described 9th switch and the tenth switch is mutually anti-phase.
Present invention also offers a kind of switch power converter, comprise the circuit of the raising charge pump charging and discharging currents matching degree described in above any one.
Compared with prior art, the present invention has the following advantages:
In the circuit of the raising charge pump charging and discharging currents matching degree of the embodiment of the present invention, current mirror input, output current are switched the impact on charge pump charging, discharge current matching degree caused with the process deviation eliminated between transistor through loop cycle, except the current source that reference current flows through, to charging, the relevant current source of discharge current all through cyclic switching, thus greatly eliminate the error of charging, discharge current matching degree difference band.
Accompanying drawing explanation
Fig. 1 is a kind of charge pump charging of the prior art, discharge circuit;
Fig. 2 is another kind of charge pump charging of the prior art, discharge circuit;
Fig. 3 shows the circuit block diagram of the raising charge pump charging and discharging currents matching degree of the embodiment of the present invention;
Fig. 4 shows in first embodiment of the invention the detailed circuit diagram of the circuit improving charge pump charging and discharging currents matching degree;
Fig. 5 shows in second embodiment of the invention the detailed circuit diagram of the circuit improving charge pump charging and discharging currents matching degree.
Detailed description of the invention
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
With reference to figure 3, the circuit of the raising charge pump charging and discharging currents matching degree of the present embodiment comprises: the first current lens array 1, first current cycle switching array 2, charging and discharging switch 3, the 3rd current cycle switching array 4, second current cycle switching array 5, second current lens array 6 and reference current source 7.
Wherein, reference current source 7 output reference electric current, it can adopt any one suitable reference current source structure in prior art.
First current lens array 1 is 2 first image currents equal with this reference current for the reference current mirror image exported by reference current source 7, and the first current lens array 1 such as can adopt 2 current mirrors to realize.
First current cycle switching array 2 has 2 current input terminals 21 and 2 circulating current outputs 22,23,2 current input terminals 21 of the first current cycle switching array 2 receive 2 the first image currents of the first current lens array 1 output respectively, first current cycle switching array 2 carries out cyclic switching to receive 2 the first image currents, makes 2 circulating current outputs 22,23 of the two alternate conduction to the first current cycle switching array 2.
Furthermore, a gauge tap is all connected between each image current input 21 and each circulating current output 22,23, gauge tap totally 4, after cyclic switching by the first current cycle switching array 2, each circulating current output 22,23 output current is the mean value of the image current that two image current inputs 21 input, thus the reference current playing electric current that circulating current output 22,23 that the deviation of eliminating transistor causes exports and reference current source 7 does not mate.
Second current lens array 6 comprises N number of current source, and the reference current mirror image for being exported by reference current source 7 is the second image current that N-1 is equal with this reference current, wherein N be greater than 1 integer.When the first current lens array 1 is used as charging current, the second current lens array 6 can be used as discharge current; When the first current lens array 1 is used as discharge current, the second current lens array 6 can be used as charging current.As a nonrestrictive example, the N number of current source in the second current lens array adopts N number of MOS transistor to realize, and certainly, it will be appreciated by those skilled in the art that current source can also adopt other appropriate ways to realize, the current source of such as cascade structure.
Second current cycle switching array 5 has N number of current input terminal (comprising 1 current input terminal 50 and N-1 current input terminal 51) and 2 circulating current outputs 52, 53, N number of current input terminal 50 of the second current cycle switching array, 51 connect the N number of current source in the second current lens array 6 respectively, second current cycle switching array 5 carries out cyclic switching to this N number of current source, make one of them reference source as current mirror of N number of current source and other N-1 current source as the output source of current mirror, 2 circulating current outputs 52 of the second current cycle array 5, 53 are connected to reference source and one of them output source respectively.
Furthermore, N number of MOS transistor one_to_one corresponding of current source output 50, a N-1 current input terminal 51 and the second current lens array 6, is connected to a switch, gauge tap constant conduction between current input terminal 50 and circulating current output 52; N-1 current source output 51 and the indirect of circulating current output 53 all have a switch, in the clock cycle in office, have and only have a conducting in N-1 switch, and within N-1 clock cycle, each conducting of arbitrary N-1 switch once.After cyclic switching by the second current cycle switching array 5, circulating current output 53 output current is the mean value of the first image current that N-1 current input terminal 51 inputs, thus the reference current playing electric current that circulating current output 53 that the deviation of eliminating transistor causes exports and reference current source 7 does not mate.
3rd current cycle switching array 4 has 2 current input terminals, 40,41 and 2 circulating current outputs 42,43,2 current input terminals 40,41 of the 3rd current cycle switching array 4 connect 2 circulating current outputs 52,53 of the second current cycle switching array 5 respectively, 2 the circulating current outputs 52,53 of 3rd current cycle switching array 4 to the second cyclic switching array 5 carry out cyclic switching, make 2 circulating current outputs 52,53 of the second current cycle switching array 5 alternately as input and the output of current mirror.
Furthermore, current input terminal 40, 41 and second two the circulating current output 52 of current cycle switching array 5, 53 one_to_one corresponding, and current input terminal 40, 41 and circulating current output 42, a gauge tap is all connected between 43, gauge tap totally 4, after cyclic switching by the 3rd current cycle switching array 4, circulating current output 42, 43 output currents are two image current inputs 40, the mean value of the first image current of 41 inputs, thus the circulating current output 52 that the deviation playing elimination transistor causes, not mating between 53 electric currents exported.
As a nonrestrictive example, the circulating current output 42 of the 3rd current cycle switching array 4 is directly connected with the circulating current output 22 of the first current cycle switching array 2.
Charging and discharging switch 3 has 2 inputs and 1 output, these 2 inputs be connected respectively to 2 circulating current outputs one of them and the 3rd current cycle switching array 4 of the first current cycle switching array 22 circulating current outputs one of them, this output is connected to external capacitive 8 to carry out charge or discharge to it.
More specifically, two inputs of charging and discharging switch 3 are connected respectively to the circulating current output 23 of the first current cycle switching array 2 and the circulating current output 43 of the 3rd current cycle switching array 4, and output is connected to external capacitive 8.Within the same clock cycle, the output of charging and discharging switch 3 has and only has a charging, the input of discharge switch 3 and its conducting, and within two clock cycle, the output of charging and discharging switch 3 and each conducting of input of arbitrary charging and discharging switch 3 are once.
Wherein the first current lens array 1 can adopt the interconnection of multiple nmos pass transistor to realize, and now the second current lens array 6 adopts the interconnection of multiple PMOS transistor to realize; Otherwise when the first current lens array 1 adopts PMOS transistor to realize, the second current mirror 6 can adopt nmos pass transistor to realize.
Improve charge pump charging in the present embodiment, the working method of circuit of discharge current matching degree is summarized as follows: the reference current mirror image of the reference current source 7 of input is become two first image currents equal with the reference current of reference current source 7 by the first current lens array 1, and the first image current is sent into the first current cycle switching array 2, first current cycle switching array 2 makes the electric current exported at two clock cycle Inner eycle current output terminals 22,23 be the mean value of the first image current that two image current inputs 21 input through cyclic switching, second current lens array 6 has N number of current source, and its output connects the second current cycle switching array 5, the electric current that circulating current output 52 exports is the electric current that current input terminal 50 inputs, and the second current cycle switching array 5 makes the electric current exported at N-1 clock cycle Inner eycle current output terminal 53 be the mean value of the electric current of N-1 current input terminal 51 input through cyclic switching, the electric current that circulating current output 52,53 exports is sent into the 3rd current cycle switching array the 4, three current cycle switching array 4 and is made the electric current exported at two clock cycle Inner eycle current output terminals 42,43 be the mean value of the electric current that two current input terminals 40,41 input through cyclic switching, by the cyclic switching of the second current cycle switching array 5 and the 3rd current cycle switching array 4, the electric current exported at 2 × (N-1) Inner eycle current output terminals of individual clock cycle 42,43 is made to be the mean value of the mean value of the electric current that N-1 current input terminal 51 inputs and the electric current of current input terminal 50 input, circulating current output 42 export electric current be used as the second current lens array 6 reference source reference source electric current and and circulating current output 22 output electric current be same electric current, the electric current of electric current and circulating current output 23 output exported at 2 × 2 × (N-1) Inner eycle current output terminals 43 of individual clock cycle is made to be the mean value of the image current that two image current inputs 21 input, the charging current of charge pump within 2 × 2 × (N-1) individual clock cycle and discharge current is namely made to be the mean value of the image current that two image current inputs 21 input.
Circuit shown in Fig. 3 may be used for switch power converter, and this switch power converter can be the various switch power converter being controlled constant current output by charge pump charging, discharge current proportionate relationship in prior art.
Show the detailed circuit diagram of the first embodiment with reference to figure 4, Fig. 4, wherein N equals 3.Be described in detail below.
In a first embodiment, the first current lens array 1 comprises nmos pass transistor B0 to B2, wherein nmos pass transistor B0 grid and drain electrode short circuit, source ground; The grid of nmos pass transistor B1 and nmos pass transistor B2 is connected to the grid of nmos pass transistor B0, source ground; The drain electrode of nmos pass transistor B1 and nmos pass transistor B2 exports the first image current respectively.
Second current lens array 6 comprises PMOS transistor A1 to A2, and wherein the source electrode of PMOS transistor A1 to A2 is connected to source electrode, and the grid of PMOS transistor A1 to A2 links together.
First current cycle switching array 2 comprises the first switch Q0, second switch Q1, the 3rd switch Q2, the 4th switch Q3.Wherein, the first end of the first switch Q0 and the 4th switch Q3 links together, and the first end of second switch Q1 and the 3rd switch Q2 links together (being specially the drain electrode being connected to nmos pass transistor B2).Second end of the first switch Q0 and second switch Q1 links together, and second end of the 3rd switch Q2 and the 4th switch Q3 links together.
In the first embodiment shown in Fig. 4, the second current cycle switching array 5 comprises 3 switches J0, J1, J2.The first end of its breaker in middle J0 connects the drain electrode of PMOS transistor A1, and the first end of switch J1 connects the drain electrode of PMOS transistor A2, and the first end of switch J2 connects the drain electrode of PMOS transistor A3, and second end of switch J1 and switch J2 links together.
3rd current cycle switching array 4 comprises the 5th switch P 0, the 6th switch P 1, the 7th switch P 2 and the 8th switch P 3.Wherein the second end of the 5th switch P 0 and the 6th switch P 1 is connected to the grid of PMOS transistor A1, and the grid of PMOS transistor A2 and PMOS transistor A3 is connected to the grid of PMOS transistor A1.The first end of the 5th switch P 0 and the 8th switch P 3 is connected to one end of switch J0, and the first end of the 6th switch P 1 and the 7th switch P 2 is connected to one end of switch J1 and switch J2.
Charging and discharging switch 3 comprises the 9th K switch 1 and the tenth K switch 0.Wherein, the first end of the 9th K switch 1 connects one end of the 3rd switch Q2 and the 4th switch Q3, one end of first end connecting valve P2 and P3 of the tenth K switch 0, second end of the 9th K switch 1 and the second end of the tenth K switch 0 link together and are jointly connected to one end of external capacitive C0, the other end ground connection of external capacitive C0.
As a nonrestrictive example, the first switch Q0 and the 3rd switch Q2 controls by same clock signal C 0, and second switch Q1 and the 4th switch Q3 controls by the inversion signal C1 of same clock signal C 0.Tenth K switch 0 suspension control signal C2 controls, and the inversion signal C3 of the 9th K switch 1 suspension control signal C2 controls.5th switch P 0 and the 7th switch P 2 control by same clock signal C 4, and the 6th switch P 1 and the 8th switch P 3 control by the inversion signal C5 of same clock signal C 4.Switch J0 constant conduction, switch J1 subject clock signal C6 controls, and the inversion signal C7 of switch J2 subject clock signal C6 controls.Clock signal C 0, clock signal C 4 and clock signal C 6 form 8 unit period clocks, and C0, C4, C6 cover 000,001,010,011,100,101,110,111 these 8 kinds of states.
Control signal C2 can be such as the square wave of 50% dutycycle.Suppose
be mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current flowing through nmos pass transistor B1 can be used
represent, wherein I
0represent the current value of reference current, similarly, the transmission error between other MOS transistors and the electric current flowing through each MOS transistor also can adopt as upper type is stated, then every 4 unit period clock charging current I
chargingwith discharge current I
electric dischargeratio is:
Suppose
be 0.7,
be 0.7, substitution can obtain:
Suppose that 0.7 for maximum deviation, usually
with
0.7 can not be equaled simultaneously, therefore:
As seen from the above, adopt the program, charge pump charging, discharge current matching degree are significantly improved.
With reference to figure 5, Fig. 5 shows the detailed circuit diagram of the second embodiment, wherein N equals 2, in the case, 2 switches in second current cycle switching array are all in permanent conducting state, thus the second cyclic switching array can be saved and direct short circuit, other structures and aforementioned first embodiment similar, be described in detail below.
The grid of nmos pass transistor B0 and drain electrode short circuit, source ground.The grid of nmos pass transistor B1 and NNMOS transistor B2 is connected to the grid of nmos pass transistor B0, source ground.The drain electrode of nmos pass transistor B1 is connected to one end of switch Q0 and Q3, and the drain electrode of nmos pass transistor B2 is connected to one end of switch Q1 and Q2.The other end of switch Q0 and Q1 is connected to the grid of PMOS transistor A1, and the other end of switch Q2 and Q3 is connected to one end of K switch 1.One end of switch P 0 and P1 is connected to the grid of PMOS transistor A1, and the grid of PMOS transistor A2 is connected to the grid of PMOS transistor A1, and the source electrode of PMOS transistor A1, A2 is connected to power supply.The other end of K switch 1 is connected to one end of external capacitive C0 and K switch 0, the other end ground connection of electric capacity C0.The other end of switch P 0 and P3 is connected to the drain electrode of PMOS transistor A1.The other end of switch P 1 and P2 is connected to the drain electrode of PMOS transistor A2.
Switch Q0 and Q2 controls by same clock signal C 0, and switch Q1 and Q3 controls by the inversion signal C1 of same clock signal C 0.K switch 0 suspension control signal C2 controls, and the inversion signal C3 of K switch 1 suspension control signal C2 controls.Switch P 0 and P2 control by same clock signal C 4, and switch P 1 and P3 control by the inversion signal C5 of same clock signal C 4.
Clock signal C 0, clock signal C 4 form 4 unit period clocks, and C0, C4 cover 00,01,10,11 these 4 kinds of states.Control signal C2 can be the square wave of 50% dutycycle.
Suppose
for being mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current flowing through nmos pass transistor B1 can be used
represent, wherein I
0represent the current value of reference current, similarly, the transmission error between other MOS transistors and the electric current flowing through each MOS transistor also can adopt as upper type is stated, then every 4 unit period clock charging currents and discharge current ratio are:
Suppose
be 0.7, substitution can obtain
This shows, adopt the program, charge pump charging, discharge current matching degree are significantly improved.
In sum, the invention provides a kind of charge pump to be charged, discharge current switches eliminates process deviation between transistor to the circuit of the impact that matching degree causes through loop cycle, above raising charge pump charges, in the circuit for eliminating of discharge current matching degree prior art due to impact that the deviation between transistor causes matching precision.
Above-described embodiment is just to explanation of the present invention, instead of limitation of the present invention, any innovation and creation do not exceeded in spirit of the present invention, charging circuit and discharge circuit structure is included but not limited to exchange, change clock signal sequential, to the change of the local structure of circuit (as utilize those skilled in the art thinkable technical method replace current source structure in the present invention, electric capacity is replaced to electric capacity with being connected to and is connected to power supply etc.), to the type of components and parts or the replacement (as PMOS is replaced with NMOS tube etc.) of model, and the replacement of other unsubstantialities or amendment, all fall within scope.
Claims (6)
1. improve a circuit for charge pump charging and discharging currents matching degree, it is characterized in that, comprising:
First current lens array, for by reference current mirror image being 2 first image currents equal with this reference current;
First current cycle switching array, there are 2 current input terminals and 2 circulating current outputs, 2 current input terminals of described first current cycle switching array receive 2 the first image currents of described first current lens array output respectively, described first current cycle switching array carries out cyclic switching to described 2 the first image currents, makes the two alternate conduction to 2 circulating current outputs of described first current cycle switching array;
Second current lens array, comprises N number of current source, for by described reference current mirror image being the second image current that N-1 is equal with this reference current, wherein N be greater than 1 integer;
Second current cycle switching array, there are N number of current input terminal and 2 circulating current outputs, N number of current input terminal of described second current cycle switching array connects the N number of current source in described second current lens array respectively, described second current cycle switching array carries out cyclic switching to described N number of current source, make one of them reference source as current mirror of described N number of current source and other N-1 current source as the output source of current mirror, 2 circulating current outputs of described second current cycle array are connected to described reference source and one of them output source respectively;
3rd current cycle switching array, there are 2 current input terminals and 2 circulating current outputs, 2 current input terminals of described 3rd current cycle switching array connect 2 circulating current outputs of described second current cycle switching array respectively, 2 the circulating current outputs of described 3rd current cycle switching array to described second current cycle switching array carry out cyclic switching, make 2 circulating current outputs of described second current cycle switching array alternately as input and the output of current mirror;
Charging and discharging switch, there is 2 inputs and 1 output, these 2 inputs be connected respectively to 2 circulating current outputs one of them and the described 3rd current cycle switching array of described first current cycle switching array 2 circulating current outputs one of them, this output is connected to external capacitive to carry out charge or discharge to it.
2. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, is characterized in that, described first current cycle switching array comprises:
First switch, its first end receives first image current that described first current lens array exports, and its second end is as a circulating current output of described first current cycle switching array;
Second switch, its first end receives another first image current that described first current lens array exports, and its second end connects the second end of described first switch;
3rd switch, its first end connects the first end of described second switch, and its second end is as another circulating current output of described first current cycle switching array;
4th switch, its first end connects the first end of described first switch, and its second end connects the second end of described 3rd switch;
Wherein, the control end of described first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
3. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, it is characterized in that, described second current cycle switching array comprises N number of switch, the first end of this N number of switch connects described N number of current source respectively, second end of described N number of one of them switch of switch connects a circulating current output of described second current cycle switching array and constant conduction, second end of another N-1 switch in described N number of switch connects another circulating current output of described second current cycle switching array, and have in a described another N-1 switch in the clock cycle in office and only have a conducting, and each conducting of a described another N-1 switch is once within N-1 clock cycle.
4. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, is characterized in that, described 3rd current cycle switching array comprises:
5th switch, its first end connects a circulating current output of described second current cycle switching array, its second end as described 3rd current cycle switching array a circulating current output and be connected to the control end of N number of current source of described second current lens array;
6th switch, its first end connects another circulating current output of described second current cycle switching array, and its second end connects the second end of described 5th switch;
7th switch, its first end connects the first end of described 6th switch, and its second end is as another circulating current output of described 3rd current cycle switching array;
8th switch, its first end connects the first end of described 5th switch, and its second end connects the second end of described 7th switch;
Wherein, the control end of described 5th switch and the 7th switch receives same control signal, and the control end of described 6th switch and the 8th switch receives the inversion signal of described control signal.
5. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, it is characterized in that, described charging and discharging switch comprises:
9th switch, its first end connects a circulating current output of described first current cycle switching array, and its second end connects described external capacitive;
Tenth switch, its first end connects a circulating current output of described 3rd current cycle switching array, and its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described 9th switch and the tenth switch is mutually anti-phase.
6. a switch power converter, is characterized in that, comprises the circuit of the raising charge pump charging and discharging currents matching degree according to any one of claim 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210594578.5A CN103066833B (en) | 2012-12-31 | 2012-12-31 | Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210594578.5A CN103066833B (en) | 2012-12-31 | 2012-12-31 | Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103066833A CN103066833A (en) | 2013-04-24 |
| CN103066833B true CN103066833B (en) | 2015-03-25 |
Family
ID=48109325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210594578.5A Active CN103066833B (en) | 2012-12-31 | 2012-12-31 | Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103066833B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN203014673U (en) * | 2012-12-31 | 2013-06-19 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
-
2012
- 2012-12-31 CN CN201210594578.5A patent/CN103066833B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN203014673U (en) * | 2012-12-31 | 2013-06-19 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103066833A (en) | 2013-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102195316B (en) | Balancing circuit for charge storage elements | |
| CN104796132A (en) | Flip-flop circuit | |
| TW201315155A (en) | Phase interpolation circuit | |
| CN106558992A (en) | Power supply change-over device | |
| CN203014674U (en) | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump | |
| CN102455732B (en) | Improve the circuit of multichannel big current matching degree | |
| JP2008005446A (en) | Frequency divider and its control method | |
| CN105071809B (en) | Complementary current circuit, on-off circuit and the current mode digital-to-analog converter of Background calibration | |
| CN102025270A (en) | Charge pump circuit | |
| CN103066833B (en) | Switching power supply converter and circuit capable of improving charge pump charge-discharge current match degree | |
| CN113114175A (en) | VCDL delay unit circuit and application thereof | |
| CN203014673U (en) | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump | |
| CN103001489B (en) | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump | |
| CN102761325B (en) | Selector circuit with fixed output state | |
| CN102931983B (en) | Delay element and digitally controlled oscillator | |
| CN103580650A (en) | D flip-flop with high-swing output | |
| CN101488738B (en) | Time clock generating circuit and design method | |
| CN106330176B (en) | Latch and frequency divider | |
| CN108063549A (en) | A kind of isolation control circuit | |
| CN111490756B (en) | Time sequence generating circuit | |
| CN104579318A (en) | Multichannel clock buffer | |
| CN110739961B (en) | Level shifter | |
| CN102710233B (en) | Self-adaptive tuning system of continuous time filter | |
| CN117318258A (en) | Switch capacitor charging circuit | |
| CN203761374U (en) | Channel selection switch and analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |