CN113114117A - Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier - Google Patents
Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier Download PDFInfo
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- CN113114117A CN113114117A CN202110376884.0A CN202110376884A CN113114117A CN 113114117 A CN113114117 A CN 113114117A CN 202110376884 A CN202110376884 A CN 202110376884A CN 113114117 A CN113114117 A CN 113114117A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
Abstract
The invention discloses a bias circuit for a cascode radio frequency low noise amplifier common-gate tube, which comprises a cascode radio frequency low noise amplifier amplifying circuit and a bias voltage generating circuit, wherein the bias voltage generating circuit comprises a current source I, a sixth MOS tube M6, a fifth MOS tube M5, a third MOS tube M3, a fourth MOS tube M4, a seventh MOS tube M7, an eighth MOS tube M8, a first resistor R1, a fifth resistor R5 and a second resistor R2; the invention adopts a mode that the current of a current source flows into a combined system of a resistor and an MOS tube to generate a bias voltage to apply the bias voltage to the common-gate tube, thereby greatly reducing the change of the quiescent current of the amplifier along with the change of the power voltage, the threshold of the resistor and the MOS device in different batches and improving the stability of various characteristics of the amplifier.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a biasing circuit for a common-gate tube of a cascode radio-frequency low-noise amplifier.
Background
At present, in a traditional cascode radio frequency low noise amplifier, a common gate transistor bias voltage is usually generated by dividing a power supply voltage by a transistor or a resistor, but the divided voltage changes along with the power supply voltage, the length of a transistor channel is reduced along with the development of an integrated circuit process, the influence of the common gate transistor threshold voltage and a gate voltage on a cascode configuration common gate transistor current caused by a channel length modulation effect is large, the consistency of the radio frequency amplifier quiescent current mass production is poor, and in order to ensure the consistency of the amplifier bias current, a technical means is provided for calibrating and trimming the current by adopting a digital Fuse current, so that the chip integration cost and the test cost are high.
As shown in fig. 1, the fifth MOS transistor M5, the sixth MOS transistor M6, the fifth resistor R5, the current source I and the resistors Ra and Rb form a conventional amplifier bias circuit, in a conventional manner, VG2c is connected to VG2 as a bias voltage of the common-gate transistor,
under this bias condition
Vce=Vdd*(Rb/(Ra+Rb))-Vod_M2-Vth_M2-Veg
Vig=Vdd*(Rb/(Ra+Rb))-Vod_M6-Vth_M6
Vod _ M2/Vth _ M2 are the overdrive voltage and the threshold voltage of the second MOS transistor M2, respectively, and Veg is close to 0V.
Vod _ M6/Vth _ M6 is the overdrive voltage and the threshold voltage of the sixth MOS transistor M6, respectively.
If the power supply voltage Vdd changes or the second MOS transistor M2 changes and the threshold voltage of the sixth MOS transistor M6 changes, the drain-source voltage Vce of the first MOS transistor M1 changes, the drain-source voltage Vig of the fifth MOS transistor M5 changes, and under the short channel effect, the change of the drain-source voltage of the first MOS transistor M1 and the fifth MOS transistor M5 significantly affects the magnitude of the bias current thereof, so that the amplifier gain, the noise coefficient and the linearity change greatly and exceed the design index range.
Disclosure of Invention
The invention aims to provide a bias circuit for a common-gate tube of a cascode radio-frequency low-noise amplifier, and the bias circuit is used for solving the problems that in the prior art, the current of a cascode configuration common-gate tube is greatly influenced by the threshold voltage and the gate voltage of the common-gate tube due to the channel length modulation effect, and further the mass production of quiescent current of a radio-frequency amplifier is poor in consistency.
In order to achieve the purpose, the invention adopts the technical scheme that: a bias circuit for a cascode radio-frequency low-noise amplifier common-gate tube comprises a cascode radio-frequency low-noise amplifier amplifying circuit and a bias voltage generating circuit, wherein the bias voltage generating circuit comprises a current source I, a sixth MOS tube M6, a fifth MOS tube M5, a third MOS tube M3, a fourth MOS tube M4, a seventh MOS tube M7, an eighth MOS tube M8, a first resistor R1, a fifth resistor R5 and a second resistor R2, a power supply voltage Vdd is connected with the drain electrode of the sixth MOS tube M6 through the current source I, the gate electrode of the sixth MOS tube M6 is coupled to a voltage source 2 through a fifth resistor R5 to receive bias voltage VG, the source electrode of the sixth MOS tube M6 is connected with the MOS drain electrode of the fifth MOS tube M5, the source electrode of the fifth MOS tube M5 is grounded, the gate electrode of the fifth MOS tube M5 is connected with the drain electrode of the sixth MOS tube M6 to output first voltage VG 24, the first voltage VG 24 is connected with the source electrode of the third MOS tube M2 through a third MOS tube M2, and the gate electrode of the fifth MOS tube M2 is connected with the gate electrode VG 9, The source of the fourth MOS transistor M4 is grounded, the drain of the third MOS transistor M3 is connected to the source of the seventh MOS transistor M7, the drain of the fourth MOS transistor M4 is connected to the source of the eighth MOS transistor M8 through the first resistor R1 and outputs a second voltage VG2b, the drains of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the supply voltage Vdd, and the gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to each other.
Furthermore, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are NMOS transistors.
Furthermore, the seventh MOS transistor M7 and the eighth MOS transistor M8 are PMOS transistors.
The invention has the beneficial effects that: the common-gate tube is biased by adopting a mode that the current of a current source flows into a combined system of the resistor and the MOS tube to generate a bias voltage, so that the change of the quiescent current of the amplifier along with the change of the power voltage, the resistor and the threshold of the MOS device in different batches can be greatly reduced, and the stability of various characteristics of the amplifier is improved.
Drawings
FIG. 1 is a prior art cascode RF low noise amplifier common-gate transistor bias circuit diagram;
fig. 2 is a bias circuit diagram for a cascode rf low noise amplifier common-gate transistor according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawing figures.
As shown in fig. 2, a bias circuit for a cascode transistor of a cascode radio frequency low noise amplifier includes a cascode radio frequency low noise amplifier amplifying circuit composed of a first MOS transistor M1, a second MOS transistor M2, inductors Lg, Ls, Ld, capacitors Cgs, Cd, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, and further includes a bias voltage generating circuit including a current source I, a sixth MOS transistor M6, a fifth MOS transistor M5, a third MOS transistor M3, a fourth MOS transistor M4, a seventh MOS transistor M7, an eighth MOS transistor M8, a first resistor R1, a fifth resistor R638, a second resistor R2, a power supply voltage is connected to a drain of the sixth MOS transistor M6 through the current source I, a gate of the sixth MOS transistor M6 is coupled to a voltage source VG2 through the fifth MOS transistor R5 to receive a bias voltage VG, a drain of the sixth MOS transistor M4642 is connected to a source of the fifth MOS transistor M5, the grid electrode of the fifth MOS transistor M5 is connected with the drain electrode of the sixth MOS transistor M6 to output a first voltage VG1, the first voltage VG1 is connected with the grid electrode of the third MOS transistor M3 through a second resistor R2, the source electrode of the third MOS transistor M3 and the source electrode of the fourth MOS transistor M4 are grounded, the drain electrode of the third MOS transistor M3 is connected with the source electrode of the seventh MOS transistor M7, the drain electrode of the fourth MOS transistor M4 is connected with the source electrode of the eighth MOS transistor M8 through a first resistor R1 to output a second voltage VG2b, the drain electrodes of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected with a power supply voltage Vdd, and the grid electrodes of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected.
The bias voltage generating circuit comprises a bias voltage generating circuit of a first-stage NMOS amplifying tube (common source tube) and a bias voltage generating circuit of a second-stage NMOS tube (common gate tube), wherein the bias voltage generating circuit of the second-stage common gate tube can reduce the change of the current of the bias voltage generating circuit of the first-stage common source tube along with the power voltage Vdd, the resistance and the MOS tube process angle.
The voltage VG2b generated by the circuit composed of the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7, the eighth MOS transistor M8, the first resistor R1 and the second resistor R2 replaces the voltage VG2c generated by the conventional amplifier bias circuit, and the voltage VG2b is connected to VG2 as the bias voltage of the amplifier common-gate transistor.
In the bias circuit provided by the invention
Vce=Vbg*R1/Rb+Vod_M4+Vth_M4-Vod_MN2-Vth_MN2-Veg
Vig=Vbg*R1/Rb+Vod_M4+Vth_M4-Vod_MN6-Vth_MN6
Vbg is a reference voltage, Vod _ M4 and Vth _ M4 are an overdrive voltage and a threshold voltage of the fourth MOS transistor M4, respectively, and since the threshold voltages of the devices of the same type are equal under an ideal condition in a first order approximation, the voltage formula becomes as follows:
Vce=Vbg*R1/Rb+Vod_M4-Vod_MN2-Veg
Vig=Vbg*R1/Rb+Vod_M4-Vod_M6
because the overdrive voltage of the device depends on the bias current and the size of the device, the drain-source voltage Vce of the first MOS transistor M1, the drain-source voltage Vig of the fifth MOS transistor M5 and the power voltage Vdd, the resistance and the threshold voltage of the device are irrelevant.
The working principle of the invention is as follows: external bias current flows into the first resistor R1 and the fourth MOS transistor M4 after being mirrored through the fifth MOS transistor M5/the third MOS transistor M3 and the seventh MOS transistor M7/the eighth MOS transistor M8 to generate a voltage VG2b, and the voltage is directly connected to VG2 to be used as bias voltage of the amplifier common-gate transistor second MOS transistor M2, so that the grid voltage of the transistor is ensured to change along with the threshold voltage change of the MOS transistor, the change caused by the bias current generation resistance change is eliminated, the voltage of the drain terminal c of the first MOS transistor M1 is ensured not to change along with the threshold value change of the MOS transistor and the change of the resistor R, the stability of the bias state of the amplifier circuit is ensured, and the performance stability of the amplifier circuit is improved.
The invention can replace the corresponding MOS device with the corresponding BJT device when in application.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. A biasing circuit for a common-gate tube of a cascode radio-frequency low-noise amplifier comprises a cascode radio-frequency low-noise amplifier amplifying circuit, and is characterized in that: the circuit also comprises a bias voltage generating circuit, the circuit comprises a current source (I), a sixth MOS tube (M6), a fifth MOS tube (M5), a third MOS tube (M3), a fourth MOS tube (M4), a seventh MOS tube (M7), an eighth MOS tube (M8), a first resistor (R1), a fifth resistor (R5) and a second resistor (R2), a power supply voltage (Vdd) is connected with the drain electrode of the sixth MOS tube (M6) through the current source (I), the gate electrode of the sixth MOS tube (M6) is coupled to a voltage source (VG 2) through the fifth resistor (R5) to receive the bias voltage, the source electrode of the sixth MOS tube (M6) is connected with the drain electrode of the fifth MOS tube (M5), the source electrode of the fifth MOS tube (M5) is grounded, the gate electrode of the fifth MOS tube (M5) is connected with the drain electrode of the sixth MOS tube (M6) to output the first voltage (VG 1), and the gate electrode of the first MOS tube (M3) is connected with the third MOS tube (VG 1), the source electrode of the third MOS tube (M3), the source electrode of the fourth MOS tube (M4) are grounded, the drain electrode of the third MOS tube (M3) is connected with the source electrode of the seventh MOS tube (M7), the drain electrode of the fourth MOS tube (M4) outputs a second voltage (VG 2 b) after being connected with the source electrodes of the first resistor (R1) and the eighth MOS tube (M8), the drain electrodes of the seventh MOS tube (M7) and the eighth MOS tube (M8) are connected with a power supply voltage (Vdd), and the gate electrodes of the seventh MOS tube (M7) and the eighth MOS tube (M8) are connected.
2. The bias circuit for the cascode radio frequency low noise amplifier common-gate tube according to claim 1, wherein: the third MOS transistor (M3), the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the sixth MOS transistor (M6) are NMOS transistors.
3. The bias circuit for the cascode radio frequency low noise amplifier common-gate tube according to claim 1, wherein: the seventh MOS transistor (M7) and the eighth MOS transistor (M8) are PMOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110376884.0A CN113114117A (en) | 2021-04-08 | 2021-04-08 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110376884.0A CN113114117A (en) | 2021-04-08 | 2021-04-08 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
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