CN111478687B - High-precision current-limiting load switch circuit - Google Patents
High-precision current-limiting load switch circuit Download PDFInfo
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- CN111478687B CN111478687B CN202010342024.0A CN202010342024A CN111478687B CN 111478687 B CN111478687 B CN 111478687B CN 202010342024 A CN202010342024 A CN 202010342024A CN 111478687 B CN111478687 B CN 111478687B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
Abstract
The invention discloses a high-precision current-limiting load switch circuit, which is connected between a power supply and a load and mainly solves the problems of low precision and low response speed of the conventional current-limiting load switch circuit. The current-limiting load switching circuit includes: a reference current unit (1), a current limit detection unit (2) and a load switch unit (3); the reference current unit is used for generating a stable reference current signal and setting a limiting current; the current-limiting detection unit is used for detecting load current and outputting bias voltage to drive an NMOS load switch; the load switch unit has small on-resistance when working in a deep linear region, and has higher power utilization efficiency. In addition, the operational amplifier for the current-limiting detection unit has lower offset voltage and higher slew rate, so that the current-limiting load switch circuit has the characteristics of high precision and high response speed, and can be used in an intelligent and integrated power management system.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a load switch integrated circuit with current limiting protection, which can be used in a power management system.
Background
The current-limiting load switch circuit is an important component of a protection circuit in a power management system. When the circuit has overload and short-circuit faults, the load current reaches a plurality of amperes, and the accurate current limiting circuit is needed to provide protection for the power tube and the input power supply, so that the research on the current limiting load switch circuit with high accuracy and the overcurrent protection function has important value in an integrated power supply management system.
Since a high open loop gain operational amplifier circuit is required in the current limited load switch to form the detection feedback loop, the design of the amplifier will affect the performance of the current limited load switch. The conventional amplifier structure has the following disadvantages: (1) The two-stage operational amplifier structure can provide high gain, but the stability is improved by adopting a Miller capacitance compensation method, so that the slew rate of the operational amplifier is reduced, and the response speed of a current-limiting load switch circuit is influenced; (2) The traditional operational amplifier has certain offset voltage due to the problems of design and process, and the current limiting precision is influenced when the traditional operational amplifier is used in a current limiting load switch circuit; (3) A sufficiently high gate driving voltage cannot be supplied when the load is normal.
Disclosure of Invention
The invention aims to provide a two-stage operational amplifier structure with low offset and high slew rate, which realizes a high-precision and quick-response load switch circuit and can be used for current-limiting protection of a load.
In order to achieve the purpose, the technical scheme of the invention is as follows: a high-precision current-limiting load switch circuit is characterized in that: the device comprises a reference current unit 1, a current limiting detection unit 2 and a load switch unit 3; wherein:
the reference current unit 1 generates a stable reference current I LIMIT For setting a current limit threshold of the current limit load switching circuit; the input terminal of the module is connected with an internal reference voltage V REF The output end of the current limiting circuit outputs a limiting current I LIMIT To the current limit detection unit 2;
the current limiting detection unit 2 is used for detecting the load current I LOAD Comparing the magnitude of the load current with the magnitude of the limiting current; the first input end of the module is connected with a limiting current I LIMIT The second input end is connected with a load current I LOAD The third input end is connected with an input power supply V IN An output terminal of the output terminal outputs a bias voltage V BIAS The load switch unit 3 is used for biasing the load switch tube in a reasonable working area;
the load switch unit 3 is equivalent to a lead to enable a load to be connected with a power supply when the load current is normal, and is equivalent to a current source to provide constant current for the load when the load current exceeds the limit; the input end of the module is connected with a bias voltage V BIAS A first output terminal thereof outputting a load current I LOAD To the current-limiting detection unit 2, a second output terminal is connected with an output voltage V OUT 。
Preferably, the reference current unit 1 includes a first operational amplifier OP1, an NMOS transistor M1 and a resistor R1; wherein: the positive phase end of the first operational amplifier OP1 is used as the input end of the reference current unit 1 to be connected with the reference voltage V REF The output end of the first operational amplifier OP1 is connected with the gate end of the first NMOS tube M1, the source end of the first NMOS tube M1 is connected with the negative phase end of the first operational amplifier OP1, and the drain end of the first NMOS tube M1 is used as the referenceThe output end of the current unit 1 outputs a limiting current I LIMIT (ii) a The first resistor R1 is bridged between the source end of the first NMOS tube M1 and the ground.
Preferably, the current-limiting detection unit 2 includes a second operational amplifier OP2, and three resistors R2, R3, and R4; wherein: one end of the second resistor R2 is used as a first input end of the current limiting detection unit 2 to be connected with the limiting current I LIMIT The other end of the current limiting detection unit 2 is connected with a chip input power supply V as a third input end of the current limiting detection unit IN (ii) a One end of the third resistor R3 is used as a second input end of the current limiting detection unit 2 to be connected with the load current I LOAD The other end is connected with a power supply voltage V IN ；
The non-inverting terminal of the second operational amplifier OP2 is connected with a limiting current I LIMIT The negative phase end is connected with one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected with the load current I LOAD The output end of the second operational amplifier OP2 is used as the output end of the current-limiting detection unit 2 to output the bias voltage V BIAS 。
Preferably, the load switch unit 3 includes a second NMOS transistor M2, wherein: the grid end of the second NMOS tube M2 is used as the input end of the load switch unit 3 and is connected with a bias voltage V BIAS The source end of the current-limiting load switch circuit is used as the output end of the whole current-limiting load switch circuit and outputs a voltage V OUT The drain terminal of which outputs a load current I LOAD 。
Preferably, the first-stage amplifier 21 of the second operational amplifier OP2 includes two triodes Q1 and Q2, three PMOS transistors M3, M4 and M5, four NMOS transistors M6, M7, M8 and M9, two resistors R5, R6 and R7, and a current source I S1 (ii) a Wherein: the base electrodes of the first PNP triode Q1 and the second PNP triode Q2 are connected to form a differential structure, the emitting electrode of the first PNP triode Q1 serves as a first input end of a first-stage amplifier 21, the collecting electrode of the first PNP triode Q1 is connected with the source end of a third PMOS tube M3, the emitting electrode of the second PNP tube Q2 serves as a second input end of the first-stage amplifier 21, and the collecting electrode of the second PNP tube Q2 is connected with the source end of a fourth PMOS tube M4; the grid end of the third PMOS tube M3 is connected with the drain end thereof to form a diode structure and is connected with the grid end of the fourth PMOS tube M4, and the drain end of the fourth PMOS tube M4 is connected with the drain end of the seventh NMOS tube M7 and is used as a first-stage amplifierAn output of the amplifier 21; the first current source I S1 The base electrode of the first PNP tube Q1 is bridged between a power supply voltage VDD; the source end of the fifth PMOS transistor M5 is connected to the base of the first PNP transistor Q1, the gate end thereof is connected to the gate end of the third PMOS transistor M3, and the drain end thereof is connected to ground through a seventh resistor R7; the sixth NMOS transistor M6 is connected with the gate terminal of the seventh NMOS transistor M7 and is connected with an internal first bias voltage V B1 A drain terminal of the sixth NMOS transistor M6 is connected to a drain terminal of the third NMOS transistor M3 and serves as a third input terminal of the first-stage amplifier 21, a source terminal of the sixth NMOS transistor M6 is connected to a drain terminal of the eighth NMOS transistor M8, a source terminal of the seventh NMOS transistor M7 is connected to a drain terminal of the ninth NMOS transistor M9, and the eighth NMOS transistor M8 is connected to a gate terminal of the ninth NMOS transistor M9 and is connected to an internal second bias voltage V B2 The source terminal of the eighth NMOS transistor M8 is connected to ground through a fifth resistor R5, and the source terminal of the ninth NMOS transistor M9 is connected to ground through a sixth resistor R6.
Preferably, the second-stage amplifier 22 of the second operational amplifier OP2 includes four PMOS transistors M12, M13, M14, M15, two NMOS transistors M11, M21, and a current source I S3 (ii) a Wherein: the gate end of the eleventh NMOS transistor M11 serves as the input end of the second-stage amplifier 22, the drain end of the eleventh NMOS transistor M11 is connected to the source end of the twenty-first NMOS transistor M21, the gate end of the eleventh NMOS transistor M11 serves as the output end of the second-stage amplifier 22, and the source end of the eleventh NMOS transistor M11 is connected to the ground; the twelfth PMOS tube M12, the thirteenth PMOS tube M13, the fourteenth PMOS tube M14 and the fifteenth PMOS tube M15 form a cascode current mirror structure, and source ends of the twelfth PMOS tube M12 and the thirteenth PMOS tube M13 are connected and connected with a charge pump voltage V PUMP The grid electrode of the thirteenth PMOS tube M13 is connected with the source end of the fifteenth PMOS tube M15; the grid end of the fourteenth PMOS tube M14 is connected with the grid end of the fifteenth PMOS tube M15, and the grid end of the fourteenth PMOS tube M14 is connected with the drain end of the fourteenth PMOS tube M14 and is connected with a third current source I S3 Its source end is connected with the drain end of the twelfth PMOS tube M12, and a third current source I S3 Is connected to ground; the drain terminal of the twenty-first NMOS transistor M21 is connected to the drain terminal of the fifteenth PMOS transistor M15, and the gate terminal thereof is connected to the power supply voltage VDD.
Preferably, the frequency compensation circuit 23 of the second operational amplifier OP2 comprises oneAn NPN transistor Q3, an NMOS transistor M10, a current source I S2 (ii) a Wherein: the base of the third NPN transistor Q3 is connected with the drain of the tenth NMOS transistor M10, and the input end serving as the frequency compensation 23 is connected with the voltage V A The emitter of which is connected to the voltage V as the output of the frequency compensation 23 B The collector of the power supply is connected with a power supply voltage VDD; the grid end of the tenth NMOS tube M10 is connected with a second current source I S2 Has its source terminal connected to ground, a second current source I S2 Is connected to ground.
Preferably, the current compensation circuit 24 of the second operational amplifier OP2 includes an NPN transistor Q4, five NMOS transistors M16, M17, M18, M19, and two current sources I S4 、I S5 (ii) a Wherein: the gate end of the sixteenth NMOS tube M16 is connected with the gate end of the seventeenth NMOS tube M17, the gate end of the eighteenth NMOS tube M18 is connected with the gate end of the nineteenth NMOS tube M19 to form a cascode current mirror structure, the gate end of the sixteenth NMOS tube M16 is connected with the drain end of the sixteenth NMOS tube M16 and is connected with the fifth current source I S5 A source terminal of the negative terminal of (1) is connected to a drain terminal of the eighteenth NMOS transistor M18, and a drain terminal of the seventeenth NMOS transistor M17 serves as a first output terminal of the current compensation 24 to output a first compensation current I 1 The source end of the NMOS transistor is connected with the drain end of a nineteenth NMOS transistor M19; the source end of the eighteenth NMOS transistor M18 and the source end of the nineteenth NMOS transistor M19 are commonly connected to the ground; the fifth current source I S5 The positive terminal of the voltage regulator is connected with a power supply voltage VDD;
the grid end of the twentieth NMOS tube M20 is connected with a fourth current source I S4 A source terminal of the negative terminal is connected with a base electrode of a fourth NPN tube Q4, and a drain terminal of the negative terminal is used as a second output terminal of the current compensation 24 to output a second compensation current I 2 (ii) a The fourth current source I S4 The positive terminal of the fourth NPN transistor Q4 is connected to the power supply voltage VDD, the collector of the fourth NPN transistor Q4 is connected to the gate terminal of the twentieth NMOS transistor M20, and the emitter thereof is connected to ground.
Compared with the prior art, the invention has the following advantages:
1. the current limiting precision of the load switch circuit provided by the invention is mainly determined by a reference voltage V REF The offset of the first operational amplifier OP1 and the second operational amplifier OP2 is affected, wherein the offset voltage of the OP2 plays a major role, the invention provides the circuit structure of the OP2 with more advantagesLow offset voltage to improve the current limiting precision of the whole circuit.
2. The second operational amplifier OP2 does not adopt a Miller capacitance compensation method, so that the slew rate of the operational amplifier is improved, and the response speed of a current-limiting load switch is improved.
3. The load switch provided by the invention uses the NMOS power tube, compared with the PMOS tube, the NMOS tube has higher carrier mobility, and has smaller on-resistance when working in a deep linear region; in addition, the resistance value of the current-limiting detection resistor is very small, so that the on-resistance of the whole load switch is smaller, and the utilization efficiency is higher.
Drawings
Fig. 1 is a schematic structural diagram of a load switch.
Fig. 2 is a schematic structural diagram of the present invention.
FIG. 3 is a schematic diagram of an operational amplifier according to the present invention
FIG. 4 is a specific circuit diagram of an operational amplifier according to the present invention.
Detailed Description
The embodiments of the present invention will be further described below with reference to the drawings.
Referring to fig. 1, the present invention provides a load switching circuit including: a reference current unit 1, a current limit detection unit 2 and a load switch unit 3; wherein the reference current unit 1 is provided with an input terminal connected to a reference voltage V REF Is provided with an output end for outputting a reference current I LIMIT (ii) a The current-limiting detection unit 2 is provided with three input ends which are respectively connected with a middle reference current I LIMIT Load current I LOAD And an input power supply V IN Is provided with an output end for outputting a bias voltage V BIAS (ii) a The load switch unit 3 has an input terminal connected to a bias voltage V BIAS Two output terminals respectively connected to the load current I LOAD And a load voltage V OUT 。
The reference current unit 1 is used for generating a stable reference current for setting a current limiting threshold; the current limiting detection unit 2 is used for comparing the reference current I LIMIT And the load current I of the power tube LOAD Providing gate drive when load current is normal or excessiveThe voltage changes the working state of the power tube; the load switch unit 3 is used for providing current for the load, when the power tube works in a deep linear region, the load is connected to a power supply, and when the power tube works in a saturation region, the power tube provides limited current for the load.
Referring to fig. 2, the reference current unit 1 includes a first operational amplifier OP1, an NMOS transistor M1, and a resistor R1; wherein: the positive phase end of the first operational amplifier OP1 is used as the input end of the reference current unit 1 and is connected with the reference voltage V REF The output end of the first operational amplifier OP1 is connected with the gate end of the first NMOS tube M1, the source end of the first NMOS tube M1 is connected with the negative phase end of the first operational amplifier OP1, and the drain end of the first NMOS tube M1 is used as the output end of the reference current unit 1 to output the limiting current I LIMIT (ii) a The first resistor R1 is connected between the source end of the first NMOS transistor M1 and the ground in a bridging mode.
Reference voltage V by zero temperature coefficient REF Generating stable reference current I with resistor R1 LIMIT 。
The virtual short of the first operational amplifier OP1 indicates that:
the current limiting threshold of the whole circuit can be adjusted by changing the size of the first resistor R1.
Referring to fig. 2, the current limiting detection unit 2 includes a second operational amplifier OP2, and three resistors R2, R3, and R4; wherein: one end of the second resistor R2 is connected with a limiting current I LIMIT The other end is connected with a power supply voltage V IN (ii) a One end of the third resistor R3 is connected with a load current I LOAD The other end is connected with an input power supply V IN (ii) a The non-inverting terminal of the second operational amplifier OP2 is connected with a limiting current I LIMIT The negative phase end is connected with one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected with the load current I LOAD The second operational amplifier OP2 outputs a bias voltage V BIAS 。
Because the second operational amplifier OP2 adopts the triode emitter as input and has input bias current, the fourth resistor R4 is introduced to ensure that the second operational amplifier OP2 meets the virtual short condition when balanced, and the resistance values of the second resistor R2 and the fourth resistor R4 are about 1 kohm. As known from the virtual short of the second OP2,
V A ＝V B -R 4 ·I BIAS2 (2)
V A ＝V IN -R 2 ·(I LIMIT +I BIAS1 ) (3)
V B ＝V IN -R 3 ·(I LOAD +I BIAS2 ) (4)
when the second resistor R2 and the fourth resistor R4 are matched, the input bias current I of the OP2 BIAS1 And I BIAS2 When matching, the load current limit value obtained by combining the formulas (1), (2), (3) and (4) is as follows:
referring to fig. 2, the load switch unit 3 includes a second NMOS transistor M2, wherein: the grid end of the second NMOS tube M2 is connected with a bias voltage V BIAS The source end of the second NMOS tube M2 is connected with a load, and the drain end of the second NMOS tube M2 outputs a load current I LOAD 。
The load switch unit 3 adopts a second NMOS transistor M2 as a switch transistor, and the on-resistance of the load switch unit operating in the deep linear region is:
wherein, mu n Is the mobility of NMOS tube carriers, C OX Is the gate oxide capacitance per unit area, W and L are the width and length, V, respectively, of the second NMOS transistor M2 GS -V TH Is the overdrive voltage of the second NMOS transistor M2; compared with a PMOS (P-channel metal oxide semiconductor) tube, the NMOS tube has high carrier mobility and low on-resistance when the NMOS tube works in a deep linear region under the same area, so that the load switch provided by the invention adopts the NMOS tube; in addition, the resistance value of the current-limiting detection resistor R3 is small and can be ignored, and when the load current is normal, the on-resistance from the power supply to the load is small, so that the utilization rate of the power supply is improved.
Referring to fig. 4, the second operational amplifier OP2 includes four transistors Q1, Q2, Q3, Q4, seven PMOS transistors M3, M4, M5, M12, M13, M14, M15, twelve NMOS transistors M6, M7, M8, M9, M10, M11, M16, M17, M18, M19, M20, M21, three resistors R5, R6, R7, and five current sources I S1 、I S2 、I S3 、I S4 、I S5 (ii) a Wherein:
the base electrodes of the first PNP triode Q1 and the second PNP triode are connected to form a differential structure, the emitting electrode of the first PNP triode Q1 serves as the first input end of the first-stage amplifier 21, and the collecting electrode of the first PNP triode Q1 is connected with the source end of the third PMOS tube M3; the emitter of the second PNP transistor Q2 serves as the second input terminal of the first-stage amplifier 21, the collector thereof is connected to the source terminal of the fourth PMOS transistor M4, the gate terminal of the third PMOS transistor M3 is connected to the drain terminal thereof to form a diode structure and is connected to the gate terminal of the fourth PMOS transistor M4, and the drain terminal of the fourth PMOS transistor M4 is connected to the drain terminal of the seventh NMOS transistor M7 and serves as the output terminal of the first-stage amplifier 21; the first current source I S1 The base electrode of the first PNP tube Q1 is bridged between a power supply voltage VDD; the source end of the fifth PMOS tube M5 is connected with the base electrode of the first PNP tube Q1, the grid end of the fifth PMOS tube M5 is connected with the grid end of the third PMOS tube M3, the drain end of the fifth PMOS tube M3 is connected with the ground through a seventh resistor R7, the sixth NMOS tube M6 is connected with the grid end of the seventh NMOS tube M7 and is connected with the internal first bias voltage V B1 The drain terminal of the sixth NMOS transistor M6 is connected to the drain terminal of the third NMOS transistor M3 and serves as the third input terminal of the first-stage amplifier 21, the source terminal of the sixth NMOS transistor M6 is connected to the drain terminal of the eighth NMOS transistor M8, and the source terminal of the seventh NMOS transistor M7 is connected to the drain terminal of the ninth NMOS transistor M9; the eighth NMOS transistor M8 is connected with the gate terminal of the ninth NMOS transistor M9 and is connected with an internal second bias voltage V B2 The source end of the eighth NMOS transistor M8 is connected to ground through a fifth resistor R5, and the source end of the ninth NMOS transistor M9 is connected to ground through a sixth resistor R6;
the gate end of the eleventh NMOS transistor M11 serves as the input end of the second-stage amplifier 22, the drain end of the eleventh NMOS transistor M11 is connected to the source end of the twenty-first NMOS transistor M21, the gate end of the eleventh NMOS transistor M11 serves as the output end of the second-stage amplifier 22, and the source end of the eleventh NMOS transistor M11 is connected to the ground; a twelfth PMOS tube M12, a thirteenth PMOS tube M13, a fourteenth PMOS tube M14 and a fifteenth PMOS tube M15 form a cascode current mirror structure;the source ends of the twelfth PMOS tube M12 and the thirteenth PMOS tube M13 are connected and connected with the charge pump voltage V PUMP The grid electrode of the thirteenth PMOS tube is connected with the grid end of the twelfth PMOS tube M12, the grid end of the twelfth PMOS tube M12 is connected with the drain end of the twelfth PMOS tube, and the drain end of the thirteenth PMOS tube M13 is connected with the source end of the fifteenth PMOS tube M15; the grid ends of the fourteenth PMOS tube M14 and the fifteenth PMOS tube M15 are connected, the grid end of the fourteenth PMOS tube M14 is connected with the drain end thereof and is connected with the third current source I S3 The source end of the positive end of the transistor is connected with the drain end of the twelfth PMOS transistor M12; the third current source I S3 Is connected to ground; the drain end of the twenty-first NMOS transistor M21 is connected with the drain end of the fifteenth PMOS transistor M15, and the grid end of the twenty-first NMOS transistor is connected with the power supply voltage VDD;
the base of the third NPN transistor Q3 is connected with the drain of the tenth NMOS transistor M10, and the input end serving as the frequency compensation 23 is connected with the voltage V A The emitter of which is connected to the voltage V as the output of the frequency compensation 23 B The collector of the power supply is connected with a power supply voltage VDD; the grid end of the tenth NMOS tube M10 is connected with a second current source I S2 The source end of the positive terminal of (2) is connected with the ground; the second current source I S2 Is connected to ground.
The sixteenth NMOS tube M16 is connected with the gate end of the seventeenth NMOS tube M17, and the eighteenth NMOS tube M18 is connected with the gate end of the nineteenth NMOS tube M19 to form a cascode current mirror structure; the gate terminal of the sixteenth NMOS transistor M16 is connected to the drain terminal thereof and connected to a fifth current source I S5 A source terminal of the negative terminal of the transistor is connected to a drain terminal of the eighteenth NMOS transistor M18, and a drain terminal of the seventeenth NMOS transistor M17 is used as a first output terminal of the current compensation 24 to output a first compensation current I 1 The source end of the NMOS transistor is connected with the drain end of a nineteenth NMOS transistor M19; the source end of the eighteenth NMOS transistor M18 and the source end of the nineteenth NMOS transistor M19 are commonly connected to the ground, and a fifth current source I S5 The positive terminal of the voltage regulator is connected with a power supply voltage VDD; the gate end of the twentieth NMOS tube M20 is connected with a fourth current source I S4 A source terminal of the negative terminal is connected with a base electrode of a fourth NPN tube Q4, and a drain terminal of the negative terminal is used as a second output terminal of the current compensation 24 to output a second compensation current I 2 A fourth current source I S4 The positive terminal of the fourth NPN transistor Q4 is connected to the power supply voltage VDD, the collector of the fourth NPN transistor Q4 is connected to the gate terminal of the twentieth NMOS transistor M20, and the emitter thereof is connected to ground.
The input geminate transistor of the second operational amplifier OP2 adopts a PNP tube, certain base current exists during normal work, and in order to reduce the error of collector current of the first PNP tube Q1 and the second PNP tube Q2, a fifth NMOS tube M5 is added to provide base current, so that the influence of beta is reduced; v of a third NPN transistor Q3 is added between the grid and drain ends of a tenth NMOS transistor M10 BE The seventh NMOS tube M7 and the ninth NMOS tube M9 work in a saturation region by voltage; in order to enable the second NMOS transistor M2 to work in a deep linear region when being conducted, the potential of the output end of the second operational amplifier needs to be higher than the power supply potential when outputting a high level, therefore, a cascode current mirror load taking the charge pump voltage as the power supply is introduced into a second-stage amplifier of the second operational amplifier OP2, and the level shift function is realized, because V is PUMP The voltage is higher, so a twenty-first NMOS high-voltage tube M21 is added to protect the M11 tube; the base current of the third NPN transistor Q3 and the leakage current of the tenth NMOS transistor M10 make the currents of the left and right branches of the second operational amplifier OP2 unequal in a balanced state, so that the current of the left branch of the cascode amplifier needs to be compensated, and the compensation current is determined according to the base current of the third NPN transistor Q3 and the leakage current of the tenth NMOS transistor M10, so as to ensure that the second operational amplifier Q2 is in a balanced state when working normally.
The current-limiting detection unit adopts a negative feedback structure, when the load current is small, the positive-phase voltage of the second operational amplifier OP2 rises, the output voltage rises along with the voltage, and the second NMOS tube M2 is driven to work in a linear region; on the contrary, when the load current exceeds the limit, the second NMOS transistor M2 finally operates in the saturation region after negative feedback, and can provide a constant current of the magnitude of the current-limiting threshold for the load.
The second NMOS transistor M2 has a large size, so that a large gate-source parasitic capacitance exists, and the output impedance of the first-stage amplifier 21 of the second operational amplifier OP2 is large, so that the output poles of the first-stage amplifier 21 and the second-stage amplifier 22 are close to each other, the phase margin of the operational amplifier is reduced, and the stability of the operational amplifier is deteriorated. Therefore, the diode structure formed by the tenth NMOS transistor M10 is used to reduce the output impedance of the first-stage amplifier 21, so as to separate the positions of the two poles to complete frequency compensation, and the positions of the major and minor poles after compensation are:
wherein C1 is an equivalent capacitance of the output terminal of the second-stage amplifier 22 to ground, and C2 is an equivalent capacitance of the output terminal of the first-stage amplifier 21 to ground. Compared with a compensation method of bridging a Miller capacitor between the traditional two-stage amplifier, the method can effectively improve the slew rate of the operational amplifier, and can quickly respond to drive the second NMOS transistor M2 to work in a saturation region when the load current is abnormal.
The precision of the current-limiting load switch circuit provided by the invention is mainly influenced by V REF Offset voltage influence of the reference voltage and the operational amplifiers OP1 and OP 2. Consider OP1 and V REF Total offset voltage V OS1 Offset voltage V of OP2 OS2 Thus, it can be seen that:
because the resistance value of R3 is very small, the offset voltage of OP2 can seriously affect the current-limiting precision according to the formula (10), the OP2 operational amplifier circuit provided by the invention has small offset voltage, and the current-limiting precision of the whole load switch circuit can be improved.
The offset voltage of OP2 is derived from input pair Q1, Q2 mismatch, current mirror load M8 and M9 mismatch, resistor R5 and R6 mismatch, and current compensation mismatch. The base-emitter offset voltage of the PNP type input pair transistor is in direct proportion to offset of bias current, so mismatch of current mirror load and mismatch of resistors R5 and R6 need to be reduced, compared with single-tube current mirror transconductance, equivalent transconductance of a common source stage with source electrode negative feedback formed by M8 and M9 and R5 and R6 is smaller, current generated by M8 and M9 mismatch can be reduced, and mismatch current caused by increased self mismatch of the resistors R5 and R6 is reduced due to increased equivalent transconductance. To sum up, the second OP-amp OP2 has a very small offset voltage.
In summary, the present invention provides a current-limiting load switch circuit, which adopts a two-stage operational amplifier structure with low offset and high slew rate to improve the current-limiting precision and the response speed of a load switch, and is suitable for an integrated power management system.
The above is only the best example of the present invention, and does not constitute any limitation to the present invention, and it is obvious that various changes and modifications can be made to the circuit thereof under the concept of the present invention, but these are all protected by the present invention.
Claims (6)
1. A high accuracy current limiting load switching circuit comprising: the circuit comprises a reference current unit (1) and a load switch unit (3), and is characterized by further comprising a current limiting detection unit (2);
the reference current unit (1) is used for generating a stable reference current signal to set a threshold value of current limiting detection; the input end of the reference current unit (1) is connected with an internal reference voltage V REF The output end of the current limiting circuit outputs a limiting current I LIMIT To a current limit detection unit (2); the reference current unit (1) comprises a first operational amplifier OP1, a first NMOS transistor M1 and a first resistor R1; wherein: the positive phase end of the first operational amplifier OP1 is used as the input end of the reference current unit (1) to be connected with a reference voltage V REF The output end of the first operational amplifier OP1 is connected with the gate end of the first NMOS tube M1; the source end of the first NMOS tube M1 is connected with the negative phase end of the first operational amplifier OP1 module, and the drain end of the first NMOS tube M1 is used as the output end of the reference current unit (1) to output a limiting current I LIMIT (ii) a The first resistor R1 is bridged between the source end of the first NMOS transistor M1 and the ground;
the current limiting detection unit (2) is used for detecting the load current I LOAD Comparing the magnitude of the load current with the magnitude of the limiting current; the first input end of the current-limiting detection unit (2) is connected with a limiting current I LIMIT The second input end is connected with a load current I LOAD The third input end is connected with an input voltage V IN The output terminal of which outputs a bias voltage V BIAS To the load switch unit (3), the load switch tube is biased in a reasonable working area; the current limiting detection unit (2) comprises a second operational amplifier OP2, a second resistor R2, a third resistor R3 and a third resistorA four-resistor R4; wherein: one end of the second resistor R2 is used as a first input end of the current limiting detection unit (2) to be connected with the limiting current I LIMIT The other end of the current limiting detection unit (2) is used as a third input end to be connected with the chip input voltage V IN (ii) a One end of the third resistor R3 is used as a second input end of the current limiting detection unit (2) to be connected with the load current I LOAD The other end is connected with a power supply voltage V IN (ii) a The positive phase end of the second operational amplifier OP2 is connected with a limiting current I LIMIT The negative phase end is connected with one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected with a load current I LOAD The output end of the second operational amplifier OP2 is used as the output end of the current-limiting detection unit (2) to output the bias voltage V BIAS ；
The load switch unit (3) adopts an NMOS power tube as an electronic switch element, the load switch unit is equivalent to a lead wire to enable a load to be connected with a power supply when the load current is normal, and the load switch unit is equivalent to a current source to provide constant current for the load when the load current exceeds the limit; the input end of the load switch unit (3) is connected with a bias voltage V BIAS A first output terminal thereof outputs a load current I LOAD To the current-limiting detection unit (2), the second output end is connected with the output voltage V OUT (ii) a The load switch unit (3) comprises a second NMOS transistor M2, wherein: the grid end of the second NMOS tube M2 is used as the input end of the load switch unit (3) and is connected with a bias voltage V BIAS The source end of the current limiting load switch circuit is used as the output end of the whole current limiting load switch circuit and outputs a voltage V OUT The drain terminal of which outputs a load current I LOAD 。
2. The current-limiting load switching circuit of claim 1, wherein the second OP2 comprises: a first stage amplifier (21), a second stage amplifier (22), a frequency compensation (23) and a current compensation (24);
the current compensation (24) is used for compensating the bias current of the first-stage amplifier (21) and outputs a first compensation current I 1 And a second compensation current I 2 A third input to the first stage amplifier (21);
the first-stage amplifier (21) adopts a differential input single-ended output structure, and a first input end of the first-stage amplifier is used as a first input endPositive input end V of second operational amplifier OP2 P The second input terminal of which is used as the negative phase input terminal V of the second operational amplifier OP2 N Output voltage V of its output terminal A To frequency compensation (23);
the frequency compensation (23), as a frequency compensation part of a two-stage amplifier configuration, has its input connected to a voltage V A Output terminal of which outputs voltage V B To a second stage amplifier (22);
the second-stage amplifier (22) adopts a single-stage amplification structure with level shift, and the output end of the second-stage amplifier is used as the output end of the second operational amplifier OP 2.
3. The current-limiting load switch circuit of claim 2, wherein the first stage amplifier (21) comprises two PNP transistors: a first PNP triode Q1 and a second PNP triode Q2; three PMOS tubes: a third PMOS tube M3, a fourth PMOS tube M4 and a fifth PMOS tube M5; four NMOS tubes: a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9; three resistors: a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7; and a first current source I S1 (ii) a Wherein:
the base electrodes of the first PNP triode Q1 and the second PNP triode Q2 are connected to form a differential structure, the emitting electrode of the first PNP triode Q1 serves as the first input end of the first-stage amplifier (21), and the collecting electrode of the first PNP triode Q1 is connected with the source end of the third PMOS tube M3; an emitter of the second PNP tube Q2 is used as a second input end of the first-stage amplifier (21), and a collector of the second PNP tube Q2 is connected with a source end of a fourth PMOS tube M4;
the grid end of the third PMOS pipe M3 is connected with the drain end of the third PMOS pipe to form a diode structure and is connected with the grid end of a fourth PMOS pipe M4, and the drain end of the fourth PMOS pipe M4 is connected with the drain end of a seventh NMOS pipe M7 and is used as the output end of a first-stage amplifier (21);
the first current source I S1 The base electrode of the first PNP tube Q1 is bridged between a power supply voltage VDD;
the source end of the fifth PMOS tube M5 is connected with the base electrode of the first PNP tube Q1, the grid end of the fifth PMOS tube M5 is connected with the grid end of the third PMOS tube M3, and the drain end of the fifth PMOS tube M5 is connected to the ground through a seventh resistor R7;
the sixth NMOS transistor M6 is connected with the gate terminal of the seventh NMOS transistor M7 and is connected with an internal first bias voltage V B1 The drain terminal of the sixth NMOS tube M6 is connected with the drain terminal of the third NMOS tube M3 and serves as the third input terminal of the first-stage amplifier (21), and the source terminal of the sixth NMOS tube is connected with the drain terminal of the eighth NMOS tube M8; the source end of the seventh NMOS transistor M7 is connected to the drain end of the ninth NMOS transistor M9;
the eighth NMOS transistor M8 is connected with the gate terminal of the ninth NMOS transistor M9 and is connected with an internal second bias voltage V B2 The source end of the eighth NMOS transistor M8 is connected to ground through a fifth resistor R5; the source terminal of the ninth NMOS transistor M9 is connected to ground through a sixth resistor R6.
4. The current-limited load switching circuit of claim 2, wherein the second stage amplifier (22) comprises four PMOS transistors: a twelfth PMOS tube M12, a thirteenth PMOS tube M13, a fourteenth PMOS tube M14 and a fifteenth PMOS tube M15; two NMOS tubes: an eleventh NMOS transistor M11 and a twenty-first NMOS transistor M21; and a third current source I S3 (ii) a Wherein:
the grid end of the eleventh NMOS tube M11 is used as the input end of the second-stage amplifier (22), the drain end of the eleventh NMOS tube is connected with the source end of the twenty-first NMOS tube M21 and is used as the output end of the second-stage amplifier (22), and the source end of the eleventh NMOS tube is connected with the ground;
the twelfth PMOS tube M12, the thirteenth PMOS tube M13, the fourteenth PMOS tube M14 and the fifteenth PMOS tube M15 form a cascode current mirror structure; the source ends of the twelfth PMOS tube M12 and the thirteenth PMOS tube M13 are connected and connected with the charge pump voltage V PUMP The grid electrode of the thirteenth PMOS tube M13 is connected with the source end of the fifteenth PMOS tube M15; the grid ends of the fourteenth PMOS tube M14 and the fifteenth PMOS tube M15 are connected, the grid end of the fourteenth PMOS tube M14 is connected with the drain end thereof and is connected with the third current source I S3 The source end of the positive end of the transistor is connected with the drain end of the twelfth PMOS transistor M12;
the third current source I S3 Is connected to ground;
the drain end of the twenty-first NMOS transistor M21 is connected with the drain end of the fifteenth PMOS transistor M15, and the grid end of the twenty-first NMOS transistor is connected with the power supply voltage VDD;
the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15 and the twenty-first NMOS transistor M21 adopt high-voltage tubes, the drain ends of the high-voltage tubes can resist high voltage, and the rest MOS tubes are common devices of 5V.
5. The current-limiting load switch circuit of claim 2, wherein the frequency compensation (23) comprises a third NPN transistor Q3, a tenth NMOS transistor M10, and a second current source I S2 (ii) a Wherein:
the base electrode of the third NPN tube Q3 is connected with the drain end of a tenth NMOS tube M10, and the base electrode is used as the input end of the frequency compensation (23) and is connected with a voltage V A The emitter of which is connected to a voltage V as the output of the frequency compensation (23) B The collector of the power supply is connected with a power supply voltage VDD;
the grid end of the tenth NMOS tube M10 is connected with a second current source I S2 The source end of the positive end of the switch is connected with the ground; the second current source I S2 Is connected to ground.
6. The current-limiting load switching circuit of claim 2, wherein the current compensation (24) comprises a third NPN transistor Q4; five NMOS tubes: a sixteenth NMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, and a twentieth NMOS transistor M20; two current sources: a fourth current source I S4 A fifth current source I S5 (ii) a Wherein:
the sixteenth NMOS tube M16 is connected with the gate end of the seventeenth NMOS tube M17, and the eighteenth NMOS tube M18 is connected with the gate end of the nineteenth NMOS tube M19 to form a cascode current mirror structure; the gate terminal of the sixteenth NMOS transistor M16 is connected to the drain terminal thereof and connected to a fifth current source I S5 The source end of the negative end of the transistor is connected with the drain end of an eighteenth NMOS transistor M18, and the drain end of a seventeenth NMOS transistor M17 is used as a first output end of the current compensation (24) to output a first compensation current I 1 The source end of the NMOS transistor is connected with the drain end of a nineteenth NMOS transistor M19; the source end of the eighteenth NMOS transistor M18 and the source end of the nineteenth NMOS transistor M19 are commonly connected to the ground;
the fifth current source I S5 The positive terminal of the voltage regulator is connected with a power supply voltage VDD;
the gate end of the twentieth NMOS tube M20 is connected with a fourth current source I S4 A source terminal of the negative terminal is connected with a base electrode of a fourth NPN tube Q4, and a drain terminal of the negative terminal is used as a second output terminal of the current compensation (24) to output a second compensation current I 2 ；
The fourth current source I S4 The positive terminal of the voltage regulator is connected with a power supply voltage VDD;
the collector of the fourth NPN transistor Q4 is connected to the gate of the twentieth NMOS transistor M20, and the emitter thereof is connected to ground.
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| CN114448063B (en) * | 2022-04-11 | 2022-09-06 | 西安航天民芯科技有限公司 | MOSFET drive circuit applied to battery management chip |
| CN116346113B (en) * | 2023-05-23 | 2023-08-11 | 晶艺半导体有限公司 | High-precision current-controlled load switch circuit and trimming method thereof |
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