CN107733404B - Current-limiting detection and protection circuit for NMOS load switch - Google Patents
Current-limiting detection and protection circuit for NMOS load switch Download PDFInfo
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- CN107733404B CN107733404B CN201711000830.4A CN201711000830A CN107733404B CN 107733404 B CN107733404 B CN 107733404B CN 201711000830 A CN201711000830 A CN 201711000830A CN 107733404 B CN107733404 B CN 107733404B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
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Abstract
A current-limiting detection and protection circuit for an NMOS load switch, the load switch comprises an NMOS tube M0, a charge pump CP, a clamping circuit Clamp1 and a resistor R1; the current-limiting detection and protection circuit comprises NMOS transistors M1, M2, M3 and M4, a current reference Iref, a resistor R2, a comparator CMP and a clamping circuit Clamp 2. The output voltage VOUT of the load switch is detected through the voltage division of M1 and M2, the resistance values of M1 and M2 are consistent with the change conditions of temperature, power supply voltage and process, a stable proportional relation can be realized, and the voltage difference value of the power supply voltage VIN and a detection end and the voltage difference value between VIN and VOUT form a fixed proportional relation. Meanwhile, the current-limiting threshold reference voltage is generated by the M3 and the Iref, so that the current-limiting threshold voltage is consistent with the resistance value of the M0 along with the change of temperature, power supply voltage and process, and the stable current-limiting protection current threshold is realized.
Description
Technical Field
The invention relates to a Current-limiting switch, in particular to a Current-limiting detection and protection circuit (Current Sense and Limit) of an NMOS load switch for 5V USB port output.
Background
The output end of the USB port is directly plugged and unplugged towards a user, and the connected electric equipment is complex in condition and easy to generate the conditions of overcurrent and short circuit, so that a load switch with a current-limiting protection function is needed.
Disclosure of Invention
The invention aims to provide a current-limiting detection and protection circuit for an NMOS load switch, which can ensure that a current-limiting protection threshold value is kept stable when factors such as temperature, power supply voltage, process conditions and the like fluctuate, thereby realizing reliable current-limiting protection.
In order to achieve the purpose, the technical scheme of the invention is as follows: a current limit detection and protection circuit for an NMOS load switch, characterized by: the current limiting protection circuit comprises an NMOS load switch and a current limiting detection and protection circuit, wherein the NMOS load switch comprises an NMOS power tube M0, a charge pump CP, a clamping circuit Clamp1 and a resistor R1, the drain electrode of the NMOS power tube M0 is connected with a power supply VIN, the source electrode of the NMOS power tube M0 is connected with the input end of the clamping circuit Clamp1 and serves as an output voltage end VOUT, the output end of the clamping circuit Clamp1 is connected with the grid electrode of the NMOS power tube M0 and one end of the resistor R1, the other end of the resistor R1 is connected with the output end of the charge pump CP, and the input end of the charge pump CP is connected with the power; the current-limiting detection and protection circuit comprises an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a current reference Iref, a resistor R2, a comparator CMP and a clamping circuit Clamp 2; the gate of the NMOS tube M1 is connected to the gate of the NMOS power tube M0 in the NMOS load switch, the source of the NMOS tube M1 is connected to the source of the NMOS power tube M0 in the NMOS load switch, the drain of the NMOS tube M1 is connected to the negative input terminal of the comparator CMP and the source of the NMOS tube M2, the positive input terminal of the comparator CMP is connected to the input terminal of the current reference Iref and the source of the NMOS tube M3 and the input terminal of the Clamp circuit Clamp2, the output terminal of the Clamp circuit Clamp2 is connected to the gate of the NMOS tube M2, the gate of the NMOS tube M3 and one terminal of the resistor R2, the other terminal of the resistor R2 is connected to the output terminal of the charge pump CP in the NMOS load switch, the drain of the NMOS tube M2 is interconnected to the drain of the NMOS tube M3 and connected to the power supply VIN, the output terminal of the current reference Iref is grounded, the output terminal of the comparator CMP is connected to the gate of the NMOS tube M4, the source of the NMOS tube.
The resistor R1 and the resistor R2 are both clamping current-limiting resistors, the resistance values of R1 and R2 are related to the driving capability of the charge pump CP, the resistance values of R1 and R2 are not less than 1.5Mohm so that the output of the charge pump can maintain a sufficiently high voltage, and the resistance value of R2 is less than that of R1 so that the establishment speed of the gate potentials of the NMOS transistors M2 and M3 is faster than that of the gate potentials of the NMOS transistors M0 and M1.
The NMOS transistor M1, the NMOS transistor M2, the NMOS transistor M3 and the NMOS power transistor M0 are all devices of the same type.
The invention has the advantages and obvious effects that: the output voltage VOUT is detected through the partial pressure of the NMOS tubes M1 and M2, and the NMOS tubes M1 and M2 are of the same device type and have the same gate-source voltage bias, so that the resistance values of the NMOS tubes M1 and M2 are consistent with the change of temperature, power supply voltage and process, a stable proportional relation can be realized, and the voltage difference value of VIN and a detection end and the voltage difference value of VIN and VOUT form a fixed proportional relation. Meanwhile, the current-limiting threshold reference voltage is generated by the NMOS transistor M3 and the Iref, and because the NMOS transistor M3 and the power transistor M0 are of the same device type and have the same gate-source voltage bias, the current-limiting threshold voltage and the resistance value of the power transistor M0 can be consistent with the change of temperature, power supply voltage and process, and therefore the stable current-limiting protection current threshold is realized.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a graph of the current limiting protection threshold versus supply voltage of the present invention;
fig. 3 is a graph of current limiting protection threshold versus temperature according to the present invention.
Detailed Description
As shown in fig. 1, PART1 is an NMOS load switch, which includes an NMOS power transistor M0, a charge pump CP, a Clamp circuit Clamp1, and a Clamp current limiting resistor R1. The drain of the NMOS power tube M0 is connected with a power supply VIN, the source of the power tube M0 is connected with an output voltage VOUT and the input end of a clamping circuit Clamp1, the grid of the power tube M0 is connected with one end of a clamping current-limiting resistor R1 and the output end of a clamping circuit Clamp1, and the other end of the resistor R1 is connected with the output of the charge pump CP. During normal operation, the output of the charge pump CP provides a high voltage with limited driving capability, and then the gate potential of the power transistor M0 is clamped to be higher than the source potential by about 4.5V through the clamping current-limiting resistor R1 and the clamping circuit Clamp1, so as to be completely turned on, and M0 operates in a linear region, which is equivalent to a resistor, and is denoted as RM 0. The resistance values of R1 and R2 are selected according to the driving capability of the charge pump CP, and the resistance values of R1 and R2 need not be less than 1.5Mohm, so that the output of the charge pump can maintain a sufficiently high voltage. And the resistance of the R2 should be smaller than that of the R1, so that the gate potentials of the NMOS transistors M2 and M3 can be established faster than those of the NMOS transistors M0 and M1.
The PART of the PART2 is a current-limiting detection and protection circuit, which comprises an NMOS tube M1, M2, M3, M4, a current reference Iref, a clamping circuit Clamp2, a clamping current-limiting resistor R2 and a comparator CMP. The drain of the NMOS tube M2, the drain of the NMOS tube M3 is connected to the power VIN, the gates of the NMOS tubes M2, M3 are connected to one end of the clamping current-limiting resistor R2 and the output end of the clamping circuit Clamp2, the other end of the resistor R2 is connected to the output of the charge pump CP, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M1 and the negative input end of the comparator CMP, the gate of the NMOS tube M1 is connected to the gate of the power tube M0, the source of the NMOS tube M1 is connected to the output voltage VOUT, the source of the NMOS tube M3 is connected to the input end of the current reference Iref and the input end of the clamping circuit Clamp mp cla 2, the output end of the current reference Iref is grounded, the positive input end of the comparator CMP is connected to the source of the NMOS tube M3, the output end of the comparator CMP is connected to the gate of the NMOS tube M4, the drain. The working principle is that the high voltage output by the charge pump CP at the gate potentials of M2 and M3 passes through the clamping action of the clamping current-limiting resistor R2 and the clamping circuit Clamp2, so that the potentials are about 4.5V higher than the source potential of M3, and thus M2 and M3 are completely turned on and work in a linear region, which is equivalent to a resistor, and are respectively marked as RM2 and RM 3. Similarly, the gate-source voltage of M1 is equal to the gate-source voltage of M0, so M1 is also fully turned on and operates in a linear region, equivalent to a resistor, denoted as RM 1.
RM0, RM1, RM2, and RM3 are equivalent resistances of NMOS transistors M0, M1, M2, and M3, respectively, and are calculated as:
μnis the mobility of electron carriers, COXIs the gate oxide capacitance per unit area, W/L is the width-to-length ratio of NMOS tube, VGSThe voltage difference between the gate and the source of the NMOS tube is Vth which is the threshold value of the NMOS tube. Since the NMOS transistors M0, M1, M2 and M3 are all the same device type, the NMOS transistors have the same mobility and the same gate-oxide capacitance product term munCoxAnd a threshold voltage Vth, and has the same VGSAnd the change rules of the NMOS transistors are consistent with the change rules of power supply voltage, temperature and process change, so the proportional relation among the equivalent resistances RM0, RM1, RM2 and RM3 is only dependent on the width-to-length ratio W/L of the corresponding NMOS transistors M0, M1, M2 and M3. The width-to-length ratios of M0, M1, M2, and M3 are hereinafter referred to as S0, S1, S2, and S3, respectively.
When a load current Io flows from the power source VIN to VOUT through the power transistor M0, since the on-resistance RM0 exists in M0, VOUT voltage will be lower than VIN by the following difference: VIN-VOUT Io RM 0. The potential at the negative input of comparator CMP is the divided voltage of the voltage difference between VIN and VOUT between RM1 and RM2, which is:
the positive input terminal of the comparator CMP is generated from RM3 by current reference Iref, and is VIN-Iref RM3, and when the negative input potential of the comparator CMP is equal to the positive input potential, the Io value is determined as the current-limiting protection threshold. It can be calculated as follows:
consists of:
and (VIN-VOUT) ═ Io RM0
The following can be obtained:
then:
it can be seen that the current-limiting protection threshold is only related to the width-to-length ratios of the MOS transistors M0, M1, M2, and M3 and the reference current Iref, but is not related to the power supply voltage, temperature, and process variations, thereby realizing a stable current-limiting protection threshold.
Fig. 2 and 3 are the relationship between the current limiting protection threshold value and the power supply voltage and temperature, respectively, of the current limiting switching circuit employing the present invention, and it can be seen that the current limiting protection threshold value has only small fluctuation with the change of the power supply voltage and temperature, and is almost constant.
Claims (2)
1. A current limit detection and protection circuit for an NMOS load switch, characterized by: the current limiting protection circuit comprises an NMOS load switch and a current limiting detection and protection circuit, wherein the NMOS load switch comprises an NMOS power tube M0, a charge pump CP, a clamping circuit Clamp1 and a resistor R1, the drain electrode of the NMOS power tube M0 is connected with a power supply VIN, the source electrode of the NMOS power tube M0 is connected with the input end of the clamping circuit Clamp1 and serves as an output voltage end VOUT, the output end of the clamping circuit Clamp1 is connected with the grid electrode of the NMOS power tube M0 and one end of the resistor R1, the other end of the resistor R1 is connected with the output end of the charge pump CP, and the input end of the charge pump CP is connected with the power; the current-limiting detection and protection circuit comprises an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a current reference Iref, a resistor R2, a comparator CMP and a clamping circuit Clamp 2; the grid of the NMOS tube M1 is connected with the grid of an NMOS power tube M0 in an NMOS load switch, the source of the NMOS tube M1 is connected with the source of the NMOS power tube M0 in the NMOS load switch, the drain of the NMOS tube M1 is connected with the negative input end of a comparator CMP and the source of an NMOS tube M2, the positive input end of the comparator CMP is connected with the input end of a current reference Iref and the source of the NMOS tube M3 and the input end of a clamping circuit Clamp2, the output end of the clamping circuit Clamp2 is connected with the grid of the NMOS tube M2, the grid of the NMOS tube M3 and one end of a resistor R2, the other end of the resistor R2 is connected with the output end of a charge pump CP in the NMOS load switch, the drain of the NMOS tube M2 is interconnected with the drain of the NMOS tube M3 and connected with a power supply VIN, the output end of the current reference Iref is grounded, the output end of the comparator CMP is connected with the grid of the NMOS tube M4, the source of the NMOS; the NMOS transistor M1, the NMOS transistor M2, the NMOS transistor M3 and the NMOS power transistor M0 are all the same type of devices.
2. The current limit detection and protection circuit for an NMOS load switch of claim 1, wherein: the resistor R1 and the resistor R2 are both clamping current-limiting resistors, the resistance values of R1 and R2 are related to the driving capability of the charge pump CP, the resistance values of R1 and R2 are not less than 1.5Mohm so that the output of the charge pump can maintain a sufficiently high voltage, and the resistance value of R2 is less than that of R1 so that the establishment speed of the gate potentials of the NMOS transistors M2 and M3 is faster than that of the gate potentials of the NMOS transistors M0 and M1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711000830.4A CN107733404B (en) | 2017-10-24 | 2017-10-24 | Current-limiting detection and protection circuit for NMOS load switch |
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| CN201711000830.4A CN107733404B (en) | 2017-10-24 | 2017-10-24 | Current-limiting detection and protection circuit for NMOS load switch |
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| CN107733404B true CN107733404B (en) | 2020-08-18 |
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| US10833668B2 (en) | 2019-03-07 | 2020-11-10 | Analog Devices International Unlimited Company | Integrated and distributed over temperature protection for power management switches |
| CN112448568B (en) * | 2019-08-30 | 2021-11-05 | 圣邦微电子（北京）股份有限公司 | Overvoltage clamping circuit |
| CN110971134B (en) * | 2019-12-19 | 2021-06-22 | 南京微盟电子有限公司 | Rectifier diode voltage drop compensation system of non-isolated switch power supply |
| CN111478687B (en) * | 2020-04-27 | 2023-03-21 | 西安电子科技大学 | High-precision current-limiting load switch circuit |
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| CN102769281A (en) * | 2012-08-07 | 2012-11-07 | 圣邦微电子（北京）股份有限公司 | Quick-response current-limiting protection circuit |
| CN102832807A (en) * | 2012-08-31 | 2012-12-19 | 电子科技大学 | Current control circuit for charge pump |
| CN104242277A (en) * | 2013-06-21 | 2014-12-24 | 中国科学院微电子研究所 | Device for current-limiting protection of load or output |
| CN105680431A (en) * | 2016-03-25 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Adjustable current-limiting protection circuit |
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| CN102043078B (en) * | 2009-10-15 | 2013-04-24 | 意法半导体研发(深圳)有限公司 | Accurate current detection circuit with ultra-low voltage supply |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769281A (en) * | 2012-08-07 | 2012-11-07 | 圣邦微电子（北京）股份有限公司 | Quick-response current-limiting protection circuit |
| CN102832807A (en) * | 2012-08-31 | 2012-12-19 | 电子科技大学 | Current control circuit for charge pump |
| CN104242277A (en) * | 2013-06-21 | 2014-12-24 | 中国科学院微电子研究所 | Device for current-limiting protection of load or output |
| CN105680431A (en) * | 2016-03-25 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Adjustable current-limiting protection circuit |
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Address after: 210042 4th floor, building 1, Xuzhuang Software Park, 699-8 Xuanwu Avenue, Xuanwu District, Nanjing City, Jiangsu Province Patentee after: NANJING MICRO ONE ELECTRONICS Inc. Country or region after: China Address before: Xuzhuang Software Park, No. 699-8 Xuanwu Avenue, Xuanwu District, Nanjing City, Jiangsu Province, 210042 Patentee before: NANJING MICRO ONE ELECTRONICS Inc. Country or region before: China |