CN110971134B - Rectifier diode voltage drop compensation system of non-isolated switch power supply - Google Patents
Rectifier diode voltage drop compensation system of non-isolated switch power supply Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/2176—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only comprising a passive stage to generate a rectified sinusoidal voltage and a controlled switching element in series between such stage and the output
Abstract
A rectifying diode compensation system of a non-isolated switch power supply is based on a non-isolated high-voltage step-down alternating current-direct current conversion topological structure, a diode voltage drop compensation circuit comprising a delay circuit is additionally arranged, a sampling circuit is improved, and the output of a PFM modulator generates a control signal T through the delay circuitCMEntering a diode voltage drop compensation circuit, and outputting a compensation current signal ICMThe compensation voltage signal V generated after being superposed with the output of the sampling circuitCMAnd then the voltage of the output voltage of the PFM modulator is input into a diode voltage drop compensation circuit, the error of the sampling voltage output by an error amplifier OP1 caused by the difference of the voltage drop of a rectifier diode D1 is compensated, the voltage drop change of the rectifier diode D1 caused by the change of the peak current is counteracted in a mode of compensating the sampling voltage output by the error amplifier OP1, and the constancy of the output voltage of the system is realized.
Description
Technical Field
The invention relates to a non-isolated switch power supply, in particular to a rectifying diode voltage drop compensation system of the non-isolated switch power supply, and belongs to the technical field of integrated circuits.
Background
As shown in fig. 1, the conventional non-isolated switching power supply includes a rectifier bridge composed of four diodes (D3, D4, D5, D6), an input filter capacitor C1, an inductor L1, a power tube M1, a peak current sampling resistor R5, a rectifier diode D1, an isolation diode D2, voltage dividing resistors (R1, R2), and an output capacitor C2, and the chip internal circuit includes an error amplifier, a sampling circuit, a PFM modulator, and a driving circuit; the output voltage is connected to the FB end through an isolation diode and a voltage dividing resistor, and the output of the driving circuit is connected with the grid electrode of the power tube M1; the non-isolated switch power supply can convert high-voltage alternating current signals into low-voltage direct current signals, and is widely applied to the fields of household appliances, industrial control power supplies, consumer electronics and the like due to the advantages of few peripheral system devices, low cost, simple structure and the like. At present, many ICs adopting non-isolated control technology are introduced in the market, the ICs adopt a Pulse Frequency Modulation (PFM) mode, the working frequency of the switching power supply is linearly related to the load current, when the output load current is reduced, the switching frequency of the switching power supply is also reduced, in order to reduce the no-load standby power consumption of the system, the working frequency is usually reduced very low, when the switching frequency of the system is as low as an audio frequency region (20 Hz-20 KHz), if the working power of the system is too high, audio noise is generated due to the mechanical vibration of external devices such as a transformer, a capacitor and a resistor, the audio noise is used seriously, in order to eliminate the audio noise when the light load is carried out, the non-isolated switching power supply controller gradually reduces the peak current of the system when the heavy load is turned to the light load, and avoids the system from entering the audio working frequency to generate the audio noise when the high power is carried out, this will make rectifier diode's voltage drop change along with the load, and voltage drop is big when the heavy load, and voltage drop is little when the light load, and the sampling of feedback voltage will be accomplished when inductance discharges (rectifier diode forward conduction promptly), leads to the feedback sampling voltage when the heavy load to be higher than the feedback sampling voltage when the light load, if do not do corresponding voltage drop compensation, system output voltage also will change along with the load current, leads to the load adjustment rate (the change of output voltage along with load current) of system to worsen.
Disclosure of Invention
The invention aims to solve the problem that the output load regulation rate of a system is poor due to the change of the voltage drop of a rectifier diode when the traditional non-isolated switching power supply is switched between heavy load and light load. Therefore, the invention provides a rectifier diode compensation circuit of a non-isolated switching power supply, which counteracts the voltage drop change of a rectifier diode caused by the change of peak current by a mode of compensating the output sampling voltage of an error amplifier on the basis of not increasing external components of a chip, thereby realizing the constancy of the output voltage of a system.
In order to achieve the purpose, the invention adopts the technical scheme that: a rectifying diode voltage drop compensation system of a non-isolated switch power supply is based on a non-isolated high-voltage step-down alternating current-direct current conversion topological structure and comprises a rectifying bridge, an input filter capacitor C1, an inductor L1, a power tube M1, a peak current sampling resistor R5, a rectifying diode D1, an isolation diode D2, voltage dividing resistors R1 and R2 and an output capacitor C2, an error amplifier OP1, a sampling circuit, a PFM modulator, a driving circuit, resistors R3 and R4 are arranged inside a chip, and output voltage V of the non-isolated high-voltage step-down alternating current-direct current conversion topological structureOUTThe voltage is divided by an isolation diode D2 and resistors R1 and R2, and then the voltage is connected with the negative input end of an error amplifier OP1 and one end of a resistor R4 through a resistor R3, the positive input end of the error amplifier OP1 is connected with a reference voltage VREF, and an output signal V of the error amplifier OP1EAThe other end of the resistor R4 is connected to the sampling circuit, and the output signal V of the error amplifier OP1 is connectedEAThe output of the sampling circuit is fed back to the negative input end of an error amplifier OP1 through a resistor R4, and is connected to the grid electrode of a power tube M1 after passing through a PFM modulator and a driving circuit;
the method is characterized in that: a delay circuit and a diode voltage drop compensation circuit are added, and a sampling circuit is improved;
the diode voltage drop compensation circuit comprises a current source IP1, NMOS transistors M2, M3, M4, M5 and M6, PMOS transistors M7, M8 and M9, a capacitor C4 and a resistor R7; the input end of the delay circuit is connected with the output of the PFM modulator, and the output signal T of the delay circuitCMThe grid of the NMOS tube M3 is connected, the input end of the current source IP1 is connected with a power supply VDD, the output end of the current source IP1 is connected with the drain of the NMOS tube M3, the grid of the NMOS tube M2, the grid of the NMOS tube M4, the drain of the NMOS tube M6 and one end of a capacitor C4, the other end of the capacitor C4 is connected with a chip ground, the source of the NMOS tube M3 is connected with the drain of the NMOS tube M2, the source of the NMOS tube M2 is connected with the chip ground, the drain of the NMOS tube M4 is connected with the grid and the drain of the PMOS tube M7 and the grid of the PMOS tube M9 and the grid of the PMOS tube M8, the source of the NMOS tube M4 is connected with one end of a resistor R7, the other end of the resistor R7 is connected with the chip ground, the source of the PMOS tube M7, the source of the PMOS tube M8 and theThe drain and the grid of the MOS transistor M5 and the grid of the NMOS transistor M6, the source of the NMOS transistor M5 and the source of the NMOS transistor M6 are connected with the chip ground, and the drain of the PMOS transistor M9 is used as the output end of the diode drop compensation circuit to output the compensation current ICM；
The sampling circuit comprises a switch K1, a capacitor C3, a voltage follower OP2 and a resistor R6, wherein one end of the switch K1 is connected with an output signal V of an error amplifier OP1EAThe other end of the switch K1 is connected to one end of the capacitor C3 and the positive end of the voltage follower OP2, the switch K1 is controlled by the PFM modulator, and when the PFM signal of the PFM modulator changes to the low level of 5us, the switch K1 is controlled to be closed for 1us, so that the output signal V of the error amplifier OP1 is outputEAThe other end of the capacitor C3 is connected to the chip ground, the negative end of the voltage follower OP2 and the output end of the voltage follower OP2 are interconnected and connected to one end of a resistor R6, and the other end of the resistor R6 is connected to the drain of the PMOS transistor M9 and serves as the output end of the sampling circuit.
The working process of the system is as follows: the output of the PFM modulator generates a control signal T through a delay circuitCMEntering a diode voltage drop compensation circuit, and outputting a compensation current signal ICMThe compensation voltage signal V generated after being superposed with the output of the sampling circuitCMEntering the PFM modulator, the time delay of the high level signal of the PFM modulator lasts until the end of sampling, namely TCMThe low level time of the signal lasts from the end of sampling until the power tube M1 is turned on, and then becomes high level; diode drop compensation circuit according to TCMThe compensating current signal I output by the low-level time control diode voltage drop compensating circuitCMLarge and small, high system operating frequency in heavy load, TCMShort time, generated compensation current ICMSmall, low working frequency at light load, TCMLong time, generated compensating current ICMWhen the peak current is large and the peak current is large during heavy load, the voltage drop generated by the rectifier diode D1 is large, the output of the error amplifier OP1 is high due to the high FB sampling voltage at the input end of the resistor R3, and the generated compensation voltage signal V corresponds to a small compensation currentCMThe lower the cost; the peak current is small when the load is light, the voltage drop generated by the rectifier diode D1 is small, and the input end of the resistor R3The low FB sampling voltage makes the output of the error amplifier OP1 low, and generates a compensation voltage signal V corresponding to a large compensation currentCMThe voltage drop compensation circuit compensates the sampling voltage error output by the error amplifier OP1 due to different voltage drops of the rectifier diode D1, and the voltage drop change of the rectifier diode D1 caused by the change of the peak current is counteracted in a mode of compensating the sampling voltage output by the error amplifier OP1, so that the constancy of the output voltage of the system is realized.
The invention has the advantages and obvious effects that: the invention can solve the problem that the output load adjustment rate of the system is poor due to the voltage drop change of the rectifier diode when the traditional non-isolated switching power supply is switched between heavy load and light load. According to the invention, on the basis of not increasing the external components of the chip, the sampling error caused by the voltage drop change of the rectifier diode caused by the change of the peak current is counteracted in a mode of compensating the output sampling voltage of the error amplifier, so that the constancy of the output voltage is realized.
Drawings
FIG. 1 is a block diagram of a conventional non-isolated switching power supply system;
FIG. 2 is a circuit diagram of the system of the present invention;
FIG. 3 is a diagram of the error amplifier, the sampling circuit and the diode drop compensation circuit according to the present invention.
Detailed Description
As shown in fig. 1, the conventional non-isolated switching power supply is based on a non-isolated high-voltage step-down ac-dc conversion topology, and includes a rectifier bridge composed of four diodes (D3, D4, D5, D6), an input filter capacitor C1, an inductor L1, a power tube M1, a peak current sampling resistor R5, a rectifier diode D1, an isolation diode D2, a voltage dividing resistor (R1, R2), and an output capacitor C2, the internal circuit of the chip includes an error amplifier, a sampling circuit (formed by a switch K1 and a capacitor C3), a PFM modulator, and a driving circuit, the output voltage is connected to the FB terminal through the isolation diode D2 and the voltage dividing resistors R1, R2, and the output of the driving circuit is connected to the gate of the power tube M1.
Referring to fig. 2, the invention adds a delay circuit and a diode drop compensation circuit on the basis of fig. 1 and improves a sampling circuit (on the basis of a switch K1 and a capacitor C3, a delay circuit and a diode drop compensation circuit are addedA voltage follower OP2 and a resistor R6) are added. The positive terminal of the error amplifier OP1 is connected to an internal reference voltage VREF, and an output signal VEAEnters the sampling circuit and is fed back to the negative terminal through a resistor R4, and the feedback signal FB is connected to the negative terminal of the error amplifier OP1 through a resistor R3. The output of the sampling circuit is superposed with the signal V generated after the compensating current signal of the diode voltage drop compensating circuitCMAnd the signal enters a PFM modulator to generate a modulation signal PFM, and the PFM signal is connected with a driving circuit to control the switching state of the power tube M1. The PFM signal generates a control signal T of the diode voltage drop compensation circuit through the delay circuitCMThe delay time of the signal, PFM high level signal, lasts until the end of sampling, i.e. TCMThe low level time of the signal lasts from the end of sampling until the power tube M1 is turned on, and then becomes high level; t isCMSignal connection diode drop compensation circuit according to TCMCompensating current I of low-level time control diode voltage drop compensating circuitCMLarge and small, high system operating frequency in heavy load, TCMShort time, small generated compensating current, low working frequency under light load, TCMThe time is long, the generated compensation current is large, the peak current is large when the heavy load is carried out, the voltage drop generated by the rectifier diode D1 is large, the FB sampling voltage is high, the output of the error amplifier is high, and the compensation voltage signal V is generated corresponding to the small compensation currentCMThe lower the cost; the peak current is small when the load is light, the voltage drop generated by the rectifier diode D1 is small, the FB sampling voltage is low, the output of the error amplifier is low, and the compensation voltage signal V is generated corresponding to the large compensation currentCMThe voltage drop compensation circuit is higher, so that the sampling voltage error caused by different diode drops is compensated by the diode drop compensation circuit, and the output voltage can be constant under the whole load condition by setting reasonable compensation current.
In FIG. 2, the output voltage V of the non-isolated switching power supply systemOUTFeedback voltage V is generated by an isolation diode D2 and voltage dividing resistors R1 and R2 which are fed back to a chip FB pinFBGenerating a difference amplified signal V from a reference voltage value VREF by an error amplifierEA，VEAAnd VFBThe relationship between them is:
when the PFM signal of the PFM modulator changes to low level, the power MOS transistor M1 is turned off, the inductor starts to discharge, the inductor discharge loop comprises an inductor L1, an output capacitor C2 and a rectifier diode D1, when the inductor discharges, the inductor current flows through the rectifier diode D1 to generate a diode drop VD1After 5us of inductor discharge, switch K1 is closed for 1us to complete V pairEAThe FB voltage within the sampling time is:
the working frequency of the non-isolated switch power supply is in linear relation with the load current, when the output load current is reduced, the switching frequency of the switch power supply is reduced, in order to reduce the no-load standby power consumption of the system, the working frequency is usually reduced very low, when the switching frequency of the system is reduced to an audio frequency region (20 Hz-20 KHz), if the working power of the system is too high, audio noise can be generated due to the mechanical vibration of external devices such as a transformer, a capacitor and a resistor, the use of equipment is serious, in order to eliminate the audio noise in light load, the non-isolated switch power supply controller gradually reduces the peak current of the system for charging an inductor in heavy load and light load, the audio noise generated when the system enters the audio frequency in high power is avoided, the discharging current of the inductor is correspondingly reduced, and the voltage drop V of the rectifier diode D1 is reducedD1The voltage drop V of the large-inductance discharge current rectifying diode D1 during heavy load is reduced along with the reduction of the inductance discharge currentD1Large voltage drop, small inductance discharge current at light load and voltage drop V of rectifier diode D1D1Small, the feedback voltage V at heavy load can be known from the formula (2)FBFeedback voltage V at high and light loadFBLow, and generates a larger deviation signal V after being amplified by the difference between the error amplifier and the reference voltage value VREFEAThe signal enters the PFM modulator after being sampled by the sampling circuit, and the biased feedback voltage causes a serious output voltage bias, which is neededFor the voltage value V after samplingEASCompensation is performed to keep the output voltage constant.
As shown in FIG. 3, the positive terminal of the error amplifier is connected to the internal reference voltage VREF, and the output signal V isEAEnters the sampling circuit and is fed back to the negative terminal through a resistor R4, and the voltage feedback signal FB is connected to the negative terminal of the error amplifier through a resistor R3.
As shown in fig. 3, the sampling circuit includes a switch K1, a capacitor C3, a voltage follower OP2, and a resistor R6. One end of the switch K1 is connected to the output of the error amplifier, and the other end is connected to one end of the capacitor C3 and the positive terminal of the voltage follower. The switch K1 is controlled by the PFM modulator, when the PFM signal of the PFM modulator changes to low level 5us, the switch K1 is controlled to close 1us, the output signal V of the error amplifier OP1EAThe other end of the capacitor C3 is connected to the chip ground GNDC, the negative end of the voltage follower is connected to the output of the voltage follower and one end of the resistor R6, and the other end of the resistor R6 is connected to the drain of the M9.
As shown in fig. 3, the diode drop compensation circuit includes a current source IP1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, a capacitor C4, and a resistor R7. The input end of the delay circuit (which can adopt a conventional and well-known structure) is connected with the PFM, and the output end TCMThe grid of the NMOS tube M3 is connected, the input end of the current source IP1 is connected with the power supply VDD, the output end of the current source IP1 is connected with the drain of the NMOS tube M3, the grid of the NMOS tube M2 and the grid of the NMOS tube M4, the drain of the NMOS tube M6 and one end of the capacitor C4, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M2, the source of the NMOS tube M2 is connected to the chip ground GNDC, the drain of the NMOS tube M4 is connected to the gate and the drain of the PMOS tube M7, the gate of the PMOS tube M8 and the gate of the PMOS tube M9, the source of the NMOS tube M4 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the chip ground GNDC, the source of the PMOS tube M7 is connected to the power supply VDD, the source of the PMOS tube M8 is connected to the power supply VDD, the drain of the PMOS tube M8 is connected to the drain and the gate of the NMOS tube M5 and the gate of the NMOS tube M6, the source of the NMOS tube M6 is connected to the chip ground GNDC, the source of the PMOS tube M9 is connected to the power supply VDD.CMFlows through resistor R6 to generate a complementCompensated voltage value VCM。
The PFM signal is changed into low level after the sampling circuit finishes voltage sampling after being delayed by the delay circuit, namely TCMWhen the voltage level changes to low level, the NMOS transistor M3 is turned off, the current source IP1 starts to charge the capacitor C4 with constant current, the voltage of VG4 gradually increases, the current I1 gradually increases, and the current is copied to I through a current mirror formed by the NMOS transistor M7 and the NMOS transistor M9CM(ii) a Meanwhile, the current I1 is copied to I2 through a current mirror formed by an NMOS tube M7 and an NMOS tube M8, the current I2 is copied to the current I3 through a current mirror formed by an NMOS tube M5 and an NMOS tube M6, the current I3 is connected to the output of a current source IP1, the charging current of the C4 is divided, the higher the voltage of the VG4 charged by the current is, the larger the current I3 is divided, the slower the rising of the VG4 is, and the I2 isCMThe rising slope of the current gradually decreases and shows exponential increase, the current flows into the resistor R6, and the sampled voltage V deviated due to the voltage drop of the rectifier diode is generatedEASCompensating for the voltage ICMXr 6, the compensation voltage being superimposed on the sample voltage VsampleOn to produce a compensated voltage value VCMAnd the output voltage enters a PFM modulation module to keep constant.
When the load of the system is switched from heavy load to light load, the generated rectifying diode is dropped to be delta V, and the error of the generated sampling voltage is shown as the formula (1) and (2)
Only the compensation voltage I generated by the diode drop compensation circuit is optimally designedCMXr 6 equals the sampled voltage error, i.e.
The constancy of the output voltage can be achieved.
In summary, the non-isolated switching power supply diode drop compensation circuit provided by the invention cancels the change of the rectifier diode drop caused by the change of the peak current by a way of compensating the output sampling voltage of the error amplifier on the basis of not increasing the external components of the chip, thereby realizing the constancy of the output voltage.
Claims (2)
1. A rectifying diode voltage drop compensation system of a non-isolated switch power supply is based on a non-isolated high-voltage step-down alternating current-direct current conversion topological structure and comprises a rectifying bridge, an input filter capacitor C1, an inductor L1, a power tube M1, a peak current sampling resistor R5, a rectifying diode D1, an isolation diode D2, voltage dividing resistors R1 and R2 and an output capacitor C2, an error amplifier OP1, a sampling circuit, a PFM modulator, a driving circuit, resistors R3 and R4 are arranged inside a chip, and output voltage V of the non-isolated high-voltage step-down alternating current-direct current conversion topological structureOUTThe voltage is divided by an isolation diode D2 and resistors R1 and R2, and then the voltage is connected with the negative input end of an error amplifier OP1 and one end of a resistor R4 through a resistor R3, the positive input end of the error amplifier OP1 is connected with a reference voltage VREF, and an output signal V of the error amplifier OP1EAThe other end of the resistor R4 is connected to the sampling circuit, and the output signal V of the error amplifier OP1 is connectedEAThe output of the sampling circuit is fed back to the negative input end of an error amplifier OP1 through a resistor R4, and is connected to the grid electrode of a power tube M1 after passing through a PFM modulator and a driving circuit;
the method is characterized in that: a delay circuit and a diode voltage drop compensation circuit are added, and a sampling circuit is improved;
the diode voltage drop compensation circuit comprises a current source IP1, NMOS transistors M2, M3, M4, M5 and M6, PMOS transistors M7, M8 and M9, a capacitor C4 and a resistor R7; the input end of the delay circuit is connected with the output of the PFM modulator, and the output signal T of the delay circuitCMThe grid of the NMOS tube M3 is connected, the input end of the current source IP1 is connected with a power supply VDD, the output end of the current source IP1 is connected with the drain of the NMOS tube M3, the grid of the NMOS tube M2, the grid of the NMOS tube M4, the drain of the NMOS tube M6 and one end of a capacitor C4, the other end of the capacitor C4 is connected with a chip ground, the source of the NMOS tube M3 is connected with the drain of the NMOS tube M2, the source of the NMOS tube M2 is connected with the chip ground, the drain of the NMOS tube M4 is connected with the grid and the drain of the PMOS tube M7 and the grid of the PMOS tube M9 and the grid of the PMOS tube M8, the source of the NMOS tube M7 is connected with one end of a resistor R7, the source of the PMOS tube M7, the source of the PMOS tube M8 and the source of the PMOS tube M9 are connected with the power supply VDD, and the drain of the PMOSA grid electrode and a grid electrode of an NMOS tube M6, a source electrode of the NMOS tube M5 and a source electrode of the NMOS tube M6 are both connected with the chip ground, and a drain electrode of the PMOS tube M9 is used as an output end of the diode voltage drop compensation circuit to output a compensation current ICM；
The sampling circuit comprises a switch K1, a capacitor C3, a voltage follower OP2 and a resistor R6, wherein one end of the switch K1 is connected with an output signal V of an error amplifier OP1EAThe other end of the switch K1 is connected to one end of the capacitor C3 and the positive end of the voltage follower OP2, the switch K1 is controlled by the PFM modulator, and when the PFM signal of the PFM modulator changes to the low level of 5us, the switch K1 is controlled to be closed for 1us, so that the output signal V of the error amplifier OP1 is outputEAThe other end of the capacitor C3 is connected to the chip ground, the negative end of the voltage follower OP2 and the output end of the voltage follower OP2 are interconnected and connected to one end of a resistor R6, and the other end of the resistor R6 is connected to the drain of the PMOS transistor M9 and serves as the output end of the sampling circuit.
2. The rectifying diode drop compensation system of a non-isolated switching power supply of claim 1, wherein: the working process of the system is as follows: the output of the PFM modulator generates a control signal T through a delay circuitCMEntering a diode voltage drop compensation circuit, and outputting a compensation current signal ICMThe compensation voltage signal V generated after being superposed with the output of the sampling circuitCMEntering the PFM modulator, the time delay of the high level signal of the PFM modulator lasts until the end of sampling, namely TCMThe low level time of the signal lasts from the end of sampling until the power tube M1 is turned on, and then becomes high level; diode drop compensation circuit according to TCMThe compensating current signal I output by the low-level time control diode voltage drop compensating circuitCMLarge and small, high system operating frequency in heavy load, TCMShort time, generated compensation current ICMSmall, low working frequency at light load, TCMLong time, generated compensating current ICMWhen the peak current is large and the peak current is large during heavy load, the voltage drop generated by the rectifier diode D1 is large, and the output of the error amplifier OP1 is high due to the high FB sampling voltage at the input end of the resistor R3, corresponding to small compensation currentFlow, generating a compensation voltage signal VCMThe lower the cost; the peak current is small when the load is light, the voltage drop generated by the rectifier diode D1 is small, the output of the error amplifier OP1 is low due to the low FB sampling voltage at the input end of the resistor R3, and a compensation voltage signal V is generated corresponding to the large compensation currentCMThe voltage drop compensation circuit compensates the sampling voltage error output by the error amplifier OP1 due to different voltage drops of the rectifier diode D1, and the voltage drop change of the rectifier diode D1 caused by the change of the peak current is counteracted in a mode of compensating the sampling voltage output by the error amplifier OP1, so that the constancy of the output voltage of the system is realized.
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| CN116937960B (en) * | 2023-09-18 | 2023-11-28 | 新誉集团有限公司 | Voltage compensation method and system of inverter, electronic equipment and storage medium |
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