CN102761273B - No-load control system of original-side feedback AC-DC switching power supply - Google Patents
No-load control system of original-side feedback AC-DC switching power supply Download PDFInfo
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Abstract
The invention discloses a no-load control system of an original-side feedback AC-DC switching power supply. The no-load control system comprises a control chip, a transformer and an NMOS (N-channel Metal Oxide Semiconductor) tube, wherein the control chip is provided with a PWM (Pulse-Width Modulation) control and line compensation unit; one input end of the PWM control and line compensation unit is connected with an output voltage detecting and sampling unit, and another two inputs of the PWM control and line compensation unit are respectively connected with a feedback signal incoming pin FB and an original-side current detection signal incoming pin CS; and an output end of the PWM control and line compensation unit and a cycle-by-cycle current-limiting unit are respectively connected with an RS trigger through OR-logic. According to the no-load control system of the original-side feedback AC-DC switching power supply, the PWM control and line compensation unit generates a PWM control mode during medium-load and light-load, so that the original-side peak current in each period is lowered along with the lowering of the load and the system noise in light-load is favorably reduced; in addition, the line compensation is carried out on the lowest original-side peak value, so that the system has extremely low standby power consumption in a wide input voltage range; and the smooth transition between the PWM control mode and a PFM (Pulse Frequency Modulation) control mode is realized by the OR logic.
Description
Technical field
The present invention relates to switch power technology, in particular the unloaded control system of a kind of former limit feedback AC-DC Switching Power Supply.
Background technology
AC-DC control technology of former limit feedback system is the new A C-DC control technology grown up between nearest 10 years, compared with traditional secondary side feedback Switching Power Supply mechanism structure, its maximum advantage is to eliminate isolating chip and the constituent element device with isolating chip cooperating, which offers a saving the space on circuit board, reduce cost and improve the reliability of system.Former limit feedback DC power is in the larger application of the cost pressures such as charger for mobile phone, and the application very high to volume requirement such as LED drive power has the larger market share.
Fig. 1 illustrates a kind of former limit feedback AC-DC power supply control chip of prior art and the structured flowchart of application thereof, as shown in Figure 1, described former limit feedback AC-DC driving power comprises control chip, transformer, NMOS tube, described transformer comprises former limit winding Np, auxiliary winding Na and secondary winding Ns, described control chip comprise secondary ON time detecting unit, constant current frequency control unit, constant pressure control unit, with gate logic, rest-set flip-flop, PFM unit, driver element, Cycle by Cycle flow-restriction and built-in power module.
The former limit formed adopting this control chip is fed back in AC-DC power supply, and resistance R1 and resistance R2 forms sample circuit, and described FB pin is that auxiliary winding Na Voltage Feedback introduces pin, and obtains signal from resistance R1 and resistance R2 formation sample circuit.Inner at control chip, FB pin is connected to the input of output voltage detecting unit and secondary ON time detecting unit, the output of described ON time detecting unit is connected to constant current frequency control unit, the output of described output voltage detecting unit is connected to constant voltage frequency control unit, described CS pin is that former limit winding Np current detection signal introduces pin, obtains signal from NMOS tube source resistance R3.Inner at control chip, CS pin is connected to the input of Cycle by Cycle flow-restriction, constant current frequency control unit and the output signal of constant voltage frequency control unit are connected and two of door inputs respectively, the S being connected respectively to rest-set flip-flop with the output (i.e. start signal) of gate logic and the output (i.e. cut-off signals) of Cycle by Cycle flow-restriction holds and R holds, the output of described rest-set flip-flop and Q end are connected to the input of PFM unit, PFM unit is connected to driver element, the output of described driver element is connected with the OUT pin of control chip, OUT pin exports the grid being connected to NMOS tube, for driving outside power NMOS tube.VCC pin is the power pins of control chip, for being whole control chip access external power source; FB pin is simultaneously as constant current frequency control signal and constant voltage frequency control signal, its constant current FREQUENCY CONTROL is for detecting the ON time of auxiliary winding Na, so that constant current frequency control unit regulates the work period in proportion, make secondary winding Ns outputting current steadily in the value of setting, namely realize the constant current function of LED drive power; The voltage of winding is assisted when its constant voltage frequency controls for detecting secondary conducting, indirect reflection exports the voltage of winding, and then indirectly reflect the size of output voltage, and carry out by-pass cock frequency according to detected voltage swing, make output voltage stabilization in set point.CS is former limit winding Np current sense pin, for detecting peak current during former limit winding Np conducting, to realize the Cycle by Cycle current limliting in each periodic process, and then makes the energy of each periodic transfer all identical; GND is the grounding pin of chip.When the systems are operating normally, relatively auxiliary winding Na is contrary with secondary winding Ns Same Name of Ends for the polarity due to transformer primary side winding Np, and therefore when former limit winding Np conducting, FB pin is negative voltage, when being in secondary winding Ns conducting phase, because auxiliary winding Na is identical with secondary winding Ns Same Name of Ends polarity, therefore FB voltage is positive voltage, now transformer secondary winding voltage is Vs=Vo+Vz, auxiliary winding voltage Va=Vs × (NA/NS)=VFB × R2/ (R1+R2), therefore Vo=VFB × R2 × NS/ [(R1+R2) * NA]-Vz, namely output voltage is the function of feedback voltage V FB, chip regulates VFB to arrive set point by constant voltage frequency control unit, output voltage Vo can be made to be stabilized in set point, now system works is at constant voltage mode, when system works is at constant current mode, secondary ON time detecting unit determines the ON time Tons of secondary winding Ns by the time that detecting FB pin is positive voltage, and the work period T=K × Tons of certainty annuity on this basis, wherein K is proportionality coefficient.Because system works is in discontinuous mode, the energy that each cycle all will make former limit winding Np store all discharges at secondary winding Ns, average output current Iout=Ips × Tons/T=Ipp × (NS/NP) × (1/K) of such secondary winding Ns, peak current when Ips is secondary winding Ns conducting, peak current when Ipp is former limit winding Np conducting, Ns is the number of turns of secondary winding Ns, and Np is the number of turns of former limit winding Np.As long as set Ipp and K and transformer parameter like this, so the output current of secondary winding Ns is exactly a steady state value.
When system works is in underloading or zero load, because former limit conducting of each cycle peak current immobilizes, therefore each periodic transfer is constant to the energy estimate methods of secondary, like this when exporting completely unloaded, transmits to secondary owing to ceaselessly there being energy, secondary output voltage can constantly be elevated, and higher than set point, in order to solve this problem, usually need to add a dummy load RL to secondary output, for consuming the energy that each periodic transfer is come, output voltage is made to maintain set point.What add that dummy load RL brings is the increase of stand-by power consumption, in order to reduce stand-by power consumption, the lowest operating frequency Fmin of control chip must be reduced, its conducting number of times in same time is reduced, thus reduce the energy of transmission, so just can increase RL resistance to reduce stand-by power consumption.But Fmin can produce extreme influence to the dynamic characteristic of system again, when load jumps to the restriction of full load by Fmin from zero suddenly, chip can not make the conducting of former limit carry out makeup energy immediately, but must wait for that maximum turn-off time Tmax (Tmax=1/F_min) has been crossed and just can make the conducting of former limit, like this, Tmax during this period of time in due to output load very large, and whether energy transmits, therefore output voltage can decline rapidly, its drop-out value depends on Tmax completely, Tmax is larger, namely the lower then stand-by power consumption of Fmin is less, but dynamic characteristic is poorer, otherwise then stand-by power consumption is larger, and dynamic characteristic is better.Therefore the stand-by power consumption of system and dynamic characteristic are difficult to carry out simultaneously, must compromise or sacrifice one to improve another.
Therefore, prior art existing defects, needs to improve.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of dynamic characteristic good and the unloaded control system of the low former limit feedback AC-DC Switching Power Supply of stand-by power consumption.
Technical scheme of the present invention is as follows: the unloaded control system of a kind of former limit feedback AC-DC Switching Power Supply, comprise control chip, transformer, NMOS tube, described control chip comprise secondary ON time detecting unit, constant current frequency control unit, output voltage detecting sampling unit, constant voltage frequency control unit, built-in power subsystem, with gate logic, rest-set flip-flop, PFM unit, driver element and Cycle by Cycle flow-restriction; Further, described control chip also arranges PWM control and a line compensating unit; Described PWM controls and line compensating unit arranges three inputs, and wherein, the output that an input detects sampling unit with described output voltage is connected, and another two inputs are introduced pin FB respectively and introduced pin CS with primary current detection signal and be connected with feedback signal; Further, described PWM controls and line compensating unit output and described Cycle by Cycle flow-restriction are connected with shown rest-set flip-flop respectively by one or gate logic.
Be applied to technique scheme, in described unloaded control system, described output voltage detecting sampling unit arranges sampling and keeps module, amplifier and compensation and clamping unit; Described sampling keeps module to be connected with described transformer, its output is connected with the inverting input of described amplifier, the in-phase input end of described amplifier connects internal reference voltage, its output connects an input of described compensation and clamping unit, described compensation is connected described internal reference voltage with another input of clamper list, and its output controls with described constant voltage frequency control unit and described PWM respectively and line compensating unit is connected.
Be applied to each technique scheme, in described unloaded control system, described PWM controls and line compensating unit is made up of amplifier, the first PMOS, the second PMOS, the first resistance, the second resistance and comparator, the in-phase input end connecting to neutral current potential of described amplifier, one end of first resistance described in its anti-phase input termination and the drain electrode of described first PMOS, transformer described in another termination of described first resistance, the output of described amplifier connects the grid of described first PMOS and described second PMOS, the source electrode of the grid of described first PMOS and described second PMOS connects internal electric source, the drain electrode of described second PMOS connects one end of described second resistance and connects the inverting input of described comparator, the other end of described second resistance connects described transformer, described comparator in-phase input end connects described compensation and clamping unit output, described in comparator output terminal or an input of gate logic.
Adopt such scheme, the present invention by add in control chip PWM control and line compensating unit and or gate logic.PWM control and line compensating unit, for generation of pwm pattern during middle underloading, make the former limit peak current in each cycle reduce with the reduction of load, are conducive to system noise during underloading in reducing like this; In addition this unit also carries out line compensation to minimum former limit peak value, makes it not change with the change of line voltage, thus makes system all have extremely low stand-by power consumption in wide input voltage range (85VAC-264VAC).Or gate logic is for realizing the combination of PWM and PFM, realize the level and smooth conversion of PWM and PFM control model.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art.
Fig. 2 is for being structural representation of the present invention.
Fig. 3 is the electrical block diagram of output voltage detecting sampling unit.
Fig. 4 is the electrical block diagram of PWM control and line compensating unit.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 2, present embodiments provide the unloaded control system of a kind of former limit feedback AC-DC Switching Power Supply, described unloaded control system by increase in control chip PWM control and line compensating unit and or gate logic, controlled by described PWM and line compensating unit thus make unloaded control system in wide input voltage range, as in the voltage range of 85VAC-264VAC, all there is extremely low stand-by power consumption, and, the level and smooth conversion of PWM and PFM control model is realized by described or gate logic.
Wherein, described unloaded control system comprises control chip 1, transformer 3, NMOS tube 2, described control chip 1 comprise secondary ON time detecting unit 101, constant current frequency control unit 102, output voltage detecting sampling unit 103, constant voltage frequency control unit 105, built-in power subsystem 104, with gate logic 106, rest-set flip-flop 107, PFM unit 108, driver element 109 and Cycle by Cycle flow-restriction 110.
Further, described control chip 1 also arranges PWM control and a line compensating unit 111; Described PWM controls and line compensating unit one end is connected with the output that described output voltage detects sampling unit, the other end is connected with the former limit winding Np of described transformer, by the former limit winding Np input electric cur-rent measure signal of described transformer, and input the output voltage of described output voltage detecting sampling unit; PWM control and line compensating unit 111, for generation of pwm pattern during middle underloading, make the former limit peak current in each cycle reduce with the reduction of load, are conducive to system noise during underloading in reducing like this; In addition PWM control and line compensating unit 111 also carry out line compensation to minimum former limit peak value, make it not change with the change of line voltage, thus make unloaded control system in wide input voltage range, such as, 85VAC-264VAC, inside all has extremely low stand-by power consumption.
Further, described PWM control and line compensating unit 111 are connected with shown rest-set flip-flop 107 respectively by one or gate logic 112 with described Cycle by Cycle flow-restriction 110.
Wherein, or gate logic 112 is for realizing the combination of PWM and PFM, when system works is in constant current mode, the output voltage of described output voltage detecting sampling unit is very high, Cycle by Cycle current limit threshold OCP is lower than the threshold value of PWM, therefore each cycle carrys out on-off switching tube by Cycle by Cycle current limit threshold OCP, when system works is in middle underloading, namely during constant voltage mode, the voltage of Cycle by Cycle current limit threshold reduces with the reduction of load, Cycle by Cycle current limit threshold OCP is higher than the threshold value of PWM, therefore each cycle carrys out on-off switching tube by PWM, namely to be controlled by PWM and line compensating unit 111 carrys out on-off switching tube, described, therefore the cut-off signals in each cycle depends on that signal lower in the OCP threshold value of Cycle by Cycle current limit threshold and the PWM threshold value of PWM control and line compensating unit 111, thus realizes the level and smooth conversion of PWM and PFM control model.
Further, as shown in Figure 3, Fig. 3 is the internal circuit schematic diagram of output voltage detecting sampling unit 103.Output voltage detecting sampling unit 103 keeps module 1031, amplifier 1032 and compensation and clamping unit 1033 to form by sampling.Sampling keeps module 1031 by the introducing pin FB input signal of described control chip 1, its output FBs connects the inverting input of amplifier 1032, the in-phase input end of amplifier 1032 connects internal reference voltage Vref, the output EAout of amplifier 1032 connects the input compensated with clamping unit 1033, compensate and be connected internal reference voltage VL with another input of clamping unit 1033, compensate and control and line compensating unit 111 with PWM for the constant voltage frequency control unit 105 controlling rear class with the output of clamping unit 1033.Wherein sampling unit 1031 is sampled for certain fixed time when each cycle secondary conducting to the signal voltage introducing pin FB and keeps, thus indirectly carries out sampling to output voltage Vo and keep, and it exports and is the inhibit signal FBs that samples, amplifier 1032 for amplifying the difference between sampled output signal and internal reference voltage Vref, amplifier 1032 size of former limit peak current when the operating frequency for controlling constant voltage mode and middle underloading, thus the value accurately controlling output voltage, compensate with clamping unit 1033 for carrying out frequency compensation to amplifier 1032, guarantee the stability of loop, lower clamper is carried out to the output of amplifier simultaneously, when system is in underloading or is unloaded, introduce the signal voltage of pin FB a little more than reference voltage V ref, the now output of amplifier 1032 is low level (lowest order 0V), and compensate with clamping unit 1033 once detect the output voltage EAout<VL of amplifier, just exporting clamper at VL, namely the voltage comp lowest order VL with the output signal of clamping unit 11033 is compensated, as EAout >=VL, comp=EAout, the comp=VL as EAout<VL, controls constant voltage frequency control unit 105 by VL like this, produces lowest operating frequency Fmin, and VL is controlled and line compensating unit 1111 by control PWM, determines former limit minimum peak electric current.
Further, as shown in Figure 4, Fig. 4 is that PWM controls and the internal circuit schematic diagram of line compensating unit 111, and it is made up of amplifier 1111, first PMOS 1112 and the second PMOS 1113, first resistance 1114, second resistance 1115 and comparator 1116.Wherein, the in-phase input end connecting to neutral current potential of amplifier 1111, one end of anti-phase input termination first resistance 1114 of amplifier 1111 and the drain electrode of the first PMOS 1112, the other end of the first resistance 1114 is connected with the described transformer in outside by introducing pin FB, by introducing pin FB input signal, the output of amplifier 1114 connects the grid of PMOS 1112 and 1113, the source electrode of the first PMOS 1112 and the second PMOS 1113 connects internal electric source, the drain electrode of the second PMOS 1113 connects one end of the second resistance 1115 and connects the inverting input of comparator 1116, the introducing pin CS of the other end connection control chip of the second resistance 1115, and input signal, comparator 1116 in-phase input end connects the output compensated with clamping unit, input signal, comparator 1116 output output pwm signal, one input of the connection of comparator 1116 output or gate logic 112.
So, introduce pin FB terminal voltage to be determined by the turn ratio (Np/Na) of line voltage and transformer primary side and auxiliary winding when former limit conducting, and polarity is contrary, i.e. VFB=– Vline*(Na/Np) * R2/ (R1+R2), therefore drain terminal electric current I FB=(0 – the VFB)/Rc=Vline*Na*R2/ [NP*Rc* (R1+R2)] of the first PMOS 1112, and the second PMOS 1113 and the first PMOS 1112 are relations of current mirror, and ratio is 1:n, therefore the drain terminal electric current I line=n*IFB=n*Vline*Na*R2/ [NP*Rc* (R1+R2)] of the second PMOS 1113.When system is in the unloaded stage, compensate with the voltage comp voltage of the output signal of clamping unit 11033 minimum, be VL, now former limit peak current is minimum,
VCS=VL-Iline*RB=VL-RB* n*Vline*Na*R2/[NP*Rc*(R1+R2)]
And the electric current that chip turn off delay time Δ t brings is when being Vline* Δ t/Lp, as long as design suitable parameter to make RB* n*Vline*Na*R2/ [NP*Rc* (R1+R2)]=R3* Vline* Δ t/Lp,
Namely RB* n* Na*R2/ [NP*Rc* (R1+R2)]=R3e* Δ t/Lp can eliminate the impact that Δ t brings, the former limit minimum peak electric current of system is made fixedly to equal VL/R3, do not change with the change of line voltage, like this in wide input voltage range, when system is unloaded, to be sent to the energy of secondary identical each cycle, therefore in wide voltage range, as 85V-264V, in can use identical, that resistance is larger dummy load RL, to obtain extremely low stand-by power consumption.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improve and convert the protection range that all should belong to claims of the present invention.
Claims (2)
1. the unloaded control system of a former limit feedback AC-DC Switching Power Supply, comprise control chip, transformer, NMOS tube, described control chip comprise secondary ON time detecting unit, constant current frequency control unit, output voltage detecting sampling unit, constant voltage frequency control unit, built-in power subsystem, with gate logic, rest-set flip-flop, PFM unit, driver element and Cycle by Cycle flow-restriction, it is characterized in that;
Further, described control chip also arranges PWM control and a line compensating unit;
Described PWM controls and line compensating unit arranges three inputs, and wherein, the output that an input detects sampling unit with described output voltage is connected, and another two inputs are introduced pin FB respectively and introduced pin CS with primary current detection signal and be connected with feedback signal;
Further, described PWM controls and line compensating unit output and described Cycle by Cycle flow-restriction are connected with described rest-set flip-flop respectively by one or gate logic;
Described PWM controls and line compensating unit is made up of amplifier, the first PMOS, the second PMOS, the first resistance, the second resistance and comparator, the in-phase input end connecting to neutral current potential of described amplifier, one end of first resistance described in its anti-phase input termination and the drain electrode of described first PMOS, transformer described in another termination of described first resistance, the output of described amplifier connects the grid of described first PMOS and described second PMOS, the source electrode of described first PMOS and described second PMOS connects internal electric source, the drain electrode of described second PMOS connects one end of described second resistance and connects the inverting input of described comparator, the other end of described second resistance connects described transformer, described comparator in-phase input end connects compensation and clamping unit output, described comparator output terminal connects an input that is described or gate logic,
Or gate logic realizes the combination of PWM and PFM, when system works is in constant current mode, the output voltage of described output voltage detecting sampling unit is high, Cycle by Cycle current limit threshold OCP is lower than the threshold value of PWM, therefore each cycle carrys out on-off switching tube by Cycle by Cycle current limit threshold OCP, when system works is in constant voltage mode, the voltage of Cycle by Cycle current limit threshold reduces with the reduction of load, Cycle by Cycle current limit threshold OCP is higher than the threshold value of PWM, and therefore each cycle is controlled by PWM and line compensating unit carrys out on-off switching tube.
2. unloaded control system according to claim 1, is characterized in that, described output voltage detecting sampling unit arranges sampling and keeps module, amplifier and compensation and clamping unit; Described sampling keeps module to be connected with described transformer, its output is connected with the inverting input of described amplifier, the in-phase input end of described amplifier connects internal reference voltage, its output connects an input of described compensation and clamping unit, described compensation is connected described internal reference voltage with another input of clamper list, and its output controls with described constant voltage frequency control unit and described PWM respectively and line compensating unit is connected.
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| CN201210211365.XA CN102761273B (en) | 2012-06-26 | 2012-06-26 | No-load control system of original-side feedback AC-DC switching power supply |
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