CN108923639B - Circuit for eliminating audio noise of primary side feedback switching power supply - Google Patents
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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Abstract
The invention discloses a circuit for eliminating audio noise of a primary side feedback switching power supply, wherein the primary side feedback switching power supply is based on an AC-DC primary side control converter topological structure, and is characterized in that: the system is provided with an oscillator, a zero clearing circuit, a noise detection circuit, a time-voltage converter, a switched capacitor filter, a voltage-current conversion circuit and a peak current detection circuit, forms a closed loop with a controlled primary side feedback switching power supply, achieves the purpose of controlling the system frequency by adjusting the peak current of the system, and has high transmission energy when the system is loaded at high power, so that the working frequency of the system is always clamped above 20KHz and works outside an audio frequency area; when the power is low, the transmission energy of the switching power supply is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
Description
Technical Field
The invention relates to a switching power supply with primary side feedback control, in particular to a circuit for eliminating audio noise of a primary side feedback switching power supply, and belongs to the technical field of integrated circuits.
Background
The primary side feedback control switching power supply can convert a high-voltage alternating current signal into a low-voltage direct current signal, and is widely applied to the fields of chargers, adapters, LED driving and the like due to the advantages of few peripheral system devices, low cost, simple structure and the like. Many ICs adopting a primary feedback control technology are proposed in the market at present, the ICs adopt a pulse frequency modulation mode (PFM), the operating frequency of a switching power supply is linearly related to a load current, when an output load current is reduced, the switching frequency of the switching power supply is also reduced, in order to reduce the no-load standby power consumption of a system, the operating frequency is usually reduced to be very low, when the switching frequency of the system is as low as an audio frequency region (20 Hz-20 KHz), if the operating power of the system is too high, audio noise is generated due to mechanical vibration of external devices such as a transformer, a capacitor and a resistor, and the use of equipment is seriously affected.
Disclosure of Invention
The invention aims to solve the problem that when the working frequency of a traditional primary side feedback AC-DC switching power supply chip is lower than 20KHz, audio noise is generated when the chip enters an audio frequency range. Therefore, the invention provides a circuit for eliminating the audio noise of a primary side feedback switch power supply, which achieves the aim of accurately controlling the system frequency by adjusting the peak current of a system, and when a high-power load is carried out, the transmission energy of the switch power supply is high, so that the working frequency of the system is always clamped above 20KHz and works outside an audio frequency region; when the power is low, the system frequency quickly passes through an audio frequency area, the transmission energy of the switching power supply is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
The technical scheme adopted by the invention is as follows: a circuit for eliminating audio noise of a primary side feedback switching power supply based on an AC-DC primary side control converter topological structure comprises a rectifier bridge, an input filter capacitor, a primary side winding NP, a primary side switching tube, a sampling resistor R5, an auxiliary winding NA, a voltage division output resistor, a secondary side winding NS, a rectifier diode and an output resistor R0And a capacitor C0The auxiliary winding NA is connected with the negative end of an error amplifier through a voltage signal output by resistor voltage division, the positive end of the error amplifier is connected with 2V voltage, and the output of the error amplifier controls the grid electrode of a primary side switching tube after passing through a PFM modulator and a driving circuit; the method is characterized in that: the method comprises the following steps that a system consisting of an oscillator, a zero clearing circuit, a noise detection circuit, a time-voltage converter, a switched capacitor filter, a voltage-current conversion circuit and a peak current detection circuit is arranged, and the system and a controlled primary side feedback switching power supply form a closed loop; the peak current detection circuit is connected with the positive end of a comparator COMP through a peak current signal CS acquired by a sampling resistor of a primary side switching tube, a reference voltage VREF is connected with the negative end of the comparator COMP after being connected with a resistor R3 and a resistor R4 in series, the output of the comparator COMP is connected with a PFM modulator, an oscillator generates a periodic square wave clock signal CLK with a duty ratio of 50% and constant frequency, a noise detection circuit receives the square wave clock signal CLK output by the oscillator as a clock signal, the clock signal CLK is processed by a counter and a logic circuit, and the difference between the switching frequency of a system and the frequency reciprocal of 25KHz, namely a difference signal T is calculateddetectThe time-voltage converter receives the difference signal T output by the noise detection circuitdetectConverting the voltage value into a voltage value V _ DETECT in direct proportion to time, receiving a PFM signal output by a PFM modulator by a zero clearing circuit, providing a zero clearing RESET signal RESET at the beginning of each period for a noise detection circuit and a time-to-voltage converter, and switching a capacitorThe control signal of the filter is a PFM signal output by a PFM modulator, a voltage value V _ DETECT which is in direct proportion to time outputs a filtered voltage V _ SCF through a switched capacitor filter, the voltage V _ DETECT is connected to the connecting end of a resistor R3 and a resistor R4 through a voltage-current conversion circuit, a pull-down current which changes linearly along with the input voltage is output, the comparison threshold voltage of the negative end of a comparator COMP is pulled down by the current, the peak current of a system is adjusted to reach the working frequency of the control system, and when a high-power load is carried out, the transmission energy of a switching power supply is high, so that the working frequency of the system is clamped above 20KHz all the time and the system works outside; when the power is low, the transmission energy of the switching power supply is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
The noise detection circuit comprises a T flip-flop T1, a T flip-flop T2, a T flip-flop T3, a T flip-flop T4, an SR flip-flop D1, an SR flip-flop D2, an inverter INV1, an inverter INV2, an inverter INV3, a NAND gate NAND1 and an XOR gate XOR 1; a clock input end CK of a T trigger T1 is connected with a square wave clock signal CLK output by an oscillator, a SET end of the T trigger T1 is connected with a RESET signal RESET, an output end Q of the T trigger T1 is connected with the clock input end CK of the T trigger T2 and one input end of a NAND gate NAND1, an output end Q of the T trigger T2 is connected with the clock input end CK of the T trigger T3, and the SET end of the T trigger T3 is connected with the RESET signal RESET; an output end Q of the T flip-flop T3 is connected with a clock input end CK of the T flip-flop T4 and the other input end of the NAND gate NAND1, an output of the NAND gate NAND1 is connected with an S end of the SR flip-flop D2, an output of the T flip-flop T4 is connected with an input end of the inverter INV1, a SET end of the T flip-flop T4 is connected with a zero RESET signal RESET, an output end of the inverter INV1 is connected with an S end of the SR flip-flop D1, an R end of the SR flip-flop D1 is connected with a zero RESET signal RESET, an output end Q of the SR flip-flop D1 is connected with one input end of the XOR gate 1, an R end of the SR flip-flop D2 is connected with the zero RESET signal RESET, an output end Q of the SR flip-flop D2 is connected with the other input end of the XOR gate 1, an output of the XOR gate 1 is connected with an input.
The time-voltage converter comprises a current source IP1, a switch K1, a switch K2 and a capacitor C1, wherein the input end of the current source IP1 is connected with a power supply VDD, the output end of the current source IP1 is connected with one end of a switch K1, the other end of a switch K1 is connected with one end of a switch K2 and one end of a capacitor C1 and serves as the output end of the time-voltage converter, a voltage value V _ DETECT in direct proportion to time is output, the other end of the switch K2 and the other end of the capacitor C1 are grounded, the control end of the switch K1 is connected with the output of an inverter INV2 in a noise detection circuit, and the control end of the switch K2 is connected with the output of an.
The switched capacitor filter comprises a switch K3, a switch K4, an inverter INV4, a capacitor C2 and a capacitor C3; the voltage value V _ DETEC which is output by the time-voltage converter and is in direct proportion to time is connected with one end of a switch K3, the other end of a switch K3 is connected with one end of a switch K4 and one end of a capacitor C2, the other end of a switch K4 is connected with one end of a capacitor C3 and serves as the output end of a switched capacitor filter, the filtered voltage V _ SCF is output, the other end of the capacitor C2 and the other end of the capacitor C3 are grounded, the control end of the switch K3 is connected with a PFM signal output by the PFM modulator, the control end of a switch K4 is connected with the output end of an inverter INV4, and the input end of an inverter INV4 is connected with.
The voltage and current conversion circuit comprises an operational amplifier A1, a resistor R1, an NMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4 and an NMOS tube M5; the positive phase input end of an operational amplifier A1 is connected with the output voltage V _ SCF of the switched capacitor filter, the negative phase input end of an operational amplifier A1 is connected with the source of an NMOS tube M1 and one end of a resistor R1, the other end of the resistor R1 is grounded, the output end of the operational amplifier A1 is connected with the gate of an NMOS tube M1, the drain of the NMOS tube M1 is connected with the drain and the gate of a PMOS tube M2 and the gate of a PMOS tube M3, the source of the PMOS tube M2 and the source of the PMOS tube M3 are both connected with a power supply VDD, the drain of the PMOS tube M3 is connected with the drain and the gate of an NMOS tube M4 and the gate of an NMOS tube M5, the source of the NMOS tube M8 and the source of the NMOS tube M5 are both grounded, the drain of the NMOS tube M5 is used as the output end of the voltage-current conversion circuit, and the.
The zero clearing circuit generates a zero clearing pulse signal when an input PFM signal becomes a rising edge of a high level, and the output zero clearing signal provides a zero clearing RESET signal RESET at the beginning of each period for the noise detection circuit; when the input PFM signal changes to the falling edge of low level, a zero clearing pulse signal is generated, and the output zero clearing signal provides a zero clearing reset signal of cycle by cycle for the time-voltage converter.
The invention has the advantages and obvious effects that: the invention can effectively eliminate the audio noise of the switching power supply controlled by the primary side feedback, achieve the purpose of accurately controlling the system frequency by adjusting the peak current of the system, and ensure that the transmission energy of the switching power supply is high when the power is loaded at high power, so that the working frequency of the system is always clamped above 20KHz and works outside an audio frequency area; when the power is low, the system frequency quickly passes through an audio frequency area, the transmission energy of the switching power supply is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
Drawings
FIG. 1 is a block diagram of a circuit system for eliminating audio noise of a primary-side feedback switching power supply according to the present invention;
FIG. 2 is a circuit diagram of the oscillator of FIG. 1 connected to a noise detection circuit and a time-to-voltage converter;
FIG. 3 is a circuit diagram of the switched capacitor filter of FIG. 1;
FIG. 4 is the voltage to current conversion circuit and the peak current detection circuit of FIG. 1;
fig. 5 is a timing diagram of the noise detection circuit control.
Detailed Description
Referring to fig. 1, the circuit for eliminating audio noise of a primary side feedback switching power supply of the present invention is based on an AC-DC primary side control converter topology structure, and includes a rectifier bridge, an input filter capacitor, a primary side winding NP, a primary side switching tube, a sampling resistor R5, an auxiliary winding NA, a voltage-dividing output resistor, a secondary side winding NS, a rectifier diode, and an output resistor R0And a capacitor C0The auxiliary winding NA is connected with the negative end of an error amplifier through a voltage signal output by resistance voltage division, the positive end of the error amplifier is connected with 2V voltage, and the output of the error amplifier passes through a PFM modulator and a driving circuitControlling a grid of a primary side switching tube; the method is characterized in that: the method comprises the following steps that a system consisting of an oscillator, a zero clearing circuit, a noise detection circuit, a time-voltage converter, a switched capacitor filter, a voltage-current conversion circuit and a peak current detection circuit is arranged, and the system and a controlled primary side feedback switching power supply form a closed loop; the peak current detection circuit is connected with the positive end of a comparator COMP through a peak current signal CS acquired by a sampling resistor of a primary side switching tube, a reference voltage VREF is connected with the negative end of the comparator COMP after being connected with a resistor R3 and a resistor R4 in series, the output of the comparator COMP is connected with a PFM modulator, an oscillator generates a periodic square wave clock signal CLK with a duty ratio of 50% and constant frequency, a noise detection circuit receives the square wave clock signal CLK output by the oscillator as a clock signal, the clock signal CLK is processed by a counter and a logic circuit, and the difference between the switching frequency of a system and the frequency reciprocal of 25KHz, namely a difference signal T is calculateddetectThe time-voltage converter receives the difference signal T output by the noise detection circuitdetectConverting the PFM signal into a voltage value V _ DETECT which is in direct proportion to time, receiving the PFM signal output by the PFM modulator by the zero clearing circuit, providing a zero clearing RESET signal RESET when each period starts for the noise detection circuit and the time-voltage converter, generating a zero clearing pulse signal by the zero clearing circuit when the input PFM signal becomes a rising edge of a high level, and providing the zero clearing RESET signal RESET when each period starts for the noise detection circuit by the output zero clearing signal; when the input PFM signal changes to the falling edge of low level, a zero clearing pulse signal is generated, and the output zero clearing signal provides a zero clearing reset signal of cycle by cycle for the time-voltage converter. The control signal of the switch capacitor filter is a PFM signal output by a PFM modulator, a voltage value V _ DETECT which is in direct proportion to time outputs a filtered voltage V _ SCF through the switch capacitor filter, the voltage V _ DETECT is connected to the connecting end of a resistor R3 and a resistor R4 through a voltage-current conversion circuit, a pull-down current which linearly changes along with an input voltage is output, the comparison threshold voltage of a negative end of a comparator COMP is pulled down by the current, the working frequency of the system is controlled by adjusting the peak current of the system, and when the power load is large, the transmission energy of the switch power supply is high, so that the working frequency clamping of the system is always above 20KHz and always works outside an audio frequency region; switching power supply transmission at low powerThe energy transmission capacity is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
As shown in fig. 2, the noise detection circuit includes T flip-flops T1, T2, T3, T4, SR flip-flops D1, D2, inverters INV1, INV2, INV3, NAND gate NAND1, and XOR gate XOR 1; a clock input end CK of the T1 is connected with a square wave clock signal CLK output by the oscillator, a SET end of the T1 is connected with a clear RESET signal RESET, an output end Q (f1) of the T1 is connected with the clock input end CK of the T2 and one input end of the NAND gate 1, an output end Q of the T2 is connected with the clock input end CK of the T3, and the SET end of the T3 is connected with the clear RESET signal RESET; an output end Q (f2) of the T3 is connected with the clock input end CK of the T4 and the other input end of the NAND gate 1, an output end (f4) of the NAND gate 1 is connected with the S end of the D2, an output end Q of the T4 is connected with the input end of the INV1, an SET end of the T4 is connected with the RESET signal RESET, an output end (f3) of the INV1 is connected with the S end of the D1, an R end of the D1 is connected with the RESET signal RESET, an output end Q (f20) of the D1 is connected with one input end of the XOR gate XOR1, an R end of the D2 is connected with the RESET signal RESET, an output end Q (f25) of the D2 is connected with the other input end of the XOR gate 1, an output of the XOR gate XOR1 is connected with the input end of the INV2, and the RESET.
The time-voltage converter comprises a current source IP1, a switch K1, a switch K2 and a capacitor C1, wherein the input end of the current source IP1 is connected with a power supply VDD, the output end of the current source IP1 is connected with one end of a switch K1, the other end of a switch K1 is connected with one end of a switch K2 and one end of a capacitor C1 and serves as the output end of the time-voltage converter, a voltage value V _ DETECT in direct proportion to time is output, the other end of a switch K2 and the other end of a capacitor C1 are grounded, the control end of the switch K1 is connected with the output of an inverter INV2 in the noise detection circuit, and the control end of a switch K2 is connected with the output of.
In fig. 2, CLK generates clock signals with cycle-by-cycle time of 40us (f25) and 50us (f20) through a counter formed by T flip-flops T1 to T4, the operating frequency of the primary side feedback control switching power supply system decreases with the decrease of the load, when the operating frequency is lower than 25KHz (the corresponding counting time is 40us), the output of INV2 becomes high level, K1 is closed, and the constant current source IP1 starts to charge the capacitor C1 with a constant current, so as to generate the output voltage value V _ DETECT of the time-to-voltage converter. The lower the operating frequency of the switching power supply system, the longer the K1 closing time, and the higher the V _ DETECT voltage value. When the system operating frequency is reduced to 20KHz, K1 is turned on and the V _ DETECT voltage reaches a maximum value.
As shown in fig. 3, the switched capacitor filter includes a switch K3, a switch K4, an inverter INV4, a capacitor C2, and a capacitor C3; the voltage value V _ DETEC which is output by the time-voltage converter and is in direct proportion to time is connected with one end of a switch K3, the other end of a switch K3 is connected with one end of a switch K4 and one end of a capacitor C2, the other end of a switch K4 is connected with one end of a capacitor C3 and serves as the output end of a switched capacitor filter, the filtered voltage V _ SCF is output, the other end of the capacitor C2 and the other end of the capacitor C3 are grounded, the control end of the switch K3 is connected with a PFM signal output by the PFM modulator, the control end of a switch K4 is connected with the output end of an inverter INV4, and the input end of an inverter INV4 is connected with. The switch capacitor filter has the advantages of small capacitance value, chip area saving, low cost, high processing speed, simple structure and high precision. When the PFM is high, the switch K3 is closed, the switch K4 is opened, the voltage value of V _ detac is transferred to the capacitor C2, and when the PFM is low, the switch K3 is opened, the switch K4 is closed, the charge stored in the capacitor C2 is transferred to C3, and the filtered voltage value V _ SCF is generated. The higher the PFM frequency, the faster the transfer speed of the switched capacitor filter, and the faster the V _ DETEC transfers to the V _ SCF.
As shown in fig. 4, the voltage-current conversion circuit includes an operational amplifier a1, a resistor R1, an NMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, an NMOS transistor M4, and an NMOS transistor M5; the positive phase input end of an operational amplifier A1 is connected with the output voltage V _ SCF of the switched capacitor filter, the negative phase input end of an operational amplifier A1 is connected with the source of an NMOS tube M1 and one end of a resistor R1, the other end of the resistor R1 is grounded, the output end of the operational amplifier A1 is connected with the gate of an NMOS tube M1, the drain of the NMOS tube M1 is connected with the drain and the gate of a PMOS tube M2 and the gate of a PMOS tube M3, the source of the PMOS tube M2 and the source of the PMOS tube M3 are both connected with a power supply VDD, the drain of the PMOS tube M3 is connected with the drain and the gate of an NMOS tube M4 and the gate of an NMOS tube M5, the source of the NMOS tube M8 and the source of the NMOS tube M5 are both grounded, the drain of the NMOS tube M5 is used as the output end of the voltage-current conversion circuit, and the. M2 and M3 are current mirror copy circuits, and the proportionality coefficient of the current mirror copy can be obtained by adjusting the width-length ratio of M2 and M3. The drain of the PMOS transistor M3 is connected to the drain and gate of the NMOS transistor M4 and the gate of the M5 transistor, and the sources of the NMOS transistors M4 and M5 are grounded. M4 and M5 are current mirror copy circuits, and the proportionality coefficient of the current mirror copy can be obtained by adjusting the width-length ratio of M2 and M3. The voltage-current conversion circuit realizes conversion of the input voltage V _ SCF into the current I _ CS.
As shown in fig. 4, the peak current detection circuit includes resistors R3 and R4, a comparator COMP, one end of a resistor R3 is connected to the reference voltage VREF, the other end is connected to the drain of the NMOS transistor M5 and one end of the resistor R4, the other end of the resistor R4 is connected to the negative-phase input end of the comparator, a peak current detection signal CS is connected to the positive-phase input end of the comparator, and the output signal is Cout. When I _ CS is 0, Vth is equal to VREF, when I _ CS is large, Vth is small (smaller than VREF), when CS is small, the output signal Cout is inverted, that is, the peak current is small, and the output signal Cout controls the PFM signal to be turned off.
The working principle of the circuit of the invention is as follows: the power transmission equation of the primary side feedback switching power supply based on the PFM mode is as follows:
wherein P is the output power of the switching power supply system, VOAnd IORespectively, system output voltage and current, η system conversion efficiency, LmIs the inductance of a transformer, fsTo the system switching frequency, IpkThe peak current of the primary side inductor of the system is calculated for each period.
From the equation (1), L is known for a PFM modulation system with a fixed peak current control modemIs a constant value, IpkFor a fixed value, the operating frequency of the switching power supply is linear with the load current, when the output load current decreases, i.e. IOSwitching frequency f of the switching power supply during reductionsAnd thenReducing the switching frequency f of the systemsThe reduction to the audio region (20 Hz-20 KHz) generates audio noise. In order to prevent the system from being reduced to the audio frequency range, the working mode of the system is changed and I is reduced under the same power conditionpkCan be lifted up fs。
As shown in fig. 2, the rising edge of the PFM signal changing to high level is taken as the starting point of one cycle, the zero clearing circuit generates a zero clearing pulse signal RESET when the rising edge of the PFM signal changing to high level, the zero clearing signal RESET clears T triggers T1 to T4 and SR triggers D1 to D2, then CLK generated by the oscillator starts to be clocked by a counter composed of T triggers T1 to T4, if the system switching frequency is greater than 25KHz, the logic output of the counter is made to be always off K1, further V _ det is zero, V _ SCF is zero, I _ CS is zero, VREF is equal to Vth, and the system operates in a fixed peak current mode. If the system load current is continuously reduced, the system working frequency is reduced to be below 25KHz, when CLK generated by an oscillator is clocked to 40us (the corresponding frequency is 25KHz) through a frequency divider formed by T flip-flops T1-T4, f25 is changed into low level, f20 is high level, high level is output after the CLK is operated by a logic gate XOR1 and an inverter INV2, K1 is closed, a constant current source IP1 starts to charge a capacitor C1 with constant current, and the capacitor C1 is charged by a capacitor formula
Can obtain the output voltage of the time-to-voltage converter
Wherein I is the current of the constant current source IP1, t is the K1 closing time, and C is the capacitance value of the capacitor C1.
As can be seen from (3), t can also be expressed as the system duty cycle time
And is provided withA fixed noise detection time of 40 us. V _ DETECT is connected to the switched capacitor filter circuit. As shown in fig. 3, when PFM is high, switch K3 is closed, switch K4 is open, and the voltage value of V _ DETEC is transferred to capacitor C2, and when PFM is low, switch K3 is open, switch K4 is closed, and the charge stored in capacitor C2 is transferred to C3, resulting in filtered voltage value V _ SCF. The higher the PFM frequency, the faster the transfer speed of the switched-capacitor filter, the faster the V _ DETEC is transferred to V _ SCF, which is transferred over several cycles. V _ SCF is used as the input of the voltage-current conversion circuit, as shown in FIG. 4, the V _ SCF is converted into a current I1 by the voltage-current conversion circuit composed of an operational amplifier A1, an NMOS transistor M1, a PMOS transistor M2 and a resistor R1,
the current value of I1 can be obtained from the formula (4), I2 accurately copies the current of I1 through a current mirror consisting of a PMOS tube M2 and a PMOS tube M3, I _ CS accurately copies the current of I2 through a current mirror consisting of an NMOS tube M4 and an NMOS tube M5, and finally the current value of I1 can be obtained
I _ CS is switched into the peak current detection circuit, as shown in figure 4,
Vth＝VREF-I_CS×R3 (5)
the linear relationship between the comparison threshold voltage Vth of CS and the pull-down current I _ CS can be known from equation (5).
The peak current I can be found from the formula (6)pkThe relationship of the threshold voltage and the sense resistance R5 is compared to CS.
From the formulae (2), (3), (4), (5) and (6)
As can be seen from the formula (7), the peak current of the switching power supply in the primary side feedback mode is converted into a function related to the switching frequency of the system, and the smaller the value of the switching frequency fS, the smaller IpkThe smaller.
From the formulae (1) and (7)
If the load current is continuously reduced, the working frequency of the system is reduced to 20KHz, CLK generated by the oscillator is counted to 50us (corresponding to the frequency of 20KHz) through a counter formed by T flip-flops T1-T4, f25 is low level, f20 is changed into low level, the low level is output after the operation of a logic gate XOR1 and an inverter INV2, K1 is opened, the constant current source IP1 stops charging C1, the voltage on C1 reaches the maximum value at the moment, and the corresponding I ispkWhen the minimum value is reached, the noise detection circuit controls the timing as shown in FIG. 5, and the power at that time can be obtained from equation (8)
The parameters of R3, R1, R5 and C1 can be reasonably set according to the formula (9), so that the switching frequency is 20KHz and IpkThe system output power P at which the minimum value is reached is small enough that even the generated transmission energy is not sufficient to generate audio noise even in the audio interval. The system switching frequency is from less than 25KHz to IpkThe clamp is always above 20KHz between minimums. Then the load current continues to decrease, the system enters a Pulse Frequency Modulation (PFM) working mode, the switching frequency of the system is lower than 20KHz, the power is small enough, the transmission energy of the switching power supply is extremely low, and no enough energy can generate audio noise even if the switching frequency of the system is lower than 20 KHz.
The whole system working process is divided into three stages: (1) the working frequency is more than 25KHz, the system adopts a pulse frequency modulation mode (PFM) with fixed peak current, and audio noise can not be generated when the system does not enter an audio section. (2) The working frequency is less than 25KHz, the circuit for eliminating the audio noise of the switching power supply controls the peak current in real time through the switching frequency fs of the detection system, so that the working frequency of the system always works above 20KHz until the peak current is reduced to the minimum value, and the audio noise cannot be generated when the audio band is not entered in the stage. (3) The working frequency is less than 20KHz, the switching power supply works in a pulse frequency modulation mode with low peak current, the power is low enough, the transmission energy of the switching power supply is extremely low, enough energy is not generated to generate audio noise, and even if the switching frequency of the system is lower than 20KHz, the audio noise can not be generated.
In summary, the circuit for eliminating the audio noise of the primary-side feedback-controlled switching power supply of the invention can accurately detect the switching frequency of the system, and by controlling the peak current, the working frequency of the system is always clamped above 20KHz when the system is in a high power state, and the transmission energy of the switching power supply is extremely low when the system is in a low power state, so that no enough energy can be generated to generate the audio noise, and finally the purpose of eliminating the audio noise is achieved.
Claims (6)
1. A circuit for eliminating audio noise of a primary side feedback switching power supply based on an AC-DC primary side control converter topological structure comprises a rectifier bridge, an input filter capacitor, a primary side winding NP, a primary side switching tube, a sampling resistor R5, an auxiliary winding NA, a voltage division output resistor, a secondary side winding NS, a rectifier diode and an output resistor R0And a capacitor C0The auxiliary winding NA is connected with the negative end of an error amplifier through a voltage signal output by resistor voltage division, the positive end of the error amplifier is connected with 2V voltage, and the output of the error amplifier controls the grid electrode of a primary side switching tube after passing through a PFM modulator and a driving circuit;
the method is characterized in that: the method comprises the following steps that a system consisting of an oscillator, a zero clearing circuit, a noise detection circuit, a time-voltage converter, a switched capacitor filter, a voltage-current conversion circuit and a peak current detection circuit is arranged, and the system and a controlled primary side feedback switching power supply form a closed loop; the peak current detection circuit is connected with the positive end of a comparator COMP through a peak current signal CS acquired by a sampling resistor of a primary side switching tube, a reference voltage VREF is connected with the negative end of the comparator COMP after being connected with a resistor R3 and a resistor R4 in series, the output of the comparator COMP is connected with a PFM modulator, and an oscillator generates a signalGenerating a periodic square wave clock signal CLK with a constant frequency and a duty ratio of 50%, receiving the square wave clock signal CLK output by an oscillator as a clock signal by a noise detection circuit, processing the clock signal by a counter and a logic circuit, and calculating the difference value between the system switching frequency and the frequency reciprocal of 25KHz frequency, namely a difference signal TdetectThe time-voltage converter receives the difference signal T output by the noise detection circuitdetectConverting the voltage value into a voltage value V _ DETECT which is in direct proportion to time, receiving a PFM signal output by the PFM modulator by a clear circuit, providing a clear RESET signal RESET at the beginning of each period for a noise detection circuit and a time-to-voltage converter, wherein a control signal of a switched capacitor filter is the PFM signal output by the PFM modulator, the voltage value V _ DETECT which is in direct proportion to the time outputs the filtered voltage V _ SCF through the switch capacitor filter, is connected to the connection end of the resistors R3 and R4 through the voltage-current conversion circuit, outputs the pull-down current which is linearly changed along with the input voltage, the current pulls down the comparison threshold voltage of the negative terminal of the comparator COMP, the working frequency of the control system is reached by adjusting the peak current of the system, when the load is high-power, the transmission energy of the switch power supply is high, so that the working frequency of the system is always clamped above 20KHz and always works outside an audio frequency region; when the power is low, the transmission energy of the switching power supply is extremely low, and no enough energy is generated to generate audio noise, so that the audio noise in the whole load range of the switching power supply is eliminated finally.
2. The circuit for canceling audio noise of a primary-side feedback switching power supply according to claim 1, wherein: the noise detection circuit comprises a T flip-flop T1, a T flip-flop T2, a T flip-flop T3, a T flip-flop T4, an SR flip-flop D1, an SR flip-flop D2, an inverter INV1, an inverter INV2, an inverter INV3, a NAND gate NAND1 and an XOR gate XOR 1; a clock input end CK of a T trigger T1 is connected with a square wave clock signal CLK output by an oscillator, a SET end of the T trigger T1 is connected with a RESET signal RESET, an output end Q of the T trigger T1 is connected with the clock input end CK of the T trigger T2 and one input end of a NAND gate NAND1, an output end Q of the T trigger T2 is connected with the clock input end CK of the T trigger T3, and the SET end of the T trigger T3 is connected with the RESET signal RESET; an output end Q of the T flip-flop T3 is connected with a clock input end CK of the T flip-flop T4 and the other input end of the NAND gate NAND1, an output of the NAND gate NAND1 is connected with an S end of the SR flip-flop D2, an output of the T flip-flop T4 is connected with an input end of the inverter INV1, a SET end of the T flip-flop T4 is connected with a zero RESET signal RESET, an output end of the inverter INV1 is connected with an S end of the SR flip-flop D1, an R end of the SR flip-flop D1 is connected with a zero RESET signal RESET, an output end Q of the SR flip-flop D1 is connected with one input end of the XOR gate 1, an R end of the SR flip-flop D2 is connected with the zero RESET signal RESET, an output end Q of the SR flip-flop D2 is connected with the other input end of the XOR gate 1, an output of the XOR gate 1 is connected with an input.
3. The circuit for canceling audio noise of a primary-side feedback switching power supply according to claim 1, wherein: the time-voltage converter comprises a current source IP1, a switch K1, a switch K2 and a capacitor C1, wherein the input end of the current source IP1 is connected with a power supply VDD, the output end of the current source IP1 is connected with one end of a switch K1, the other end of a switch K1 is connected with one end of a switch K2 and one end of a capacitor C1 and serves as the output end of the time-voltage converter, a voltage value V _ DETECT in direct proportion to time is output, the other end of the switch K2 and the other end of the capacitor C1 are grounded, the control end of the switch K1 is connected with the output of an inverter INV2 in a noise detection circuit, and the control end of the switch K2 is connected with the output of an.
4. The circuit for canceling audio noise of a primary-side feedback switching power supply according to claim 1, wherein: the switched capacitor filter comprises a switch K3, a switch K4, an inverter INV4, a capacitor C2 and a capacitor C3; the voltage value V _ DETEC which is output by the time-voltage converter and is in direct proportion to time is connected with one end of a switch K3, the other end of a switch K3 is connected with one end of a switch K4 and one end of a capacitor C2, the other end of a switch K4 is connected with one end of a capacitor C3 and serves as the output end of a switched capacitor filter, the filtered voltage V _ SCF is output, the other end of the capacitor C2 and the other end of the capacitor C3 are grounded, the control end of the switch K3 is connected with a PFM signal output by the PFM modulator, the control end of a switch K4 is connected with the output end of an inverter INV4, and the input end of an inverter INV4 is connected with.
5. The circuit for canceling audio noise of a primary-side feedback switching power supply according to claim 1, wherein: the voltage and current conversion circuit comprises an operational amplifier A1, a resistor R1, an NMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4 and an NMOS tube M5; the positive phase input end of an operational amplifier A1 is connected with the output voltage V _ SCF of the switched capacitor filter, the negative phase input end of an operational amplifier A1 is connected with the source of an NMOS tube M1 and one end of a resistor R1, the other end of the resistor R1 is grounded, the output end of the operational amplifier A1 is connected with the gate of an NMOS tube M1, the drain of the NMOS tube M1 is connected with the drain and the gate of a PMOS tube M2 and the gate of a PMOS tube M3, the source of the PMOS tube M2 and the source of the PMOS tube M3 are both connected with a power supply VDD, the drain of the PMOS tube M3 is connected with the drain and the gate of an NMOS tube M4 and the gate of an NMOS tube M5, the source of the NMOS tube M8 and the source of the NMOS tube M5 are both grounded, the drain of the NMOS tube M5 is used as the output end of the voltage-current conversion circuit, and the.
6. The circuit for canceling audio noise of a primary-side feedback switching power supply according to claim 1, wherein: the zero clearing circuit generates a zero clearing pulse signal when an input PFM signal becomes a rising edge of a high level, and the output zero clearing signal provides a zero clearing RESET signal RESET at the beginning of each period for the noise detection circuit; when the input PFM signal changes to the falling edge of low level, a zero clearing pulse signal is generated, and the output zero clearing signal provides a zero clearing reset signal of cycle by cycle for the time-voltage converter.
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| CN112822818B (en) * | 2019-11-15 | 2023-11-10 | 华润微集成电路(无锡)有限公司 | Circuit structure for realizing electrodeless dimming function |
| CN112542954B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Adaptive soft drive control circuit suitable for DCM |
| CN112737339B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
| CN112564511B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit suitable for CCM |
| CN114697593B (en) * | 2020-12-31 | 2023-11-10 | 广州艾美网络科技有限公司 | Power supply system of audio-video integrated machine |
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| WO1999062264A1 (en) * | 1998-05-22 | 1999-12-02 | Matsushita Electric Industrial Co., Ltd. | Block noise detector and block noise eliminator |
| US7417879B2 (en) * | 2006-03-08 | 2008-08-26 | Micrel, Inc. | PFM and current controlled switching regulator |
| US8879280B2 (en) * | 2008-12-18 | 2014-11-04 | Infineon Technologies Ag | Techniques to reduce audible noise in a power supply transformer |
| CN201569491U (en) * | 2009-11-19 | 2010-09-01 | 上海第二工业大学 | Noise detecting and warning device |
| CN102769383B (en) * | 2011-05-05 | 2015-02-04 | 广州昂宝电子有限公司 | System and method for constant-current control via primary side sensing and regulating |
| CN102761273B (en) * | 2012-06-26 | 2015-05-20 | 深圳市稳先微电子有限公司 | No-load control system of original-side feedback AC-DC switching power supply |
| CN203014670U (en) * | 2012-12-28 | 2013-06-19 | 上海贝岭股份有限公司 | Audio frequency noise elimination circuit |
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Address after: 210042 4th floor, building 1, Xuzhuang Software Park, 699-8 Xuanwu Avenue, Xuanwu District, Nanjing City, Jiangsu Province Patentee after: NANJING MICRO ONE ELECTRONICS Inc. Country or region after: China Address before: 210042 4th floor, building 1, Xuzhuang Software Park, 699-8 Xuanwu Avenue, Xuanwu District, Nanjing City, Jiangsu Province Patentee before: NANJING MICRO ONE ELECTRONICS Inc. Country or region before: China |