CN115498970A - Amplifying circuit, differential amplifying circuit and amplifier - Google Patents
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- H—ELECTRICITY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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Abstract
The application relates to an amplifying circuit, a differential amplifying circuit and an amplifier, wherein the amplifying circuit comprises a first amplifying module, a feedback module and a second amplifying module; the first amplification module is used for accessing an input voltage signal and outputting a voltage sampling signal; the feedback module is connected with the first amplification module and used for receiving the voltage sampling signal and outputting a voltage feedback signal to the first amplification module; the second amplifying module is connected with the feedback module and used for outputting a voltage signal. The gain of the first amplifying module is adjusted by introducing the feedback module as a negative feedback loop, the product of the gain of the first amplifying module and the gain of the second amplifying module is used as the gain of the amplifying circuit, the correlation between the gain and the PVT is small, and the consistency of the gain of the whole link and the output precision are ensured.
Description
Technical Field
The present application relates to electrical and electronic circuits, and more particularly to amplification circuits, differential amplification circuits, and amplifiers.
Background
The voltage amplifier circuit is a circuit capable of amplifying an input voltage signal with a certain amplitude and a certain frequency according to gain. The amplification of the transistor is used to convert the power of the power supply into an output quantity which changes in proportion to the input quantity, and the weak electric signal is enhanced to the required voltage, current or power value.
However, the gain of the open-loop Voltage amplifier circuit is often greatly affected by the variation of PVT (Process Voltage Temperature), and it is difficult to ensure the accuracy of the output signal.
Disclosure of Invention
In view of the above, it is desirable to provide an amplifier circuit, a differential amplifier circuit, and an amplifier having a stable gain and ensuring output accuracy.
An amplification circuit, comprising:
the first amplification module is used for accessing an input voltage signal and outputting a voltage sampling signal;
the feedback module is connected with the first amplification module, receives the voltage sampling signal and outputs a voltage feedback signal to the first amplification module;
and the second amplification module is connected with the feedback module and used for outputting a voltage signal.
In one embodiment, the feedback module includes a first transistor; the grid and the drain of the first transistor are connected with the first amplification module, the source of the first transistor is grounded, and the grid of the first transistor is connected with the second amplification module.
In one embodiment, the system further comprises a level processing unit; the level processing unit is connected with the first amplifying module, the grid electrode of the first transistor and the second amplifying module.
In one embodiment, the level processing unit comprises a second transistor and a first current source, wherein the grid of the second transistor is connected to the voltage sampling signal; the drain electrode of the second transistor is connected with the power supply input end, the source electrode of the second transistor is connected with the positive end of the first current source, the negative end of the first current source is grounded, and the common end of the source electrode of the second transistor, which is connected with the first current source, is respectively connected with the grid electrode of the first transistor and the second amplification module.
In one embodiment, the level processing unit includes a second transistor and a first current source; the grid electrode of the second transistor is connected with bias voltage, the drain electrode of the second transistor is connected with the positive end of the first current source, and the negative end of the first current source is grounded; the source electrode of the second transistor is connected with the first amplifying module; and the source electrode of the second transistor is connected with the common end of the first current source and is respectively connected with the grid electrode of the first transistor and the second amplification module.
In one embodiment, the second amplifying module comprises a third transistor and a load resistor, and the grid electrode of the third transistor is connected with the feedback module; the drain electrode of the third transistor is connected with the first end of the load resistor, the second end of the load resistor is connected with the power supply input end, and the source electrode of the third transistor is grounded; and the common end of the drain electrode of the third transistor, which is connected with the load resistor, is used for outputting a voltage signal.
In one embodiment, the first amplifying module comprises a fourth transistor, a load device and a negative feedback unit; the grid electrode of the fourth transistor is used for connecting an input voltage signal; the drain electrode of the fourth transistor is connected with the load device; the source electrode of the fourth transistor is connected with the negative feedback unit; the drain electrode of the fourth transistor is connected with the common end connected with the load device and the feedback module, and the feedback module is further connected with the common end connected with the source electrode of the fourth transistor and the negative feedback unit.
In one embodiment, the first amplifying module further comprises a source degeneration capacitor connected in parallel with the negative feedback unit;
the second amplifying module further comprises a load capacitor, wherein the first end of the load capacitor is connected with the drain electrode of the third transistor, and the second end of the load capacitor is grounded.
A differential amplification circuit, comprising: the first amplifying circuit is connected with the second amplifying circuit; the first amplifying circuit and the second amplifying circuit are both the amplifying circuits as described above.
An amplifier comprising an amplifying circuit as described above, and/or a differential amplifying circuit as described above.
The amplifying circuit comprises a first amplifying module, a feedback module and a second amplifying module; the first amplification module is used for accessing an input voltage signal and outputting a voltage sampling signal; the feedback module is connected with the first amplification module and used for receiving the voltage sampling signal and outputting a voltage feedback signal to the first amplification module; the second amplifying module is connected with the feedback module and used for outputting a voltage signal. The gain of the first amplifying module is adjusted by introducing the feedback module as a negative feedback loop, the product of the gain of the first amplifying module and the gain of the second amplifying module is used as the gain of the amplifying circuit, the gain has high robustness and small correlation with PVT, and the consistency and the output precision of the gain of the whole link are ensured.
Drawings
FIG. 1 is a block diagram schematically illustrating the structure of an amplifying circuit according to an embodiment;
FIG. 2 is a schematic diagram of an embodiment of an amplifier circuit;
FIG. 3 is a schematic diagram of a conventional source amplifier circuit;
FIG. 4 is a schematic diagram of an amplifier circuit according to another embodiment;
FIG. 5 is a schematic diagram showing the structure of an amplifying circuit in still another embodiment;
FIG. 6 is a schematic diagram of an equivalent structure of the feedback module in the above embodiment;
FIG. 7 is a schematic diagram of a structure of an amplifying circuit in the embodiment of FIG. 4, in which a degeneration capacitor is introduced;
FIG. 8 is a schematic diagram of the structure of the amplifier circuit of FIG. 5 with degenerated capacitance;
FIG. 9 is a block diagram of a differential amplifier circuit according to an embodiment;
FIG. 10 is a schematic diagram of a differential amplifier circuit according to an embodiment;
FIG. 11 is a schematic diagram of a structure of a differential amplifier circuit incorporating a degeneration capacitor in the embodiment of FIG. 10;
FIG. 12 is a schematic diagram of a differential amplifier circuit according to another embodiment;
fig. 13 is a schematic diagram of a structure of a differential amplifier circuit incorporating a degenerated capacitance in the embodiment of fig. 12.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided an amplifying circuit comprising a first amplifying block 10, a feedback block 20 and a second amplifying block 30; the first amplification module 10 is used for accessing an input voltage signal Vin and outputting a voltage sampling signal; the feedback module 20 is connected to the first amplification module 10, receives the voltage sampling signal, and outputs a voltage feedback signal to the first amplification module 10; the second amplifying module 30 is connected to the feedback module 20 for outputting the voltage signal Vout.
It is understood that the first amplification module 10 and the second amplification module 30 are also respectively connected to the power input terminal and are respectively grounded. In combination with actual needs, the first amplification module and the second amplification module may be both common-source amplification circuits or other amplification circuits, such as common-emitter amplification circuits; the feedback module may be a negative feedback circuit.
When the first amplification module 10 and the second amplification module 30 are both common-source amplification circuits, the feedback module 20 detects an output voltage signal of the first amplification module 10, that is, a voltage sampling signal, and converts the voltage sampling signal into a voltage feedback signal, the voltage feedback signal is fed back to the first amplification module 10, and the output voltage of the common-source amplification circuit of the first amplification module 10, that is, the voltage sampling signal, is adjusted, thereby forming a negative feedback loop, and adjusting the gain of the first amplification module 10, and the product of the gain of the first amplification module 10 and the gain of the second amplification module 30 is used as the gain of the amplification circuit, which has small correlation with PVT and high robustness.
Specifically, the voltage feedback signal output by the feedback module 20 is fed back to the source of the transistor in the common-source amplification circuit of the first amplification module 10, and the input voltage Vin is subtracted from the voltage signal, so as to adjust the output voltage of the first amplification module 10. It is to be understood that fig. 1 is only a schematic diagram of the structure of the amplifying circuit, and the specific structure of the amplifying circuit is not limited.
The amplifying circuit comprises a first amplifying module 10, a feedback module 20 and a second amplifying module 30; the first amplifying module 10 is used for accessing an input voltage signal Vin and outputting a voltage sampling signal; the feedback module 20 is connected to the first amplifying module 10, and is configured to receive the voltage sampling signal and output a voltage feedback signal to the first amplifying module 10; the second amplifying module 30 is connected to the feedback module 20 for outputting the voltage signal Vout. By introducing the feedback module 20 as a negative feedback loop, the gain of the first amplification module 10 is adjusted, and the product of the gain of the first amplification module 10 and the gain of the second amplification module 30 is used as the gain of the amplification circuit, so that the gain has high robustness and small correlation with PVT (physical vapor transport) and the output accuracy is ensured.
In one embodiment, as shown in fig. 2, the first amplification module 10 includes a fourth transistor M1, a load device 11, and a negative feedback unit 12; the grid electrode of the fourth transistor M1 is the input end of the amplifying circuit and is used for accessing an input voltage signal Vin; the drain of the fourth transistor M1 is connected to the load device 11; the source of the fourth transistor M1 is connected to the negative feedback unit 12. The drain of the fourth transistor M1 is connected to the common terminal of the load device 11 and the feedback module 20 for outputting the voltage sampling signal. The feedback module 20 is further connected to the source of the fourth transistor M1 and the common terminal of the negative feedback unit 12.
The load device 11 may be a resistor, a diode-connected transistor, or a current source, among others. If the resistor is used as the load, the load is less sensitive to PVT variations and can provide a more stable output impedance, however, the resistance value of the resistor is inevitably increased in order to seek a high gain, so that the common mode output range is reduced, and the output voltage swing is further reduced. Diode-connected transistors are used as loads which are both sensitive to PVT variations and consume a large amount of voltage margin. The current source is preferably used as a load in low voltage applications because it has an output impedance that is sensitive to PVT variations, but can consume only a small voltage margin by adjusting the overdrive voltage of the current source. In this embodiment, the load device 11 selects the current source I0, and is suitable for a lower voltage domain, for example, the voltage input by the power input terminal may be as low as 1V.
The first amplifying module 10 is further provided with a negative feedback unit 12, referring to fig. 3, fig. 3 is also a common source amplifier with a conventional load as a current source, and under a proper bias condition, an input ac voltage signal is converted into an output ac current signal through transconductance of the common source amplifier, and the output ac current signal is generated after flowing through the load. The voltage gain of the common source amplifier is:
wherein, g m Denotes the transconductance, R, of transistor M0 out Representing the impedance of the output node. The expression is as follows:
wherein, mu n Denotes the mobility of n-type carriers, C ox Represents the unit area oxide layer capacitance, W/L represents the width-to-length ratio of the transistor M0, V dsat Denotes an overdrive voltage of the transistor M0, λ denotes a channel length modulation factor of the transistor M0, I D Representing the quiescent operating current flowing through transistor M0.
It should be noted that, when the meaning of the letter in the following expression is the same as that described above, the explanation of the letter with the same meaning will not be repeated.
Derived based on the above equation:
as can be seen from the above formula, the Voltage gain of the common-source amplifier is related to the channel length modulation factor and the overdrive Voltage, and these two parameters are related to the Process (Process), the Voltage (Voltage), and the Temperature (Temperature), and it can be seen that the Voltage gain of the common-source amplifier without the negative feedback unit will change greatly with the change of PVT.
In this embodiment, the degeneration unit 12 may be a degeneration resistor R2 or other original device. The voltage gain of the first amplification module 10 after the source degeneration resistor R2 is introduced is:
wherein, g m Denotes the transconductance, R, of the fourth transistor M1 out Representing the impedance of the output node, R 2 Denotes the impedance of the degeneration resistor R2, λ denotes the channel length modulation factor of the fourth transistor M1, I D Representing the quiescent operating current flowing through the fourth transistor M1. When the value of the source degeneration resistor R2 is sufficiently large, equation three can be approximated as:
wherein r is 0 Indicating the internal resistance of the small signal source. The equivalent transconductance is approximately equal to the inverse of the source degeneration resistor R2, and the variation of the impedance of the feedback resistor R2 with PVT can be said to be very small relative to the variation of the transconductance of the fourth transistor M1 with PVT.
However, since the equivalent impedance of the output node is still equal to the product of the source degeneration resistance and the intrinsic gain of the fourth transistor M1, and the value is greatly floated with the change of PVT, the common-source amplifier circuit with the current source load using only source degeneration still cannot meet the requirement of high stable gain. Therefore, referring to fig. 2 again, in the present application, on the basis that the first amplification module 10 is a common-source amplification circuit with source degeneration, the feedback module 20 is added, the feedback module 20 detects a voltage sampling signal output by the first amplification module 10, and generates a voltage feedback signal between the source of the fourth transistor M1 and the feedback resistor R2, and the voltage feedback signal is superimposed on the source voltage of the fourth transistor M1, thereby forming a degeneration loop. After the feedback module 20 is added, the gain of the amplifying circuit is:
wherein, g m3 Represents the transconductance, g, of the feedback module 20 ds1 Representing the drain-source conductance of the fourth transistor M1. The gain expression is similar to the reciprocal of the gain of the common-source amplification circuit shown in fig. 4, the parameter of the input transistor M1 has very little influence on the gain, and the magnitude of the gain depends on the transconductance stage and the source degeneration resistor R2 of the feedback module 20, wherein the transconductance varies greatly with PVT, and the degeneration resistor R2 varies little with PVT. Based on this, the second amplification module 30 is further provided in the present application, and by providing the second amplification module corresponding to the first amplification module 10 and the feedback module 20, the gain of the amplification circuit including the two-stage amplification of the first amplification module 10 and the second amplification module 30 is converted into a parameter that does not change with the change of voltage and temperature, thereby obtaining a gain with low PVT correlation.
It is understood that the fourth transistor M1 may be a CMOS (Complementary Metal Oxide Semiconductor), a bipolar transistor or other transistors, and in this embodiment, the fourth transistor M1 is a CMOS transistor. Further, the fourth transistor M1 may also be a P-MOS transistor or an N-MOS transistor, and the specific connection relationship between the load device 11 and the negative feedback unit 12 may also be different according to the type of the MOS transistor. When the fourth transistor M1 is a P-MOS, its source is connected to the power input VCC through the negative feedback unit 12, and its drain is grounded through the load device 11; when the fourth transistor M1 is an N-MOS, its drain is connected to the power input VCC through the load device 11, and its source is grounded through the negative feedback unit 12.
In one embodiment, as shown in fig. 2, the second amplifying module 30 includes a third transistor M7 and a load resistor R6, wherein a gate of the third transistor M7 is connected to the first transistor M3; the drain of the third transistor M7 is connected to the first end of the load resistor R6, and the second end of the load resistor R6 is connected to the power input VCC; the source of the third transistor M7 is grounded. The common end of the drain of the third transistor M7 connected to the load resistor R6 is an output end of the amplifying circuit, and is used for outputting the voltage signal Vout. The third transistor M7 may also be a MOS transistor or other transistors, and in this embodiment, the third transistor M7 is an N-MOS transistor.
In one embodiment, as shown in fig. 4, the feedback module 20 includes a first transistor M3; the grid and the drain of the first transistor M3 are connected with the first amplification module 10, and the source of the first transistor M3 is grounded; the gate of the first transistor M3 is connected to the second amplification block 30.
Specifically, the gate of the first transistor M3 is connected to the common terminal of the fourth transistor M1 connected to the load device 11, and the gate of the first transistor M3 is also connected to the gate of the third transistor M7. The drain of the first transistor M3 and the fourth transistor M1 are connected to a common terminal to which the negative feedback unit 12 is connected. Therefore, the grid electrode of the first transistor M3 detects the voltage sampling signal output by the first amplifying module 10, the voltage sampling signal is converted into a current signal through transconductance, the current signal flows through the negative feedback resistor R2 to generate a voltage feedback signal, and the voltage feedback signal is superposed on the source voltage of the fourth transistor M1 to form a negative feedback loop. In this embodiment, the fourth transistor M1 is a P-MOS transistor, and the first transistor M3 is an N-MOS transistor.
In an embodiment, as shown in fig. 2, the amplifying circuit further includes a level processing unit 21, and the level processing unit 21 is connected to the first amplifying block 10, the gate of the first transistor M3, and the second amplifying block 30. The level processing unit 21 is configured to process the voltage sampling signal output by the first amplifying module 10, convert the voltage sampling signal into a level suitable for the first transistor M3, and provide an operating level for the third transistor M7 in the second voltage amplifying module 30.
Specifically, the structure of the level processing unit 21 is not unique, and for example, a passive resistor voltage division network, an active device source follower circuit, an emitter follower circuit, or a circuit form in which a passive device resistor is connected in parallel with a capacitor and then a current source is cascaded may be used to achieve the same purpose. In an embodiment, referring to fig. 2, the level processing unit 21 includes a second transistor M4 and a first current source I5, a gate of the second transistor M4 is connected to the first amplifying module 10, and is connected to the voltage sampling signal output by the first amplifying module 10; the drain of the second transistor M4 is connected to the power input VCC, the source of the second transistor M4 is connected to the positive terminal of the first current source I5, the negative terminal of the first current source I5 is grounded, and the common terminal of the source of the second transistor M4 connected to the first current source I5 is connected to the gate of the first transistor M3 and the second amplification module 30, respectively. The current input end of the current source is a positive end, and the current output end of the current source is a negative end.
In this embodiment, the fourth transistor M1 is an N-MOS transistor, the second transistor M4 is an N-MOS transistor, and the first transistor M3 is an N-MOS transistor. The gate of the second transistor M4 is specifically connected to the common terminal of the fourth transistor M1 connected to the load device 11, the common terminal of the fourth transistor M1 connected to the negative feedback unit 12 is connected to the gate of the first transistor M3, and the gate of the first transistor M3 is further connected to the gate of the third transistor M7. Thereby, the voltage sampling signal outputted from the first amplifying module 10 is converted to be adapted to the first transistor M3 and the third transistor M7.
In another embodiment, referring to fig. 5, the level converting unit 21 includes a second transistor M4 and a first current source I5; the grid of the second transistor M4 is connected to the bias voltage Vbias, the drain of the second transistor M4 is connected with the positive terminal of the first current source I5, and the negative terminal of the first current source I5 is grounded; the source of the second transistor M4 is connected to the first amplification module 10; the common terminal of the source of the second transistor M4 connected to the first current source I5 is connected to the gate of the first transistor M3 and the second amplifying block 30, respectively. The source of the second transistor M4 is specifically connected to the common terminal of the fourth transistor M1 to the load device 11. The bias voltage Vbias can be set according to actual conditions. Specifically, the second transistor M4 may be a P-MOS transistor for level conversion, the fourth transistor M1 may be an N-MOS transistor, and the first transistor M3 may be an N-MOS transistor. Therefore, the levels of the points A and B are isolated, the pole of the point B is higher, the bandwidth is higher, and the level of the point A is adjusted by the second transistor M4 through the bias voltage Vbias.
In practical design, the third transistor M7 is matched to the first transistor M3, and the degeneration resistor R2 is matched to the load resistor R6. When the load device 11 selects the second current source I0 and the degeneration unit 12 selects the degeneration resistor R2, the gain expression of the amplifying circuit in the embodiment shown in fig. 2 is:
wherein, g m3 Denotes the transconductance, g, of the first transistor M3 m7 The transconductance R of the third transistor M7 is shown 6 Representing the impedance of the load resistor R6. It can be seen that the gain is highly robust.
Since the operating conditions of the first transistor M3 and the third transistor M7 are the same, on the premise that only the first-order effect of the circuit is considered and the channel length modulation effect is ignored, the gain of the amplifying circuit is:
wherein, W 3 Denotes the width, L, of the conduction channel of the first transistor M3 3 Denotes the length, W, of the conduction channel of the first transistor M3 7 Indicates the width, L, of the conduction channel of the third transistor M7 7 Indicating the length of the conduction channel of the third transistor M7.
According to the second formula, the gain of the amplifying circuit is the product of the ratio of the width-length ratios of two transistors of the same type and the resistance ratio, the ratio of the width-length ratios of the transistors in adjacent areas on a printed circuit board diagram has small difference of resistance values of the resistors, the width-length ratios of the transistors are not changed along with the changes of voltage and temperature, and the ratio of the resistance values of the resistors is changed along with the changes of the voltage and the temperature to a very small extent, so that the circuit shown in fig. 2 can obtain the gain with low correlation with PVT, and the gain robustness is high.
However, for more precise consideration, based on the insertion of the fourth transistor M1 in the circuit for level conversion, the gain of the amplifying circuit can be corrected to be:
the gain of the amplifying circuit in the embodiment shown in fig. 4 is:
therefore, it can be seen that the gain of the amplifying circuit in the embodiment shown in fig. 4 is converted into a product of the ratio of the width-to-length ratio of the transistor device and the ratio of the resistance value of the passive resistor, and each ratio in the gain is not affected by PVT, so that the gain of the amplifying circuit has lower dependence on PVT, and the second transistor M4 is omitted from the circuit, and the gain is more accurate without considering the substrate bias effect.
Referring again to the first formula, since it is sufficient to make the gain expression approximately equal to the right side of the formula when the transconductance of the input fourth transistor M1 is much larger than the conductance of the drain and the source, in order to reduce the difference between the approximate value and the actual value, the transconductance of the fourth transistor M1 may be increased as much as possible. In the tsmc65nm process, under the same current and size conditions, the input transconductance obtained by using the N-MOS transistor is 50% larger than that of the P-MOS transistor, so that the fourth transistor M1 can obtain better benefit by using the N-MOS transistor.
The embodiment shown in fig. 5 is an amplifying circuit using an N-MOS transistor as an input transistor (the fourth transistor M1 uses an N-MOS transistor), and compared with the amplifying circuit in the embodiment shown in fig. 4, the amplifying circuit with N-type input not only can efficiently provide input transconductance, but also has the characteristic of high bandwidth, particularly because:
first, under the same current and size conditions, the input transconductance obtained by using the N-MOS transistor is 50% larger than that of the P-MOS transistor, so that the fourth transistor M1 can introduce a smaller load capacitance at the input end and the active region node by using the N-MOS transistor.
Second, inverting amplifiers tend to introduce the miller effect. The miller capacitance formed by the gate-drain capacitance of the fourth transistor M1 at node a, where the impedance can be approximated as:
wherein, g ds4 Represents the drain-source conductance, g, of the second transistor M4 ds5 Representing the transconductance of the first current source I5.
The capacitance at node A represents C A ＝C miller +C D0 +C S4 In which C is miller Denotes the Miller capacitance, C, of the fourth transistor M1 D0 Represents the drain parasitic capacitance, C, of the second current source I0 S4 Representing the parasitic capacitance of the source of the second transistor M4.
The corresponding output resistance and miller capacitance of the amplifying circuit in fig. 5 are at the node a:
The capacitance is as follows: c A ＝C miller +C D0 +C G3 +C G7 Wherein, C A Capacitance of node A, C miller Denotes the Miller capacitance, C, of the fourth transistor M1 G3 And C G7 The gate capacitances of the first transistor M3 and the third transistor M7 are respectively indicated.
The poles corresponding to node C in fig. 4 are:
wherein, pole 5C Represents the pole of node C in FIG. 4, C c Represents the parasitic capacitance at node C, g ds0 Representing the transconductance of the second current source I0.
The poles corresponding to node C in fig. 6 are:
wherein, the pole 6C Represents the pole of node C in FIG. 5, C c Representing the parasitic capacitance at node C.
Compared with the amplifying circuit in fig. 4, the amplifying circuit in fig. 5 has more node B, and the corresponding poles of the node B are:
wherein, C B Representing the parasitic capacitance at node B, C B ＝C G3 +C G7 From the distribution of the poles, it follows that the amplifier circuit in fig. 5 will have a larger bandwidth than the amplifier circuit in fig. 4.
It should be noted that, referring to fig. 6, the feedback module 20 in the above embodiment may be characterized as a transconductance amplifier Gm3, and functions to convert a voltage signal at an input end into a feedback current signal through the transconductance amplifier Gm3, specifically, detect an output voltage signal at an output end of the first amplification module 10, convert the output voltage signal into the feedback current signal through the transconductance amplifier Gm3, feed the feedback current signal back to the degeneration resistor R2 at the source of the fourth transistor M1 to form a voltage feedback signal, and subtract the input voltage Vin from the voltage signal, so as to adjust the output voltage of the first amplification module 10. The above embodiments are only alternative implementations of the transconductance stage amplifier Gm3, and the transconductance stage amplifier Gm3 may also have other implementations, which are not limited herein.
In one embodiment, the first amplification module 10 further includes a source degeneration capacitor connected in parallel with the negative feedback unit 12; the second amplifying module 30 further includes a load capacitor, a first end of the load capacitor is connected to the drain of the third transistor M7, and a second end of the load capacitor is grounded. By adding the source degeneration capacitance, a zero point can be introduced into the transmission equation of the amplifying circuit, so that the bandwidth of the amplifying circuit is improved.
In practical application, referring to fig. 7-8, the source degeneration capacitanceC8 is connected in parallel at two ends of the negative feedback resistor R2 and is loaded with a capacitor C load One end is connected to the output end of the second amplification module 30, and the other end is grounded.
The transmission equation and the pole-zero of the amplifying circuit in the embodiment shown in fig. 7 are:
wherein H(s) represents the transmission equation of the amplifying circuit, s represents the Laplace operator, C8 represents the capacitance value of the source degeneration capacitor C8, C load Representing the load capacitance C load The capacitance value of (c) zero (w) represents zero point, pole 1 Represents the pole 1, pole 2 Represents pole 2, pole 3 Representing the pole 3.
The transfer equation for the amplification circuit in the embodiment shown in fig. 8 is:
wherein, pole 4 Representing the pole 4. From the two transfer equations and the expression of the pole zero, pole can be determined 2 Being dominant, the other poles are non-dominant and are very far from the dominant pole. The existence of the zero point can reduce the drop of the gain caused by the dominant pole and hardly affect the phase, so that the amplifier circuit can provide stable gain and extremely high bandwidth after adding the degenerated capacitor. The amplifier circuit has the characteristics of stable gain, high working bandwidth, high linearity and capability of working in a low voltage domain, and is suitable for integrated circuits with various working bandwidth requirements, high gain robustness requirements, high linearity and low voltage domains.
In one embodiment, a differential amplifier circuit is provided, as shown in fig. 9, comprising a first amplifier circuit 100 and a second amplifier circuit 200, wherein the first amplifier circuit 100 is connected to the second amplifier circuit 200.
The structures of the first amplification circuit 100 and the second amplification circuit 200 can be arranged according to the amplification circuits in the above embodiments, and the structures of the first amplification circuit 100 and the second amplification circuit 200 are arranged correspondingly. In one embodiment, as shown in fig. 10, the first amplification circuit 100 includes a first amplification module 110, a feedback module 120, and a second amplification module 130; the first amplifying module 110 is configured to access the input differential voltage signal Vinp, the feedback module 120 is connected to the first amplifying module 110, and the second amplifying module 130 is connected to the feedback module 120 and configured to output the differential voltage signal Voutp. The second amplification circuit 200 includes a first amplification module 210, a feedback module 220, and a second amplification module 230; the first amplifying module 210 is configured to access an input differential voltage signal Vinm, the feedback module 220 is connected to the first amplifying module 210, and the second amplifying module 230 is connected to the feedback module 220 and configured to output a differential voltage signal Voutm.
The first amplification module 110 includes a transistor M11, a current source I10 and a degeneration resistor R12, the first amplification module 210 includes a transistor M21, a current source I20 and a degeneration resistor R22, the transistors M11 and M21 are P-MOS transistors, wherein the degeneration resistors R12 and R22 are connected, so that a P-type input differential amplification circuit is formed by connecting two source degeneration resistors.
In the embodiment shown in fig. 10, a tail current source I18 may be further disposed in the first amplifying module 110 in the first amplifying circuit 100, and the source of the transistor M11 is connected to the power supply input terminal VCC through the tail current source I18. Correspondingly, the tail current source I28 is disposed in the first amplifying module 210 in the second amplifying circuit 200, and the source of the transistor M21 is connected to the power supply input terminal VCC through the tail current source I28. By setting the tail current source, the tail current flows through each source negative feedback resistor R12 and R22, thereby generating voltage drop, consuming voltage margin and compressing the input common mode range of the differential amplifying circuit.
Further, as shown in fig. 11, the first amplification module 110 in the first amplification circuit 100 may further be respectively provided with source degeneration capacitors C18, and the first amplification module 210 in the second amplification circuit 200 is correspondingly provided with source degeneration capacitors C28. One end of source degeneration capacitor C18 is connected to the source of input transistor M11, the other end of source degeneration capacitor C18 is connected to one end of source degeneration capacitor C28, and the other end of source degeneration capacitor C28 is connected to the source of transistor M21. Through testing, under the supply voltage supply of 1V at the tsmc65nm technology, the differential amplifier circuit with the source electrode degradation capacitor can obtain the gain of 11 +/-1 dB and the bandwidth of 2.5 GHz.
In an embodiment, as shown in fig. 12, in the differential amplifier circuit, the two transistors M11 and M21 in the first amplifier module 110 in the first amplifier circuit 100 and the first amplifier module 210 in the second amplifier circuit 200 are both N-MOS transistors, and the feedback resistors R12 and R22 of the two first amplifier modules are connected, so as to form an N-input differential amplifier circuit. The difference from the structure shown in fig. 10 is that the source of the transistor M11 is grounded via the tail current source I18, and the source of the transistor M21 is grounded via the tail current source I28.
Further, as shown in fig. 13, the first amplification module 110 in the first amplification circuit 100 may further be respectively provided with source degeneration capacitors C18, and the first amplification module 210 in the second amplification circuit 200 is correspondingly provided with source degeneration capacitors C28. One end of the source degeneration capacitor C18 is connected to the source of the input transistor M11, the other end of the source degeneration capacitor C18 is connected to one end of the source degeneration capacitor C28, and the other end of the source degeneration capacitor C28 is connected to the source of the transistor M21. Through testing, under the supply voltage of 1V at the tsmc65nm technology, the differential amplifier circuit with the source electrode degradation capacitance of the input transistors M11 and M21 which are both N-type inputs can obtain the gain of 11 +/-1 dB and the bandwidth of 5 GHz.
When smoothing of the gain curve is desired, the differential operational amplifier circuit without the source degeneration capacitor as illustrated in fig. 10 and 12 still has an operating bandwidth of 1GHz or more.
In an embodiment, an amplifier is further provided, which includes an amplifying circuit and/or a differential amplifying circuit, and the structures of the amplifying circuit and the differential amplifying circuit may be configured by referring to the foregoing embodiments, and are not described herein again.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An amplification circuit, comprising:
the first amplification module is used for accessing an input voltage signal and outputting a voltage sampling signal;
the feedback module is connected with the first amplification module, receives the voltage sampling signal and outputs a voltage feedback signal to the first amplification module;
and the second amplification module is connected with the feedback module and used for outputting a voltage signal.
2. The amplifier circuit of claim 1, wherein the feedback module comprises a first transistor; the grid electrode and the drain electrode of the first transistor are connected with the first amplification module, and the source electrode of the first transistor is grounded.
3. The amplification circuit according to claim 2, further comprising a level processing unit; the level processing unit is connected with the first amplification module, the grid of the first transistor and the second amplification module.
4. The amplifying circuit according to claim 3, wherein the level processing unit includes a second transistor and a first current source, a gate of the second transistor is connected to the voltage sampling signal; the drain electrode of the second transistor is connected with the power input end, the source electrode of the second transistor is connected with the positive end of the first current source, the negative end of the first current source is grounded, and the source electrode of the second transistor and the public end connected with the first current source are respectively connected with the grid electrode of the first transistor and the second amplification module.
5. The amplifier circuit according to claim 3, wherein the level processing unit includes a second transistor and a first current source; the grid electrode of the second transistor is connected with a bias voltage, the drain electrode of the second transistor is connected with the positive end of the first current source, and the negative end of the first current source is grounded; the source electrode of the second transistor is connected with the first amplification module; and the source electrode of the second transistor and the common end of the first current source are respectively connected with the grid electrode of the first transistor and the second amplification module.
6. The amplifying circuit according to any one of claims 1 to 5, wherein the second amplifying module comprises a third transistor and a load resistor, a gate of the third transistor being connected to the feedback module; the drain electrode of the third transistor is connected with the first end of the load resistor, the second end of the load resistor is connected with the power supply input end, and the source electrode of the third transistor is grounded; and the common end of the drain electrode of the third transistor, which is connected with the load resistor, is used for outputting a voltage signal.
7. The amplifying circuit according to claim 6, wherein the first amplifying module comprises a fourth transistor, a load device and a negative feedback unit; the grid electrode of the fourth transistor is used for connecting an input voltage signal; the drain electrode of the fourth transistor is connected with the load device; the source electrode of the fourth transistor is connected with the negative feedback unit; the drain electrode of the fourth transistor is connected with the common end connected with the load device and the feedback module, and the feedback module is further connected with the common end connected with the source electrode of the fourth transistor and the negative feedback unit.
8. The amplification circuit according to claim 7, wherein the first amplification block further comprises a source degeneration capacitance connected in parallel with the negative feedback unit;
the second amplification module further comprises a load capacitor, a first end of the load capacitor is connected with the drain electrode of the third transistor, and a second end of the load capacitor is grounded.
9. A differential amplification circuit, comprising: the first amplifying circuit is connected with the second amplifying circuit; wherein the first and second amplification circuits are each as claimed in any one of claims 1 to 8.
10. An amplifier comprising an amplifying circuit according to any one of claims 1 to 8 and/or a differential amplifying circuit according to claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211252902.5A CN115498970A (en) | 2022-10-13 | 2022-10-13 | Amplifying circuit, differential amplifying circuit and amplifier |
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| CN202211252902.5A CN115498970A (en) | 2022-10-13 | 2022-10-13 | Amplifying circuit, differential amplifying circuit and amplifier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117411449A (en) * | 2023-12-14 | 2024-01-16 | 浙江地芯引力科技有限公司 | Current sampling amplifying circuit, chip and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117411449A (en) * | 2023-12-14 | 2024-01-16 | 浙江地芯引力科技有限公司 | Current sampling amplifying circuit, chip and electronic equipment |
| CN117411449B (en) * | 2023-12-14 | 2024-04-05 | 浙江地芯引力科技有限公司 | Current sampling amplifying circuit, chip and electronic equipment |
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