CN103001493B - Simple linear power source circuit - Google Patents

Abstract

The invention discloses a simple linear power source circuit. The simple linear power source circuit generates current via threshold voltage of an active device, the current is adopted as reference current of the circuit, namely the reference current is generated by bootstrap reference and the MOS (metal oxide semiconductor) threshold voltage is used as reference voltage, and a simple linear power source is realized by combining with a feedback principle, and the power source is free of affection from a system power source VDD (voltage drain drain).

Description

A kind of simple linear power supply circuit

Technical field

The present invention relates generally to the design field of power circuit, refers in particular to a kind of simple linear power supply circuit.

Background technology

For analog integrated circuit, the quality of its performance depends on several factors, wherein the quality of power supply is also a key factor that affects analog integrated circuit performance, particularly some high-precision analog circuit, as high-precision adc (ADC), high precision digital-to-analog converter (DAC), instrument amplifier etc., this class circuit all needs a high-quality Power supply conventionally, conventionally be all to adopt linear power supply (LDO), LDO converts a bad power supply signal of performance to performance power supply output relatively preferably, the performance of LDO is conventionally all fine, but the area taking is also larger, for some simple modules, or the circuit module that scale is less, and not again in extra high situation to the performance requirement of power supply, LDO is not a wise selection.

Summary of the invention

The problem to be solved in the present invention is just: the technical problem existing for prior art, proposes a kind of simple linear power supply circuit.

The solution that the present invention proposes is: this circuit is by the threshold voltage generation current of active device, and adopt the reference current of this electric current as circuit, produce reference current with bootstrapping benchmark, with metal-oxide-semiconductor threshold voltage as with reference to voltage, realized a simple linear power supply in conjunction with negative-feedback principle again, this power supply is not subject to the impact of system power supply VDD.

Brief description of the drawings

Fig. 1 is circuit theory schematic diagram of the present invention;

Embodiment

Below with reference to accompanying drawing and concrete enforcement, the present invention is described in further details.

As shown in Figure 1, PMOS pipe M ₃the diode form that is grid leak short circuit connects, and its source voltage is M ₃threshold voltage, suppose that it is V _tH3, this threshold voltage is managed M as PMOS ₈gate bias voltage, NMOS manages M ₁₀grid voltage be always M ₁₀threshold voltage, suppose that it is V _tH10, PMOS manages M ₄, M ₅size identical, NMOS manages M ₉, M ₁₀size also identical, M ₉and M ₁₀leakage current I _dSequate i.e. I _dS9=I _dS10, I _dS10m flows through ₁₀produce voltage V _gS10, I _dS9r flows through ₂produce voltage I _dS9r ₂, these two voltages are same voltage,

$I_{\mathrm{DS}9}{R}_2=V_{\mathrm{TH}10}+{\left(\frac{I_{\mathrm{DS}10}}{K_n}\right)}^{\frac{1}{2}}---\left(1\right)$

Wherein suppose I _dS9=I _dS10=I _q, through type (1) can draw

$I_Q=\frac{V_{\mathrm{TH}10}}{R_2}+\frac{1}{2K_n{R}_2^2}+\frac{1}{R_2}\sqrt{\frac{V_{\mathrm{TH}10}}{K_n{R}_2}+\frac{1}{4K_n^2{R}_2^2}}---\left(2\right)$

Can find out I from formula (2) _qirrelevant with power vd D.

Resistance R ₃resistance be resistance R ₂half, NMOS manages M ₉and M ₁₀size just the same, flow through NMOS pipe M ₁₁electric current I _dS11=I _q, reach the balance of circuit, PMOS pipe M ₈leakage current also equal I _q,

I _Q=K _p(V _O-|V _TH3|-|V _TH8|) ²(3)

Wherein V _tH8pMOS pipe M ₈threshold voltage, through type (2) and formula (3) can obtain the value of output voltage,

$V_O=\sqrt{\frac{V_{\mathrm{TH}10}}{K_p{R}_2}+\frac{1}{2K_p{K}_n{R}_2^2}+\frac{1}{K_p{R}_2}\sqrt{\frac{V_{\mathrm{TH}10}}{K_n{R}_2}+\frac{1}{4K_n^2{R}_2^2}}}+\left|V_{\mathrm{TH}3}\right|+\left|V_{\mathrm{TH}8}\right|---\left(4\right)$

Can be found out output voltage V by formula (4) _oirrelevant with supply voltage VDD, only and technological parameter and the resistance R of metal-oxide-semiconductor ₂relevant, its concrete value can be by adjusting metal-oxide-semiconductor size and resistance R ₂resistance change.

As shown in Figure 1, resistance R _lit is load.Suppose M ₁₁source voltage be V _pif, load R _lreduce, i.e. I _lincrease V _oreduce I _dS8reduce V _preduce, because I _dS11=I _qsteady state value, therefore M ₁₁drain-source voltage V _dSreduce, i.e. PMOS pipe M ₇v _gSincrease, output driving current increases, compensation I _l, keep V _oconstant; Together should load R _lwhen increase, i.e. I _lreduce, V _oincrease I _dS8increase V _praise, because I _dS11=I _qsteady state value, therefore M ₁₁drain-source voltage V _dSincrease, i.e. PMOS pipe M ₇v _gSreduce, output driving current reduces, compensation I _l, keep V _oconstant.

In sum, this circuit produces reference current with bootstrapping benchmark, has realized a simple linear power supply in conjunction with negative-feedback principle, and this power supply is not subject to the impact of system power supply VDD.

Claims (1)

1. a simple linear power supply circuit, is characterized in that:

Circuit is managed M by PMOS ₁, PMOS manages M ₂, PMOS manages M ₃, PMOS manages M ₄, PMOS manages M ₅, PMOS manages M ₆, PMOS manages M ₇, PMOS manages M ₈, NMOS manages M ₉, NMOS manages M ₁₀, NMOS manages M ₁₁, resistance R ₁, resistance R ₂and resistance R ₃composition; System power supply VDD is connected to PMOS pipe M ₁, M ₄, M ₅, M ₆and M ₇source electrode, earth signal GND is connected to PMOS pipe M ₃grid and drain electrode, resistance R ₂one end, resistance R ₃one end and NMOS pipe M ₁₀source electrode; Resistance R ₁one end be connected to PMOS pipe M ₁drain electrode, the other end is connected to PMOS pipe M ₄, PMOS manages M ₅with PMOS pipe M ₆grid and PMOS pipe M ₂source electrode, PMOS manages M ₂drain electrode is connected to PMOS pipe M ₃source electrode and PMOS pipe M ₈grid, PMOS manages M ₂grid is connected to PMOS pipe M ₁grid, PMOS manage M ₄drain electrode and NMOS pipe M ₉drain electrode; NMOS manages M ₉source electrode be connected to resistance R ₂the other end and NMOS pipe M ₁₀grid, NMOS manages M ₉grid is connected to NMOS pipe M ₁₀drain electrode, NMOS manage M ₁₁grid and PMOS pipe M ₅drain electrode; PMOS manages M ₆drain electrode is connected to PMOS pipe M ₇grid and NMOS pipe M ₁₁drain electrode, NMOS manages M ₁₁source electrode be connected to PMOS pipe M ₈drain electrode and resistance R ₃the other end, PMOS manages M ₇drain electrode and PMOS pipe M ₈source electrode links together and forms the output V of linear power supply _o; Wherein PMOS pipe M ₄, M ₅size identical, NMOS manages M ₉, M ₁₀size also identical, resistance R ₃resistance be resistance R ₂half.