CN105676938A - Voltage reference source circuit with ultra-low power consumption and high power supply rejection ratio - Google Patents

Abstract

The invention provides a voltage reference source circuit with ultra-low power consumption and a high power supply rejection ratio.The voltage reference source circuit comprises a starting circuit unit, a current generation circuit unit and an output voltage reference circuit unit which are electrically connected in sequence.The staring circuit unit is used for providing starting voltage and preventing the voltage reference source circuit from working in a zero-state zone.The current generation circuit unit is used for generating working current for the output voltage reference circuit unit and lowering the power consumption of the voltage reference source circuit at the same time.The output voltage reference circuit unit is used for achieving voltage reference output at a zero temperature coefficient and a high power supply rejection ratio.The voltage reference source circuit has the advantages of being ultra-low in power consumption, low in temperature coefficient, high in power supply rejection ratio, wide in working voltage range and small in size.

Description

A kind of super low-power consumption high PSRR voltage reference source circuit

Technical field

The present invention relates to voltage reference source circuit field, more specifically, it relates to a kind of super low-power consumption high PSRR voltage reference source circuit.

Background technology

Reference source circuit has the outstanding advantage almost unrelated with voltage of supply, technique, temperature variation, therefore being widely used in the comparer of high precision, A/D or D/A transmodulator, LDO voltage stabilizer and other many analog integrated circuit, the precision and stability of its reference voltage provided determines the final performance of whole system.

Following performance index are mainly considered: temperature factor, operating voltage scope, power supply rejection ratio and power consumption when reference source circuit designs. The output voltage temperature influence of the more low i.e. reference source circuit of temperature factor is more little, and voltage is more stable; Bigger working range can make reference source circuit be more applicable in different circuit; It is very little that high PSRR illustrates that a reference source exports the variable effect by input voltage, thus more stable; Low-power consumption is the present requirement to power management chip.

In a reference source designs, in order to obtain the amount unrelated with temperature, the amount normally having opposite temperature coefficients with two is added with suitable weight. The base-emitter voltage VBE of bipolar transistor has negative temperature coefficient, two base emitter junction difference in voltage Δ VBE under different emitter junction current density have positive temperature coefficient, by both linear superposition, the votage reference of zero-temperature coefficient can be obtained so in theory.

Fig. 1 is existing band-gap reference circuit. Here, amplifier is using X, Y as input, and the high gain of amplifier makes the current potential approximately equal of X, Y 2, and R1=R2, so the electric current flowing through two triodes is equal, it is possible to obtain expression formula:

V_BE1=V_BE2+R₃I(1)

Q1 and Q2 base-emitter difference in voltage is

V_BE1-V_BE2=V_Tlnn(2)

Thus can obtain the expression formula of output voltage:

$V_{out}=V_{BE2}+\frac{V_T\ln n}{R_3}(R_2+R_3)=V_{BE2}+V_T\ln n(1+\frac{R_2}{R_3})---\left(3\right)$

By rationally arranging n and the value of resistance R, then obtain zero-temperature coefficient.

Along with large-scale application and the development of portable electric appts, the low-power consumption of chip becomes the key index of chip design, and the operating voltage of chip is also more and more lower. The power consumption that the output voltage (1.2V) that this kind of traditional band-gap reference circuit is too high and being difficult to reduces, and bigger circuit area (use of resistance) limits its further development and application to a certain extent.

Summary of the invention

The present invention overcomes the defect of the high power consumption described in above-mentioned prior art, it is provided that a kind of super low-power consumption high PSRR voltage reference source circuit, has the advantage that super low-power consumption, low-temperature coefficient, high PSRR, wider operating voltage scope and area are little.

For solving the problems of the technologies described above, the technical scheme of the present invention is as follows:

A kind of super low-power consumption high PSRR voltage reference source circuit, comprises the startup circuit unit, current generating circuit unit and the output voltage reference circuit unit that are electrically connected in turn;

Described startup circuit unit, for providing trigger voltage, avoids voltage reference source circuit to be operated in zero condition district;

Described current generating circuit unit is used for making the lower power consumption of voltage reference source circuit for output voltage reference circuit unit produces working current simultaneously;

Described output voltage reference circuit unit exports for realizing the voltage benchmark of zero-temperature coefficient and high PSRR.

In the preferred scheme of one, described startup circuit unit comprises NMOS tube MS1, MS2, and PMOS MC, drain electrode and the source electrode of MC are all connected with power supply, and the grid of MC is connected with the grid of MS2, and the drain electrode of MS2 and source electrode draw the first initiating signal output terminal and the 2nd initiating signal output terminal respectively, initiating signal is provided to current generating circuit unit, the drain electrode of MS1 is connected with the grid of MS2, and the source ground of MS1, the grid of MS1 is connected to voltage-reference output terminal VREF.

Drain electrode and the source electrode of MC link together, and play electric capacity, thus decrease the area of circuit structure in startup circuit.

In the preferred scheme of one, described current generating circuit unit comprises NMOS tube M1, M2, M3, M4, M11, M12 and PMOS M13, M14, M15; Described M13, M14 and M15 connect with current-mirror structure, namely M13 grid is connected with drain electrode, the grid of M13, M14 and M15 connects and draws generation current output terminal, and the first initiating signal output terminal with described startup circuit unit is connected, and the source electrode of M13, M14 and M15 connects power supply; M3 and M4 is connected into diode respectively, namely the respective grid of M3 with M4 is connected with drain electrode, the source ground of M3 and M4, the source electrode of M1 and the drain electrode of M3 connect, the drain electrode of M1 connects with the drain electrode of M14, and the source electrode of M2 and the drain electrode of M4 connect, and the drain electrode of M2 connects with the drain electrode of M15, the drain and gate of M2 is all connected with the grid of M1, and the 2nd initiating signal output terminal with described startup circuit unit is connected; The grid of M12 is connected with the drain electrode of M1, and the drain electrode of M12 connects with the drain electrode of M13, and the drain electrode of M11 connects with the source electrode of M12, and the grid of M11 receives drain electrode, connects into diode, the source ground of M11.

In the preferred scheme of one, M1, M2 in described current generating circuit unit are operated in saturation region, and M3, M4, M11, M12, M13, M14, M15 are operated in sub-threshold region.

In the preferred scheme of one, described output voltage reference circuit unit comprises PMOS M10, M16, M17, M18 and NMOS tube M5, M6, M7, M8, M9; The grid of described M16, M17, M18 is connected, as the input terminus of output voltage reference circuit unit, it is connected with the generation current output terminal of described current generating circuit unit, the source electrode of M16, M17, M18 connects power supply, and the drain and gate of M5 and the grid of M6 are connected with the drain electrode of M16, and the drain electrode of M6 is connected with the source electrode of M5, the source ground of M6, the source electrode of M7 is connected with the drain electrode of M6, and the drain electrode of M7 is connected with the drain electrode of M17, and the grid of M7 receives benchmark output terminal;The drain electrode of M8 connects power supply, the grid of M8 is connected with the drain electrode of M7, the drain electrode of M9 is connected with the source electrode of M8, the grid of M9 receives the grid of described M4, the grid of M10 is connected with the drain electrode of M9, the source electrode of M9 and the drain electrode ground connection of M10, the source electrode of M10 is connected with the drain electrode of M18, and is connected to voltage-reference output terminal V_REF。

M8, M9, M10 and M18 introduce reverse feedback so that the output resistance of VREF end reduces greatly, thus substantially increase power supply rejection ratio.

In the preferred scheme of one, in described output voltage reference source circuit unit, all MOS pipe is all be operated in sub-threshold region.

In the preferred scheme of one, the voltage of described power supply is 1.8V.

Compared with prior art, the useful effect of technical solution of the present invention is: the present invention provides a kind of super low-power consumption high PSRR voltage reference source circuit, comprises the startup circuit unit, current generating circuit unit and the output voltage reference circuit unit that are electrically connected in turn; Described startup circuit unit, for providing trigger voltage, avoids voltage reference source circuit to be operated in zero condition district; Described current generating circuit unit is used for making the lower power consumption of voltage reference source circuit for output voltage reference circuit unit produces working current simultaneously; Described output voltage reference circuit unit exports for realizing the voltage benchmark of zero-temperature coefficient and high PSRR. The present invention has the little advantage of super low-power consumption, low-temperature coefficient, high PSRR, wider operating voltage scope and area.

Accompanying drawing explanation

Fig. 1 is be the schematic circuit of existing band-gap reference circuit

Fig. 2 is the schematic circuit of super low-power consumption high PSRR voltage reference source circuit of the present invention.

Embodiment

Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent; To those skilled in the art, some known features and illustrate and may omit and be appreciated that in accompanying drawing.

Below in conjunction with drawings and Examples, the technical scheme of the present invention is described further.

Embodiment 1

As shown in Figure 2, a kind of super low-power consumption high PSRR voltage reference source circuit, comprises the startup circuit unit, current generating circuit unit and the output voltage reference circuit unit that are electrically connected in turn;

Described startup circuit unit, for providing trigger voltage, avoids voltage reference source circuit to be operated in zero condition district;

Described current generating circuit unit is used for making the lower power consumption of voltage reference source circuit for output voltage reference circuit unit produces working current simultaneously;

Described output voltage reference circuit unit exports for realizing the voltage benchmark of zero-temperature coefficient and high PSRR.

The threshold voltage of CMOS varies with temperature and changes, and has negative temperature coefficient, and its expression formula is

V_TH=V_TH(T₀)-κ(T-T₀)(4)

If the source lining voltage VSB of CMOS is not zero, it is contemplated that effect of bulk effect, threshold voltage expression formula is

$V_{TH}^{*}=V_{TH}+(\mathrm{\η}-1)V_{SB}---\left(5\right)$

The current-voltage characteristic of CMOS tube being operated in saturation region and sub-threshold region is respectively such as formula shown in (6) (7)

$I_{DS}=\frac{1}{2}{\mathrm{\μC}}_{ox}K{(V_{GS}-V_{TH})}^2---\left(6\right)$

$I_{DS}={\mathrm{\μC}}_{ox}K(\mathrm{\η}-1)V_T^2\exp \left(\frac{V_{GS}-V_{TH}}{{\mathrm{\ηV}}_T}\right).---\left(7\right)$

Wherein VT is that pyrovoltage (VT=kBT/q) has positive temperature coefficient, and K is the breadth-length ratio of CMOS tube, and ID is drain current, and μ is carrier mobility, and COX is gate oxide capacitance, and η is the sub-threshold slope factor.

In the present embodiment, in super low-power consumption high PSRR voltage reference source circuit, the voltage of supply of MOS pipe is 1.8V, whole low-power reference source circuit only employs MOS pipe and does not use electric capacity and resistance, thus reduce the area of circuit, and circuit working in sub-threshold region thus only produces less power consumption.

As shown in Figure 2, described startup circuit unit comprises NMOS tube MS1, MS2, and PMOS MC, drain electrode and the source electrode of MC are all connected with power supply, and the grid of MC is connected with the grid of MS2, and the drain electrode of MS2 and source electrode draw the first initiating signal output terminal and the 2nd initiating signal output terminal respectively, initiating signal is provided to current generating circuit unit, the drain electrode of MS1 is connected with the grid of MS2, and the source ground of MS1, the grid of MS1 is connected to voltage-reference output terminal VREF.

Drain electrode and the source electrode of MC link together, and play electric capacity, thus decrease the area of circuit structure in startup circuit.

As shown in Figure 2, described current generating circuit unit comprises NMOS tube M1, M2, M3, M4, M11, M12 and PMOS M13, M14, M15; Described M13, M14 and M15 connect with current-mirror structure, namely M13 grid is connected with drain electrode, the grid of M13, M14 and M15 connects and draws generation current output terminal, and the first initiating signal output terminal with described startup circuit unit is connected, and the source electrode of M13, M14 and M15 connects power supply; M3 and M4 is connected into diode respectively, namely the respective grid of M3 with M4 is connected with drain electrode, the source ground of M3 and M4, the source electrode of M1 and the drain electrode of M3 connect, the drain electrode of M1 connects with the drain electrode of M14, and the source electrode of M2 and the drain electrode of M4 connect, and the drain electrode of M2 connects with the drain electrode of M15, the drain and gate of M2 is all connected with the grid of M1, and the 2nd initiating signal output terminal with described startup circuit unit is connected; The grid of M12 is connected with the drain electrode of M1, and the drain electrode of M12 connects with the drain electrode of M13, and the drain electrode of M11 connects with the source electrode of M12, and the grid of M11 receives drain electrode, connects into diode, the source ground of M11.

Voltage-current relationship according to M1, M2, M3 and M4 tie point can obtain the expression formula of electric current, by regulating its breadth-length ratio can just obtain required outward current. In addition, M11, M12 and M13 introduce reverse feedback, it is ensured that A and B two point voltage is equal, what reduce that channel length modulation causes does not mate, so that the electric current produced is not almost with mains voltage variations, it is to increase a reference source power supply rejection ratio.

Current generating circuit unit is connected with described startup circuit unit, to guarantee that circuit can normally start, disconnects when starting circuit unit after normal circuit operation simultaneously, thus reduces power consumption.

In described current generating circuit unit, M1, M2 are operated in saturation region, and M3, M4, M11, M12, M13, M14, M15 are operated in sub-threshold region.

Connection relation according to M1, M2, M3, M4, it is possible to obtain

V_GS1+V_GS3=V_GS2+V_GS4(8)

Wushu (5) (6) substitute into formula (8), can obtain

$V_{GS3}+V_{TH1}+(\mathrm{\η}-1)V_{GS3}+\sqrt{\frac{2I}{{\mathrm{\μC}}_{ox}{K}_1}}=V_{GS4}+V_{TH2}+(\mathrm{\η}-1)V_{GS4}+\sqrt{\frac{2I}{{\mathrm{\μC}}_{ox}{K}_2}}---\left(9\right)$

Wushu (7) substitutes into formula (9) and abbreviation, obtains current expression

$I=\frac{1}{2}{\mathrm{\μC}}_{ox}{\[{\mathrm{\η}}^2{V}_T\frac{\sqrt{K_1{K}_2}}{\sqrt{K_1}-\sqrt{K_2}}ln\frac{K_4}{K_3}\]}^2---\left(10\right)$

M11, M12 and M13 introduce reverse feedback, it is ensured that A and B two point voltage is equal, what reduce that channel length modulation causes does not mate, so that the electric current produced is not almost with mains voltage variations, it is to increase the power supply rejection ratio of a reference source.

As shown in Figure 2, described output voltage reference circuit unit comprises PMOS M10, M16, M17, M18 and NMOS tube M5, M6, M7, M8, M9; The grid of described M16, M17, M18 is connected, as the input terminus of output voltage reference circuit unit, it is connected with the generation current output terminal of described current generating circuit unit, the source electrode of M16, M17, M18 connects power supply, and the drain and gate of M5 and the grid of M6 are connected with the drain electrode of M16, and the drain electrode of M6 is connected with the source electrode of M5, the source ground of M6, the source electrode of M7 is connected with the drain electrode of M6, and the drain electrode of M7 is connected with the drain electrode of M17, and the grid of M7 receives benchmark output terminal; The drain electrode of M8 connects power supply, the grid of M8 is connected with the drain electrode of M7, the drain electrode of M9 is connected with the source electrode of M8, the grid of M9 receives the grid of described M4, the grid of M10 is connected with the drain electrode of M9, the source electrode of M9 and the drain electrode ground connection of M10, the source electrode of M10 is connected with the drain electrode of M18, and is connected to voltage-reference output terminal V_REF。

In described output voltage reference source circuit unit, all MOS pipe is all be operated in sub-threshold region.

Connection relation according to M5, M6 and M7, it is possible to obtain

$\begin{array}{c}{V}_{REF}=V_{GS7}+V_{GS6}-V_{GS5}=V_{TH7}^{*}+{\mathrm{\ηV}}_T\ln \frac{I}{{\mathrm{\μC}}_{ox}(\mathrm{\η}-1)K_7{V}_T^2}+V_{TH6}\\ +{\mathrm{\ηV}}_T\ln \frac{I+\mathrm{\β}I}{{\mathrm{\μC}}_{ox}(\mathrm{\η}-1)K_6{V}_T^2}-V_{TH5}^{*}-{\mathrm{\ηV}}_T\ln \frac{\mathrm{\β}I}{{\mathrm{\μC}}_{ox}(\mathrm{\η}-1)K_5{V}_T^2},\end{array}---\left(11\right)$

Owing to the source lining voltage VSB of M5 and M7 is equal, so V*TH7=V*TH5, wushu (4) (10) substitute into formula (11), and abbreviation obtains

$V_{REF}=V_{TH}\left(T_0\right)-\mathrm{\κ}(T-T_0)+{\mathrm{\ηV}}_{T}ln\[\frac{1}{2}{\left({\mathrm{\η}}^2\frac{\sqrt{K_1{K}_2}}{\sqrt{K_1}-\sqrt{K_2}}ln\frac{K_4}{K_3}\right)}^2\frac{(1+\mathrm{\β})K_5}{\mathrm{\β}(\mathrm{\η}-1)K_6{K}_7}\]---\left(12\right)$

OrderThe condition obtaining zero-temperature coefficient output is

$\frac{1}{2}{\left({\mathrm{\η}}^2\frac{\sqrt{K_1{K}_2}}{\sqrt{K_1}-\sqrt{K_2}}ln\frac{K_4}{K_3}\right)}^2\frac{(1+\mathrm{\β})K_5}{\mathrm{\β}(\mathrm{\η}-1)K_6{K}_7}=\exp \frac{\mathrm{\κ}q}{{\mathrm{\ηk}}_B}---\left(13\right)$

The size of the relevant MOS pipe of adjustment makes equation set up, it is possible to the votage reference realizing zero-temperature coefficient exports.

M8, M9, M10 and M18 introduce reverse feedback so that the output resistance of VREF end reduces greatly, utilize small-signal analytical procedure, it is possible to the output resistance obtaining VREF end is

$\begin{array}{c}{r}_{out}=\frac{v_{out}}{i_{ds10}}=\frac{v_{out}}{v_{out}{g}_{m7}{r}_{OX}{g}_{m10}{g}_{m8}/(g_{m8}+g_{mb8})}\\ =\frac{1}{g_{m7}{r}_{OX}{g}_{m10}{g}_{m8}/(g_{m8}+g_{mb8})}\end{array}---\left(14\right)$

Small-signal model analysis according to power supply rejection ratio, small-signal resistance from VREF to power supply is more big, and the small-signal resistance from VREF to ground is more little, then the power supply rejection ratio that a reference source exports is more high, so the introducing of feedback loop substantially increases the power supply rejection ratio that a reference source exports.

The present invention provides a kind of super low-power consumption high PSRR voltage reference source circuit, comprises the startup circuit unit, current generating circuit unit and the output voltage reference circuit unit that are electrically connected in turn; Described startup circuit unit, for providing trigger voltage, avoids voltage reference source circuit to be operated in zero condition district; Described current generating circuit unit is used for making the lower power consumption of voltage reference source circuit for output voltage reference circuit unit produces working current simultaneously; Described output voltage reference circuit unit exports for realizing the voltage benchmark of zero-temperature coefficient and high PSRR. The present invention has the little advantage of super low-power consumption, low-temperature coefficient, high PSRR, wider operating voltage scope and area.

The parts that same or similar label is corresponding same or similar;

The term describing position relation in accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent;

Obviously, the above embodiment of the present invention is only for example of the present invention is clearly described, and is not the restriction to embodiments of the present invention. For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description. Here without the need to also cannot all enforcement modes be given exhaustive. All any amendment, equivalent replacement and improvement etc. done within the spirit and principles in the present invention, all should be included within the protection domain of the claims in the present invention.

Claims (7)

1. a super low-power consumption high PSRR voltage reference source circuit, it is characterised in that, comprise the startup circuit unit, current generating circuit unit and the output voltage reference circuit unit that are electrically connected in turn;

Described startup circuit unit, for providing trigger voltage, avoids voltage reference source circuit to be operated in zero condition district;

Described current generating circuit unit is used for making the lower power consumption of voltage reference source circuit for output voltage reference circuit unit produces working current simultaneously;

Described output voltage reference circuit unit exports for realizing the voltage benchmark of zero-temperature coefficient and high PSRR.

2. super low-power consumption high PSRR voltage reference source circuit according to claim 1, it is characterized in that, described startup circuit unit comprises NMOS tube MS1, MS2, and PMOS MC, drain electrode and the source electrode of MC are all connected with power supply, the grid of MC is connected with the grid of MS2, the drain electrode of MS2 and source electrode draw the first initiating signal output terminal and the 2nd initiating signal output terminal respectively, initiating signal is provided to current generating circuit unit, the drain electrode of MS1 is connected with the grid of MS2, the source ground of MS1, the grid of MS1 is connected to voltage-reference output terminal V_REF。

3. super low-power consumption high PSRR voltage reference source circuit according to claim 2, it is characterised in that, described current generating circuit unit comprises NMOS tube M1, M2, M3, M4, M11, M12 and PMOS M13, M14, M15;Described M13, M14 and M15 connect with current-mirror structure, namely M13 grid is connected with drain electrode, the grid of M13, M14 and M15 connects and draws generation current output terminal, and the first initiating signal output terminal with described startup circuit unit is connected, and the source electrode of M13, M14 and M15 connects power supply; M3 and M4 is connected into diode respectively, namely the respective grid of M3 with M4 is connected with drain electrode, the source ground of M3 and M4, the source electrode of M1 and the drain electrode of M3 connect, the drain electrode of M1 connects with the drain electrode of M14, and the source electrode of M2 and the drain electrode of M4 connect, and the drain electrode of M2 connects with the drain electrode of M15, the drain and gate of M2 is all connected with the grid of M1, and the 2nd initiating signal output terminal with described startup circuit unit is connected; The grid of M12 is connected with the drain electrode of M1, and the drain electrode of M12 connects with the drain electrode of M13, and the drain electrode of M11 connects with the source electrode of M12, and the grid of M11 receives drain electrode, connects into diode, the source ground of M11.

4. super low-power consumption high PSRR voltage reference source circuit according to claim 3, it is characterised in that, M1, M2 in described current generating circuit unit are operated in saturation region, and M3, M4, M11, M12, M13, M14, M15 are operated in sub-threshold region.

5. super low-power consumption high PSRR voltage reference source circuit according to claim 3, it is characterised in that, described output voltage reference circuit unit comprises PMOS M10, M16, M17, M18 and NMOS tube M5, M6, M7, M8, M9; The grid of described M16, M17, M18 is connected, as the input terminus of output voltage reference circuit unit, it is connected with the generation current output terminal of described current generating circuit unit, the source electrode of M16, M17, M18 connects power supply, and the drain and gate of M5 and the grid of M6 are connected with the drain electrode of M16, and the drain electrode of M6 is connected with the source electrode of M5, the source ground of M6, the source electrode of M7 is connected with the drain electrode of M6, and the drain electrode of M7 is connected with the drain electrode of M17, and the grid of M7 receives benchmark output terminal; The drain electrode of M8 connects power supply, the grid of M8 is connected with the drain electrode of M7, the drain electrode of M9 is connected with the source electrode of M8, the grid of M9 receives the grid of described M4, the grid of M10 is connected with the drain electrode of M9, the source electrode of M9 and the drain electrode ground connection of M10, the source electrode of M10 is connected with the drain electrode of M18, and is connected to voltage-reference output terminal V_REF。

6. super low-power consumption high PSRR voltage reference source circuit according to claim 5, it is characterised in that, in described output voltage reference source circuit unit, all MOS pipe is all be operated in sub-threshold region.

7. super low-power consumption high PSRR voltage reference source circuit according to the arbitrary item of claim 1-6, it is characterised in that, the voltage of described power supply is 1.8V.