CN104460799A - CMOS reference voltage source circuit - Google Patents

Abstract

The invention discloses a CMOS reference voltage source circuit. The CMOS reference voltage source circuit comprises a start circuit, a first bias current generation circuit, a second bias current generation circuit and a reference voltage generation circuit, wherein the start circuit provides the start voltage after being connected with a direct-current power supply, the first bias current generation circuit is used for receiving the start voltage provided by the start circuit to produce the first bias current and providing the output voltage, the temperature coefficient direction of the first bias current serves as the first direction, the second bias current generation circuit is used for receiving the output voltage provided by the first bias current generation circuit as the input and generating the second bias current, the temperature coefficient direction of the second bias current serves as the second direction, and the reference voltage generation circuit is used for receiving the first bias current and the second bias current as the input and obtaining the reference voltage by adjusting the first bias current and the second bias current. By means of the CMOS reference voltage source circuit, the reliability and flexibility of the reference voltage source circuit are improved.

Description

CMOS reference voltage source circuit

Technical field

The present invention relates to CMOS transistor circuit engineering field, particularly relate to CMOS reference voltage source circuit.

Background technology

In simulation, numerical model analysis, and often can use reference voltage source in digital circuit, its stability is directly connected to the performance of whole circuit.General conventional reference voltage source adopts BiCMOS technique, as a kind of traditional bandgap reference voltage source circuit that Fig. 1 provides, comprises triode transistor Q ₁and Q ₂, error amplifier OP, feedback resistance R ₁and R ₂, adjusting resistance R ₃; Transistor Q ₁and Q ₂emitter analogue ground AVSS, amplifier two input ends are connected node A and B respectively, and output terminal exports V _rEF, contact resistance R simultaneously ₁and R ₂.Amplifier operation is in profound and negative feedbck, and two input end connected node A and B respectively, make two point voltages equal, connect the identical resistance R of two resistances simultaneously ₁and R ₂, make to flow through Q ₁and Q ₂two-way electric current equal, thus to obtain:

V _BE1-V _BE2＝I ₂R ₃＝V _TlnN (1)

And then obtain output voltage VO UT:

$V_{\mathrm{REF}}=V_{\mathrm{BE}2}+\left(V_T\ln N\right)(1+\frac{R_2}{R_3})---\left(2\right)$

There is following two problems in this circuit, first, and usual V _rEFfor about 1.25V, can not be applied in low-voltage circuit; Secondly, the method needs to use transistor and metal-oxide-semiconductor jointly to realize, and proposes requirement to technique.

Fig. 2 gives a kind of improved plan, M in band-gap circuit ₁, M ₂and M ₃composition current mirror, amplifier OP ₁be in .0 profound and negative feedbck state, making AB two point voltage equal, is V _bE, namely flow through R ₂electric current be V _bE/ R ₂, there is negative temperature coefficient, and by resistance R ₁electric current be the electric current with VT direct proportionality, two-way electric current sum flows through M ₂, be copied to I ₃, then resistance R3 both end voltage is:

$V_{\mathrm{REF}}=\frac{R_3}{R_2}{V}_{\mathrm{BE}}+\frac{R_3}{R_1}{V}_T\ln N---\left(3\right)$

Suitably choose N, R ₁, R ₂and R ₃the output voltage V of zero-temperature coefficient can be obtained _rEF, and the temperature coefficient of output voltage and R ₃independent mutually, the bandgap voltage reference namely exported can regulate.But this circuit is same with technology one employs transistor, need to use BiCMOS technique, this reference circuit cannot be used under CMOS technology.

Fig. 3 gives a kind of band-gap reference circuit of CMOS technology, M in this band-gap circuit ₁and M ₃be operated in sub-threshold region, namely flow through M ₁and M ₃electric current be respectively

$I_1=I_0\frac{W_1}{L_1}{e}^{\frac{V_{\mathrm{GS}1}}{{\mathrm{\δV}}_T}}---\left(4\right)$

$I_2=I_0\frac{W_2}{L_2}{e}^{\frac{V_{\mathrm{GS}2}}{{\mathrm{\δV}}_T}}---\left(5\right)$

M ₂and M ₄pipe connects into current mirror form, and breadth length ratio is equal, namely

I ₁＝I ₂(6)

Warp (4), (5), (6) obtain

$V_{\mathrm{GS}1}-V_{\mathrm{GS}2}={\mathrm{\δV}}_T\ln \left(\frac{W_2{L}_1}{W_1{L}_2}\right)---\left(7\right)$

Knownly flow through resistance R ₁electric current be

$I_2=\frac{V_{\mathrm{GS}1}-V_{\mathrm{GS}2}}{R_1}=\frac{{\mathrm{\δV}}_T\ln \left(\frac{W_2{L}_1}{W_1{L}_2}\right)}{R_1}---\left(8\right)$

I ₂temperature coefficient and V _tproportional, i.e. I ₂for positive temperature coefficient (PTC) electric current.

M ₆pipe and M ₄pipe forms current mirror, is M ₅there is provided stable drain-source current, M ₇the clamped M of gate source voltage of pipe ₅drain-gate voltage, make M ₅steady operation is in sub-threshold region.Flow through resistance R ₂electric current I ₄for

$I_4=\frac{V_{\mathrm{GS}5}}{R_2}---\left(9\right)$

The gate source voltage of sub-threshold region metal-oxide-semiconductor has negative temperature coefficient, i.e. electric current I ₄for negative temperature parameter current.M ₉and M ₄, M ₁₀and M ₈form current mirror respectively, i.e. I ₅, I ₆copy positive temperature coefficient (PTC) electric current and negative temperature parameter current respectively, superposition and resistance R ₃, form the output voltage V of zero-temperature coefficient _rEF.

The shortcoming of this circuit is M ₁, M ₃all be operated in sub-threshold region, gate source voltage is less, but R ₁need to get a part of pressure drop, so M ₁, M ₃gate source voltage have significant difference.By process deviation influence, M in side circuit ₁gate source voltage likely exceed threshold voltage, cannot ensure to be operated in sub-threshold region, produce estimate positive temperature coefficient (PTC) electric current, therefore reliability is poor.

In order to improve the processing compatibility of the band-gap reference circuit shown in Fig. 1,2, cmos circuit structure must be adopted.In addition, in order to improve the dirigibility of the output voltage of reference circuit shown in Fig. 1, improve the stability of reference circuit shown in Fig. 3 simultaneously, then need to adopt new circuit structure.

Summary of the invention

For the problems referred to above, the object of the invention is to design and be suitable for realizing in CMOS technology, the reference voltage source circuit of high reliability and dirigibility.

The present invention adopts following technical scheme: a kind of CMOS reference voltage source circuit, comprising: start-up circuit, and it, after connection direct supply, provides trigger voltage; First bias current generating circuit, for receiving the trigger voltage that start-up circuit provides, producing the first bias current, and providing output voltage, and the temperature coefficient direction of the first bias current is first direction; Second bias current generating circuit, for receiving output voltage that the first bias current generating circuit provides as input, produce the second bias current, the temperature coefficient direction of the second bias current is second direction; Reference voltage generating circuit, for receiving the first bias current and the second bias current as input, obtains reference voltage by adjusting first, second bias current.

The present invention adopts standard CMOS process to realize, and circuit structure does not need triode transistor; Adopt mode electric currents different for two-way temperature characterisitic being superimposed on same resistance, using the reference voltage that the voltage at resistance two ends goes to zero as temperature coefficient, therefore reference voltage value can flexible, to be applicable to different circuit requirements simultaneously; In addition, the MOS device being operated in sub-threshold region of employing, add coupling and negative feedback design, therefore this circuit structure is not subject to the impact of process deviation and voltage dithering, ensure that the reliability of whole reference voltage source circuit.The circuit realizing this bandgap voltage reference produces the contrary electric current of two-way temperature coefficient variation tendency, and two-way electric current is superimposed on same resistance, suitably regulates the ratio of two-way electric current, and being formed can the bandgap voltage reference of flexible.

CMOS reference voltage source of the present invention, has obvious advantage and positive effect, and due to reference voltage source circuit conventional at present in a lot.

(1) do not contain triode in circuit of the present invention, only comprise NMOS tube, PMOS, resistance three kinds of devices, therefore, have the simple advantage of technique, it is convenient, effective, compatible good that CMOS technology line realizes;

(2) the present invention adopts new sub-threshold region CMOS reference circuit structure, add the structural parameters of the metal-oxide-semiconductor being operated in sub-threshold region and the coupling of duty, compared to traditional reference circuit containing sub-threshold region device, reduce the impact that process deviation normally realizes circuit function, improve the stability of sub-threshold region devices function in circuit, ensure that the reliability of CMOS reference voltage source;

(3) the present invention adopts mode electric currents different for two-way temperature characterisitic being superimposed on same resistance, using the reference voltage that the voltage at resistance two ends goes to zero as temperature coefficient, therefore reference voltage value can flexible, to be applicable to different circuit requirements.

Accompanying drawing explanation

By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious, and in accompanying drawing, same or analogous Reference numeral represents same or analogous parts.

Figure 1 shows that prior art 1, for adopting BiCMOS technique band gap reference voltage source circuit;

Figure 2 shows that prior art 2, for adopting BiCMOS technique band gap reference voltage source circuit;

Figure 3 shows that prior art 3, is a kind of sub-threshold region CMOS reference voltage source circuit;

Figure 4 shows that CMOS reference voltage source circuit modular structure schematic diagram of the present invention;

Figure 5 shows that CMOS reference voltage source circuit figure of the present invention.

Embodiment

Below by way of specific embodiments of the invention also by reference to the accompanying drawings, object of the present invention, circuit structure and advantage are further described.

Fig. 4 is CMOS reference voltage source circuit modular structure schematic diagram, and this circuit comprises start-up circuit 101, the first bias current generating circuit 102, first bias current generating circuit 103, reference voltage generating circuit 104, start-up circuit 101, first bias current generating circuit 102, first bias current generating circuit 103, the direct current input end of reference voltage generating circuit 104 connects direct supply VDD respectively, the input end of the first bias current generating circuit 102 connects the output terminal of start-up circuit 101, the output terminal of the first bias current generating circuit 102 is connected to the first input end of reference voltage generating circuit 104 and the input end of the first bias current generating circuit 103, the output terminal of the first bias current generating circuit 103 is connected to the second input end of reference voltage generating circuit 104, the reference voltage output end output reference voltage of reference voltage generating circuit 104.

Fig. 5 is CMOS reference voltage source circuit figure.Start-up circuit 101 is by PMOS M _s1, M _s2with NMOS tube M _s3composition, PMOS M _s1source electrode, PMOS M _s2source electrode and NMOS tube M _s3grid as the direct current input end of start-up circuit 101, PMOS M _s1drain electrode respectively with PMOS M _s2grid and NMOS tube M _s3drain electrode be connected, NMOS tube M _s3source electrode connect common, PMOS M _s1grid and PMOS M _s2drain electrode respectively as first, second output terminal of start-up circuit 101;

First bias current generating circuit 102 is by 4 PMOS M ₃, M ₄, M ₅and M ₆, 2 NMOS tube M ₇and M ₈and 2 resistance R ₁and R ₂composition, PMOS M ₁and M ₃source electrode as direct current input end, the first output terminal of start-up circuit 101 and PMOS M ₁and M ₃grid, and M ₃drain electrode connect altogether, and as the first output terminal of the first bias current generating circuit 102 and the first input end of the first bias current generating circuit 103, and the first input end of reference voltage generating circuit 104 is connected, PMOS M ₁drain electrode and PMOS M ₂source electrode be connected, PMOS M ₃drain electrode and PMOS M ₄source electrode be connected, PMOS M ₂grid and PMOS M ₄grid and drain electrode connect altogether, and as the second output terminal of the first bias current generating circuit 102 and the second input end of the first bias current generating circuit 103, and the second input end of reference voltage generating circuit 104 be connected, start-up circuit 101 second output terminal respectively with PMOS M ₂drain electrode, NMOS tube M ₅drain and gate, and NMOS tube M ₆grid connects altogether, PMOS M ₄drain electrode and NMOS tube M ₆drain electrode be connected, NMOS tube M ₅source electrode and resistance R ₁be connected, resistance R ₁another termination common, NMOS tube M ₆source electrode and resistance R ₂be connected, resistance R ₂another termination common.

First bias current generating circuit 103 is by 6 PMOS M ₇, M ₈, M ₁₁, M ₁₂, M ₁₃and M ₁₄, 2 NMOS tube M ₉and M ₁₀and a resistance R ₃composition, PMOS M ₇, PMOS ₁₃with PMOS M ₁₁source electrode as direct current input end, the first output terminal of the first bias current generating circuit 102 and PMOS M ₇grid be connected, PMOS M ₇drain electrode and PMOS M ₈source electrode be connected, PMOS M ₈grid be connected with the second output terminal of the first bias current generating circuit 102, PMOS M ₈drain electrode and NMOS tube M ₉drain electrode and NMOS tube M ₁₀grid connect altogether, NMOS tube M ₉source electrode connect common, PMOS M ₁₃grid and drain electrode, and PMOS M ₁₁grid connect altogether, and to be connected with the first input end of reference voltage generating circuit 104 as the first output terminal of the first bias current generating circuit 103, PMOS M ₁₃drain electrode and PMOS M ₁₄source electrode be connected, PMOS M ₁₁drain electrode and PMOS M ₁₂source electrode be connected, PMOS M ₁₄grid and drain electrode, and PMOS M ₁₂grid connect altogether, and to be connected with the second input end of reference voltage generating circuit 104 as the second output terminal of the first bias current generating circuit 103, PMOS M ₁₄drain electrode and NMOS tube M ₁₀drain electrode be connected, NMOS tube M ₁₀source electrode connect common, PMOS M ₁₂drain electrode and NMOS tube M ₉grid and resistance R ₃connect altogether, resistance R ₃another termination common.

Reference voltage generating circuit 104 is by 4 PMOS M ₁₅, M ₁₆, M ₁₇and M ₁₈, a resistance R ₄composition, PMOS M ₁₅source electrode and PMOS M ₁₇source electrode as direct current input end, PMOS M ₁₅grid be connected with the first output terminal of the first bias current generating circuit 102, PMOS M ₁₇grid be connected with the first output terminal of the first bias current generating circuit 103, PMOS M ₁₅drain electrode and PMOS M ₁₆source electrode be connected, PMOS M ₁₇drain electrode and PMOS M ₁₈source electrode be connected, PMOS M ₁₆grid be connected with the second output terminal of the first bias current generating circuit 102, PMOS M ₁₈grid be connected with the second output terminal of the first bias current generating circuit 103, PMOS M ₁₆drain electrode and PMOS M ₁₈drain electrode be connected to resistance R altogether ₄, and as reference voltage output end, resistance R ₄another termination common.

The course of work of circuit of the present invention: as connection direct current power source voltage V _dDtime, NMOS tube M _s3open, by PMOS M _s2grid voltage be pulled down to close to common voltage, M _s2pipe is opened, and for start-up circuit 101 second output terminal provides enough voltage, is PMOS M ₅and M ₆gate charges, ensure metal-oxide-semiconductor open, circuit working depart from off state.

PMOS M in first bias current generating circuit 102 ₁, M ₂, M ₃and M ₄for common-source common-gate current mirror, wherein M ₁, M ₃and M ₂, M ₄breadth length ratio equal, make I ₁=I ₂, resistance R simultaneously ₁=R ₂, make NMOS tube M ₅and M ₆gate source voltage equal, M ₅and M ₆be operated in sub-threshold region, and duty is similar to identical, namely

$I_1=I_0\frac{W_5}{L_5}{e}^{\frac{V_{\mathrm{GS}5}}{{\mathrm{\δV}}_T}}---\left(10\right)$

Wherein NMOS tube M ₅source voltage V _gS5=I ₁r ₁, (10) are obtained with Taylor function approximate expansion

$I_1=I_0\frac{W_5}{L_5}(1+\frac{V_{G5}-I_1{R}_1}{{\mathrm{\δV}}_T})---\left(11\right)$

Thus obtain I ₁expression formula

$I_1=I_0\frac{W_5}{L_5}\left(\frac{{\mathrm{\δV}}_T+V_{G5}}{{\mathrm{\δV}}_T+I_0\frac{W_1}{L_1}{R}_1}\right)---\left(12\right)$

Known wherein relevant with temperature variable is V _tand V _g5.PMOS M ₁, M ₂, M ₃and M ₄be operated in saturation region, its source gate voltage has positive temperature coefficient (PTC) character, V when temperature raises _sGincrease, saturation depth increases, V _sD1, V _sD2reduce, therefore V _g5increase; Know V again _tfor positive temperature coefficient (PTC) parameter, therefore I ₁raise with temperature and increase.Through the emulation of 0.18um 3.3v SOI CMOS technology,--in 50-150 degree temperature ranges, electric current I ₁temperature curve be approximately first order linear curve.

In the first bias current generating circuit 103, PMOS M ₇and M ₈form current mirror and copy I ₂, be NMOS tube M ₉bias current is provided; Resistance R simultaneously ₃two sections meet M respectively ₉grid and source electrode, therefore flow through R ₃electric current be

$I_4=\frac{V_{\mathrm{GS}9}}{R_3}---\left(13\right)$

M ₉be operated in sub-threshold region, V _gS9there is negative temperature coefficient, therefore I ₄for negative temperature parameter current.Wherein M ₉, M ₁₀, M ₁₁, M ₁₂, M ₁₃, M ₁₄and R ₃for negative feedback connects, feedback regulation M ₉gate source voltage keep steady state (SS), do not change with the shake of voltage or electric current.

In reference voltage generating circuit, Positive and Negative Coefficient Temperature electric current superposes; PMOS M ₁₅and M ₁₆copy positive temperature coefficient (PTC) electric current I ₁, PMOS M ₁₇and M ₁₈copy negative temperature parameter current I ₄, two-way replica current I ₆and I ₇jointly flow through resistance R ₄, obtain reference voltage V _rEF, namely

V _REF＝(I ₆+I ₇)R ₄＝(AI ₁+BI ₄)R ₄(14)

$V_{\mathrm{REF}}=[{\mathrm{AI}}_0\frac{W_5}{L_5}\left(\frac{{\mathrm{\δV}}_T+V_{G5}}{{\mathrm{\δV}}_T+I_0\frac{W_1}{L_1}{R}_1}\right)+B\frac{V_{\mathrm{GS}9}}{R_3}]R_4---\left(15\right)$

Can find out, by suitable adjustment factor A, B, the i.e. ratio of Positive and Negative Coefficient Temperature electric current, the reference voltage of zero-temperature coefficient can be produced.Meanwhile, by regulating R ₄resistance, can the value of flexible reference voltage, be applicable to different circuit requirements.

In this circuit design, two-way current generating circuit is negative feedback structure, stability under working conditions is good, and the duty being in the metal-oxide-semiconductor of sub-threshold region is consistent, the impact of process deviation on it can be reduced, in addition, this circuit can be compatible with CMOS technology completely, and the reference voltage that circuit exports can according to different demand, by regulating R ₄resistance carry out flexible.

Claims (9)

1. a CMOS reference voltage source circuit, is characterized in that, comprising:

Start-up circuit, it, after connection direct supply, provides trigger voltage;

First bias current generating circuit, for receiving the trigger voltage that start-up circuit provides, producing the first bias current, and providing output voltage, and the temperature coefficient direction of the first bias current is first direction;

Second bias current generating circuit, for receiving output voltage that the first bias current generating circuit provides as input, produce the second bias current, the temperature coefficient direction of the second bias current is second direction;

Reference voltage generating circuit, for receiving the first bias current and the second bias current as input, obtains reference voltage by adjusting first, second bias current.

2. CMOS reference voltage source circuit according to claim 1, wherein said start-up circuit comprises: the first PMOS (M _s2) and the first NMOS tube (M _s3); First PMOS (M _s2) source electrode and the first NMOS tube (M _s3) grid be connected to the direct current input end (V of start-up circuit _dD), the first PMOS (M _s2) grid be connected to the first NMOS tube (M _s3) drain electrode, the first NMOS tube (M _s3) source ground, the first PMOS (M _s2) drain electrode be connected to the first input end of described first bias current generating circuit as the first output terminal of start-up circuit.

3. CMOS reference voltage source circuit according to claim 2, wherein said start-up circuit also comprises: the second PMOS (M _s1); Second PMOS (M _s1) source electrode be connected to direct current input end (V _dD), the second PMOS (M _s1) drain electrode and described first PMOS (M _s2) grid and described first NMOS tube (M _s3) drain electrode connect altogether, the second PMOS (M _s1) grid be connected to the second input end of described first bias current generating circuit as the second output terminal of start-up circuit.

4. CMOS reference voltage source circuit according to claim 3, wherein said first bias current generating circuit comprises: the second NMOS tube (M ₅), the 3rd NMOS tube (M ₆), the first resistance (R ₁) and the second resistance (R ₂); Second NMOS tube (M ₅) grid and drain electrode with the 3rd NMOS tube (M ₆) grid to connect altogether and first input end as the first biasing circuit is connected with described start-up circuit, the second NMOS tube (M ₅) source electrode and the first resistance (R ₁) one end be connected, the first resistance (R ₁) other end ground connection, the 3rd NMOS tube (M ₆) source electrode and the second resistance (R ₂) one end be connected, the second resistance (R ₂) other end ground connection.

5. CMOS reference voltage source circuit according to claim 4, wherein said first bias current generating circuit also comprises the first common-source common-gate current mirror circuit, for by the second NMOS tube (M ₅) and the 3rd NMOS tube (M ₆) be biased in sub-threshold region, and ensure to flow through the first resistance (R ₁) electric current equal to flow through the second resistance (R ₂) electric current; First common-source common-gate current mirror circuit comprises the 3rd PMOS (M ₁), the 4th PMOS (M ₂), the 5th PMOS (M ₃) and the 6th PMOS (M ₄); 3rd PMOS (M ₁) source electrode and the 5th PMOS (M ₃) source electrode be connected to direct current input end (V _dD), the 3rd PMOS (M ₁) grid, the 5th PMOS (M ₃) grid, start-up circuit the second output terminal connect altogether, and as the second output terminal of the first bias current generating circuit, the 3rd PMOS (M ₁) drain electrode be connected to the 4th PMOS (M ₂) source electrode, the 5th PMOS (M ₃) drain electrode be connected to the 6th PMOS (M ₄) source electrode, and with the 5th PMOS (M ₃) grid connect altogether, the 4th PMOS (M ₂) grid and the 6th PMOS (M ₄) grid to connect altogether and as the first output terminal of the first bias current generating circuit, the 4th PMOS (M ₂) drain electrode be connected to described second NMOS tube (M ₅) drain electrode, the 6th PMOS (M ₄) drain electrode be connected to described 3rd NMOS tube (M ₆) drain electrode.

6. CMOS reference voltage source circuit according to claim 5, wherein said second bias current generating circuit comprises the current mirroring circuit for copying the first bias current, and this current mirroring circuit comprises the 7th PMOS (M ₇), the 8th PMOS (M ₈) and the 4th NMOS tube (M ₉); 7th PMOS (M ₇) source electrode meet direct current input end (V _dD), the 7th PMOS (M ₇) drain electrode and the 8th PMOS (M ₈) source electrode connect, the 8th PMOS (M ₈) drain electrode and the 4th NMOS tube (M ₉) drain electrode connect, the 4th NMOS tube (M ₉) source electrode connect common, the 7th PMOS (M ₇) grid be connected with the second output terminal of the first bias current generating circuit as the second input end of the second bias current generating circuit, the 8th PMOS (M ₈) grid be connected with the first output terminal of the first bias current generating circuit as the first input end of the second bias current generating circuit.

7. CMOS reference voltage source circuit according to claim 6, wherein said second bias current generating circuit also comprises: the 5th NMOS tube (M ₁₀), the 9th PMOS (M ₁₁), the tenth PMOS (M ₁₂), the 11 PMOS (M ₁₃), the 12 PMOS (M ₁₄) and the 3rd resistance (R ₃); Wherein the 9th PMOS (M ₁₁), the tenth PMOS (M ₁₂), the 11 PMOS (M ₁₃) and the 12 PMOS (M ₁₄) for the formation of the second common-source common-gate current mirror circuit, ensure through the 3rd resistance (R ₃) and the 5th NMOS tube (M ₁₀) electric current equal; 9th PMOS (M ₁₁) source electrode and the 11 PMOS (M ₁₃) source electrode be connected to direct current input end (V _dD), the 9th PMOS (M ₁₁) grid and the 11 PMOS (M ₁₃) grid and drain electrode connect altogether, and as the second output terminal of the second bias current, the 9th PMOS (M ₁₁) drain electrode be connected to the tenth PMOS (M ₁₂) source electrode, the 11 PMOS (M ₁₃) drain electrode be connected to the 12 PMOS (M ₁₄) source electrode, the tenth PMOS (M ₁₂) grid and the 12 PMOS (M ₁₄) grid and drain electrode connect altogether, and as the first output terminal of the second bias current generating circuit, the 12 PMOS (M ₁₄) drain electrode be connected to the 5th NMOS tube (M ₁₀) drain electrode, the 5th NMOS tube (M ₁₀) source ground, the 5th NMOS tube (M ₁₀) grid and described 4th NMOS tube (M ₉) drain electrode be connected, the tenth PMOS (M ₁₂) drain electrode and described 4th NMOS tube (M ₉) grid connect altogether, and be connected to the 3rd resistance (R ₃) one end, the 3rd resistance (R ₃) other end ground connection.

8. CMOS reference voltage source circuit according to claim 7, described reference voltage generating circuit comprises the 13 PMOS (M ₁₅), the 14 PMOS (M ₁₆), the 15 PMOS (M ₁₇), the 16 PMOS (M ₁₈) and the 4th resistance (R ₄); 13 PMOS (M ₁₅) and the 14 PMOS (M ₁₆) circuit that formed is used for copying the first bias current, the 15 PMOS (M ₁₇) and the 16 PMOS (M ₁₈) circuit that formed is used for copying the second bias current; 13 PMOS (M ₁₅) source electrode and the 15 PMOS (M ₁₇) source electrode be connected to direct current input end (V _dD), the 13 PMOS (M ₁₅) grid be connected to the second output terminal of the first bias current generating circuit, the 15 PMOS (M ₁₇) grid be connected to the second output terminal of the second bias current generating circuit, the 13 PMOS (M ₁₅) drain electrode be connected to the 14 PMOS (M ₁₆) source electrode, the 15 PMOS (M ₁₇) drain electrode be connected to the 16 PMOS (M ₁₈) source electrode, the 14 PMOS (M ₁₆) grid be connected to the first output terminal of the first bias current generating circuit, the 16 PMOS (M ₁₈) grid be connected to the first output terminal of the second bias current generating circuit, the 14 PMOS (M ₁₆) drain electrode and the 16 PMOS (M ₁₈) drain electrode and the 4th resistance (R ₄) one end connect altogether, and as reference voltage output end (VREF), the 4th resistance (R ₄) the other end be connected to common.

9. CMOS reference voltage source circuit according to claim 1, wherein said first direction is just, described second direction is negative.