CN103809644A - Novel low-power-consumption resistor-free type reference voltage generation circuit - Google Patents
Novel low-power-consumption resistor-free type reference voltage generation circuit Download PDFInfo
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- CN103809644A CN103809644A CN201410074785.7A CN201410074785A CN103809644A CN 103809644 A CN103809644 A CN 103809644A CN 201410074785 A CN201410074785 A CN 201410074785A CN 103809644 A CN103809644 A CN 103809644A
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Abstract
The invention relates to a novel low-power-consumption resistor-free type reference voltage generation circuit. The novel low-power-consumption resistor-free type reference voltage generation circuit comprises a starting unit. The starting unit is connected to a summation unit through a positive temperature coefficient voltage generation unit and a negative temperature coefficient voltage generation unit. The starting unit, the positive temperature coefficient voltage generation unit, the negative temperature coefficient voltage generation unit and the summation unit are all connected with a VDD and a GND. The positive temperature coefficient voltage generation unit outputs positive temperature coefficient voltages to the summation unit. The negative temperature coefficient voltage generation unit outputs negative temperature coefficient voltages to the summation unit. The summation unit sums the positive temperature coefficient voltages and the negative temperature coefficient voltages and outputs reference voltages. The positive temperature coefficient voltage generation unit further provides bias currents for the negative temperature coefficient voltage generation unit. The starting unit provides the starting function for the whole circuit. The novel low-power-consumption resistor-free type reference voltage generation circuit is simple in design, small in area and low in power consumption, temperature coefficients of the reference voltages are reduced, and the output voltage power supply rejection ratio is increased.
Description
Technical field
The present invention relates to the reference voltage generating circuit of a kind of low-power consumption, low-temperature coefficient, high PSRR, non-resistance.
Background technology
Traditional benchmark voltage source is as one of circuit unit important in IC design; it has been widely used in various Analogous Integrated Electronic Circuits, digital integrated circuit and hybrid digital-analog integrated circuit, as systems such as A/D, D/A converter, LDO voltage stabilizer and phaselocked loops (PLL).Along with developing rapidly of semiconductor industry, now reference voltage source is had to higher requirement, require it to there is the features such as low in energy consumption, temperature coefficient is little, Power Supply Rejection Ratio is high, output noise is little, area is little.
Traditional reference voltage source is generally the technology that adopts " band gap ", utilize exactly the base-emitter voltage of bipolar tube to there is negative temperature characteristic, and two bipolar transistors are operated under different current densities, its base-emitter voltage difference has positive temperature characterisitic, both are compensated mutually, thereby realize zero-temperature coefficient.But there is following problem in this method:
1. need to introduce amplifier, this just introduces the problem that amplifier stability is brought circuit, and for circuit can normally be worked, supply voltage is generally larger, also brings the problem that power consumption is higher;
2. circuit needs triode, therefore generally needs larger area;
3. circuit needs resistance, and the resistance of resistance is subject to the impact of temperature, and therefore the introducing of resistance not only brings the tradeoff of power consumption and area, and can cause output reference voltage to produce deviation;
4. sometimes in order to reach better performance, circuit has to introduce high-order compensation technology, on the one hand makes circuit design more complicated, on the other hand also the power consumption of increasing circuit and area.
A lot of non-" band gap " technology has also been proposed in recent years, this technology generally does not need to introduce amplifier, also without adopting triode, it is much the technology that adopts threshold voltage vt h and thermal voltage VT mutually to compensate, but adopt a lot of circuit of this technology still to need to introduce resistance, circuit design is also comparatively complicated simultaneously, finally cannot reach the performance such as low-power consumption and small size; Also have and adopt the gate source voltage VGS of NMOSFET and the technology that thermal voltage VT compensates mutually, but adopt this technology also to be often difficult to reach the performances such as low-temperature coefficient.
Therefore, these factors have just limited the performance of reference voltage source, have much room for improvement.
Summary of the invention
The object of the present invention is to provide a kind of in-problem novel low-power consumption non-resistance type reference voltage generating circuit of said reference potential circuit that solves.
For achieving the above object, technical scheme of the present invention is: a kind of novel low-power consumption non-resistance type reference voltage generating circuit, comprise a start unit, described start unit is connected to sum unit through positive temperature coefficient (PTC) voltage generation unit and negative temperature coefficient voltage generation unit; One end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected VDD, and the other end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected GND; Described positive temperature coefficient (PTC) voltage generation unit output positive temperature coefficient (PTC) voltage is to sum unit; Described negative temperature coefficient voltage cell output negative temperature coefficient voltage is to sum unit; Described sum unit is sued for peace to positive temperature coefficient (PTC) voltage and negative temperature coefficient voltage, and output reference voltage; Described positive temperature coefficient (PTC) voltage generation unit is also for negative temperature coefficient voltage generation unit provides bias current; Described start unit provides open function for whole circuit.
In embodiments of the present invention, described positive temperature coefficient (PTC) voltage generation unit comprises the first metal-oxide-semiconductor to the 14 metal-oxide-semiconductors; The drain electrode of described the first metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor, the 6th source electrode of metal-oxide-semiconductor and the source electrode of the 13 metal-oxide-semiconductor are all connected to VDD; The source electrode of described the first metal-oxide-semiconductor is connected to the drain electrode of the second metal-oxide-semiconductor, and the source electrode of described the first metal-oxide-semiconductor is also connected to GND through the first electric capacity; The source electrode of described the second metal-oxide-semiconductor is connected with the source electrode of the 7th metal-oxide-semiconductor; The drain and gate of described the 7th metal-oxide-semiconductor is connected to the drain electrode of the tenth metal-oxide-semiconductor, the 8th grid of metal-oxide-semiconductor and the grid of the 14 metal-oxide-semiconductor; The grid of described the 5th metal-oxide-semiconductor is connected to the source electrode of the 8th metal-oxide-semiconductor with drain electrode; The drain electrode of described the 8th metal-oxide-semiconductor is connected with the drain electrode of the 11 metal-oxide-semiconductor with the grid of the 9th metal-oxide-semiconductor; The grid of described the 6th metal-oxide-semiconductor is connected to the source electrode of the 9th metal-oxide-semiconductor with drain electrode; The grid of described the 9th drain electrode of metal-oxide-semiconductor and the drain electrode of the 12 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor is connected to start unit with the grid of the tenth metal-oxide-semiconductor; The grid of described the 13 metal-oxide-semiconductor is connected to the source electrode of the 14 metal-oxide-semiconductor with drain electrode; The drain electrode of described the 14 metal-oxide-semiconductor is connected to sum unit with the drain electrode of the 3rd metal-oxide-semiconductor; The source electrode of described the 3rd metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, and is connected to GND through the second electric capacity; The source electrode of described the 4th metal-oxide-semiconductor meets GND.
In embodiments of the present invention, described reference voltage generating circuit also comprises a pulse signal generator; Described pulse signal generator comprises exports the first clock signal output terminal of the first clock signal and the second clock signal output terminal of output the second clock signal; The sequential non-overlapping copies of described the first clock signal and the second clock signal.
In embodiments of the present invention, the grid of the grid of described the first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is all connected to the first clock signal output terminal; The grid of the grid of described the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is all connected to the second clock signal output terminal.
In embodiments of the present invention, described negative temperature coefficient voltage generation unit comprises the 15 metal-oxide-semiconductor to the 17 metal-oxide-semiconductors; The source electrode of described the 15 metal-oxide-semiconductor is connected to VDD, the grid of described the 15 metal-oxide-semiconductor is connected to the grid of the 13 metal-oxide-semiconductor, and the grid of described the 15 drain electrode of metal-oxide-semiconductor and the drain electrode of the 16 metal-oxide-semiconductor, the 16 metal-oxide-semiconductor is connected with the grid of the 17 metal-oxide-semiconductor; The source electrode of described the 16 metal-oxide-semiconductor is connected to sum unit with the drain electrode of the 17 metal-oxide-semiconductor; The source electrode of described the 17 metal-oxide-semiconductor meets GND.
In embodiments of the present invention, described sum unit comprises the 18 metal-oxide-semiconductor to the 21 metal-oxide-semiconductors; Described the 18 grid of metal-oxide-semiconductor and the grid of the 21 metal-oxide-semiconductor are all connected to the second clock signal output terminal; Described the 19 grid of metal-oxide-semiconductor and the grid of the 20 metal-oxide-semiconductor are all connected to the first clock signal output terminal; The source electrode of described the 18 metal-oxide-semiconductor is connected to the source electrode of the 16 metal-oxide-semiconductor; Described the 18 drain electrode of metal-oxide-semiconductor and the source electrode of the 19 metal-oxide-semiconductor are connected to GND through the 3rd electric capacity; The drain electrode of described the 19 metal-oxide-semiconductor is connected to reference voltage output end with the drain electrode of the 20 metal-oxide-semiconductor; Described the 20 source electrode of metal-oxide-semiconductor and the source electrode of the 21 metal-oxide-semiconductor are connected to GND through the 4th electric capacity; The source electrode of described the 21 metal-oxide-semiconductor connects the drain electrode of the 14 metal-oxide-semiconductor.
In embodiments of the present invention, described start unit comprises the 22 metal-oxide-semiconductor to the 24 metal-oxide-semiconductors; Described the 22 source electrode of metal-oxide-semiconductor and the source electrode of the 23 metal-oxide-semiconductor are all connected to VDD; Described the 22 grid of metal-oxide-semiconductor and the grid of the 24 metal-oxide-semiconductor are all connected to GND; The drain electrode of described the 22 metal-oxide-semiconductor is connected with the grid of the 23 metal-oxide-semiconductor to drain electrode and the source electrode of the 24 metal-oxide-semiconductor; The drain electrode of described the 23 metal-oxide-semiconductor is connected to the grid of the tenth metal-oxide-semiconductor.
Compared to prior art, the present invention has following beneficial effect:
1. this invention is without band gap, and without triode, without amplifier, without resistance, area is little and low in energy consumption;
2. the positive temperature coefficient (PTC) voltage generation unit adopting in this invention, its circuit has negative feedback, has improved output voltage Power Supply Rejection Ratio, and this unit is also for negative temperature coefficient voltage generation unit provides bias current simultaneously;
3. the negative temperature coefficient voltage generation unit adopting in this invention, with respect to adopting the base-emitter voltage (Vbe) of bipolar transistor as negative temperature coefficient voltage, the negative temperature coefficient voltage generation unit implementation of this invention is simple, low in energy consumption and area is little;
4. the sum unit of this invention has adopted switched-capacitor circuit, does not consume DC power, and with respect to adopting the designed sum unit of resistance, the capacity ratio resistance that this invention adopts has again better matching, has reduced the temperature coefficient of reference voltage simultaneously;
5. the start-up circuit in this invention, adopts mos capacitance to replace traditional discrete capacitor, and its implementation is simple, and area is little, and does not consume power consumption after normal work;
6. the positive temperature coefficient (PTC) voltage generation unit in this invention has adopted the mode of switching capacity equivalent resistance, and its electric capacity is less, and equivalent resistance is larger, has therefore effectively reduced the large area problem that resistance brings, and has area characteristic little and low in energy consumption;
7. the positive temperature coefficient (PTC) voltage generation unit of this invention and sum unit share sequential, have avoided the complicacy that more multiple timings design is brought.
Accompanying drawing explanation
Fig. 1 is composition frame chart of the present invention.
Fig. 2 is a kind of novel low-power consumption non-resistance type reference voltage generating circuit figure of the present invention.
In figure: Ms1-the first metal-oxide-semiconductor, Ms2-the second metal-oxide-semiconductor, Ms3-the 3rd metal-oxide-semiconductor, Ms4-the 4th metal-oxide-semiconductor, M1-the 5th metal-oxide-semiconductor, M2-the 6th metal-oxide-semiconductor, M3-the 7th metal-oxide-semiconductor, M4-the 8th metal-oxide-semiconductor, M5-the 9th metal-oxide-semiconductor, M6-the tenth metal-oxide-semiconductor, M7-the 11 metal-oxide-semiconductor, M8-the 12 metal-oxide-semiconductor, M9-the 13 metal-oxide-semiconductor, M10-the 14 metal-oxide-semiconductor, M11-the 15 metal-oxide-semiconductor, M12-the 16 metal-oxide-semiconductor, M13-the 17 metal-oxide-semiconductor, M14-the 18 metal-oxide-semiconductor, M15-the 19 metal-oxide-semiconductor, M16-the 20 metal-oxide-semiconductor, M17-the 21 metal-oxide-semiconductor, M18-the 22 metal-oxide-semiconductor, M19-the 23 metal-oxide-semiconductor, M20-the 24 metal-oxide-semiconductor, C1-the first electric capacity, C2-the second electric capacity, C3-the 3rd electric capacity, C4-the 4th electric capacity, VREF-reference voltage output end,
φ 1the-the first clock signal
, φ 2the-the second clock signal.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is specifically described.
A kind of novel low-power consumption non-resistance type reference voltage generating circuit of the present invention, comprises a start unit, and described start unit is connected to sum unit through positive temperature coefficient (PTC) voltage generation unit and negative temperature coefficient voltage generation unit; One end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected VDD, and the other end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected GND; Described positive temperature coefficient (PTC) voltage generation unit output positive temperature coefficient (PTC) voltage is to sum unit; Described negative temperature coefficient voltage cell output negative temperature coefficient voltage is to sum unit; Described sum unit is sued for peace to positive temperature coefficient (PTC) voltage and negative temperature coefficient voltage, and output reference voltage; Described positive temperature coefficient (PTC) voltage generation unit is also for negative temperature coefficient voltage generation unit provides bias current; Described start unit provides open function for whole circuit.
Be below embodiments of the invention.
The composition frame chart of reference voltage generating circuit of the present invention as shown in Figure 1, comprising positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit, sum unit and start unit; Reference voltage generating circuit of the present invention is (being 1. start unit, is 2. positive temperature coefficient (PTC) voltage generation unit, is 3. negative temperature coefficient voltage generation unit, is 4. sum unit) as shown in Figure 2; Wherein positive temperature coefficient (PTC) voltage generation unit output positive temperature coefficient (PTC) voltage is to sum unit, negative temperature coefficient voltage generation unit output negative temperature coefficient voltage is to sum unit, sum unit is sued for peace to positive temperature coefficient (PTC) voltage and negative temperature coefficient voltage, final output reference voltage; Simultaneously positive temperature coefficient (PTC) voltage generation unit provides bias current for negative temperature coefficient voltage generation unit; Start unit provides open function for whole circuit.
Reference voltage generating circuit also comprises a pulse signal generator; Pulse signal generator comprises output
φ 1the first clock signal output terminal and output
φ 2the second clock signal output terminal;
φ 1with
φ 2sequential non-overlapping copies.
As shown in Figure 2,2. positive temperature coefficient (PTC) voltage generation unit comprises Ms1 to Ms2 and M1 to M10; The drain electrode of Ms1, the source electrode of M1, the source electrode of M2 and the source electrode of M9 are all connected to VDD; The source electrode of Ms1 is connected to the drain electrode of Ms2, and the source electrode of Ms1 is also connected to GND through C1; The source electrode of Ms2 is connected with the source electrode of M3; The drain and gate of M3 is connected to the grid of the drain electrode of M6, M4 and the grid of M10; The grid of M1 is connected to the source electrode of M4 with drain electrode; The drain electrode of M4 is connected with the drain electrode of the grid of M5 and M7; The grid of M2 is connected to the source electrode of M5 with drain electrode; The drain electrode of M5 be connected with the grid of the drain electrode of M8, M8 and the grid of M6 to start unit 1.; The grid of M9 is connected to the source electrode of M10 with drain electrode; The drain electrode of M10 is connected to sum unit with the drain electrode of Ms3; The source electrode of Ms3 connects the drain electrode of Ms4, and is connected to GND through C2; The source electrode of Ms4 meets GND.
The grid of Ms1 and the grid of Ms3 are all connected to the first clock signal output terminal; The grid of Ms2 and the grid of Ms3 are all connected to the second clock signal output terminal.
Wherein, M1 ~ M10 is operated in saturation region, and M1 and M2 adopt diode connected mode; M3, M4 and M10 form current mirror form, and M6, M7 and M8 also form current mirror form, guarantee that branch current can accurately copy; Ms1, Ms2 and C1 form basic switching capacity unit, can be equivalent to resistance, set
φ 1the cycle of sequential is T,
φ 1with
φ 2two mutual non-overlapping sequential; Can release the equivalent resistance at node D and node E two ends according to the characteristic of switching capacity:
In like manner Ms3, Ms4 and C2 also form basic switching capacity unit, can know the equivalent resistance at node F and node G two ends:
Be exactly can obtain very high resistance value with very little area in integrated circuit by the advantage of switching capacity equivalent resistance, generally, if make the resistance of large resistance with diffusion resistance or polysilicon resistance in integrated circuit, need to account for very large chip area, and adopt switching capacity while carrying out equivalence, two analog switches and the little electric capacity that on chip, only need be realized by two metal-oxide-semiconductors.
From formula (1) and formula (2), equivalent resistance is larger, and required C value is less, and the area that takies chip is also less, therefore can obtain required resistance value R1 and R2 by adjustment cycle T and capacitor C 1, C2.
Therefore adopt equivalent resistance form in this invention can solve the tradeoff of area and power consumption, to obtain less area and less power consumption.
Set the breadth length ratio of pipe
, can make electric current I 3=4I4=4I5, can obtain according to saturation region I-V characteristic:
Wherein Vth is the threshold voltage of MOSFET, and μ is the mobility of charge carrier in raceway groove, and COX is the gate oxide electric capacity of unit area.
According to drawing shown in Fig. 2
; Can be released by formula (3):
The breadth length ratio of setting M10 and M3 is
, therefore finally can draw positive temperature coefficient (PTC) voltage:
Can be obtained by simplified style (5) by formula (1) and formula (2):
For the positive temperature coefficient (PTC) voltage generation unit of this invention, M3, M4, M5, M8, M7 and M6 have formed feedback loop, and M5, M8 and M7 have also formed feedback loop; These two feedback loops have guaranteed that electric current can accurately copy, and have greatly improved the Power Supply Rejection Ratio of circuit simultaneously; In the time that supply voltage changes, suppose that Node B current potential rises, by M6, the current potential of node C will be declined, then can make the current potential of node A increase by M4, finally can make Node B voltage drop by M5, by feedback loop stable the current potential of node A, B and C.
The effect of dividing potential drop is played in the introducing of M2, and the effect of dividing potential drop is not only played in the introducing of M9, and M9 is also for next stage negative temperature coefficient voltage generation unit provides bias current simultaneously.
As shown in Figure 2,3. negative temperature coefficient voltage generation unit of the present invention, comprises M11 to M13; The source electrode of M11 is connected to VDD, and the grid of M11 is connected to the grid of M9, and the drain electrode of M11 is connected with the grid of the drain electrode of M12, M12 and the grid of M13; The source electrode of M12 be connected with the drain electrode of the 17 metal-oxide-semiconductor to sum unit 4.; The source electrode of M13 meets GND.
Wherein, M12 and M13 are operated in sub-threshold region, and the threshold voltage of M13 is greater than the threshold voltage of M12, can obtain according to sub-threshold region I-V characteristic:
Wherein I0 is the specific currents of MOSFET
; ζ is the sub-threshold slope factor, and its representative value is between 1 ~ 3; VT=kT/q(k is Boltzmann constant, and q is electron charge), under normal temperature, be 26mV.
If VDS>>VT or Vth>> ζ VT, (7) formula can be reduced to:
Be operated in sub-threshold region according to M12 and M13, can derive:
（10）
Wherein Vth12, Vth13 and I012, I013 is respectively threshold voltage and the specific currents of M12, M13; Can draw according to Fig. 2:
（11）
Can be derived by formula (9) ~ (11):
(12) in formula, need only
value is suitable, just can make in (9) formula
value approach 0, therefore finally can be similar to and draw:
Because M12 and M13 threshold voltage vt h have negative temperature characteristic, so the difference of M13 and M12 threshold voltage (△ Vth) also has negative temperature characteristic; The negative temperature coefficient voltage generation circuit that the present invention obtains, with respect to adopting the base-emitter voltage (Vbe) of bipolar transistor as negative temperature coefficient voltage, its circuit is realized simple, and power consumption is very little.
As shown in Figure 2,4. sum unit of the present invention, comprises M14 to M17; The grid of M14 and the grid of M17 are all connected to the second clock signal output terminal; The grid of M15 and the grid of M16 are all connected to the first clock signal output terminal; The source electrode of M14 is connected to the source electrode of M12; The drain electrode of M14 and the source electrode of M15 are connected to GND through C3; The drain electrode of M15 is connected to reference voltage output end with the drain electrode of M16; The source electrode of M16 and the source electrode of M17 are connected to GND through C4; The source electrode of M17 connects the drain electrode of M10.
Wherein, M14, M15, M16 and M17 are switch MOS pipes, serve as on-off action, M15 and M16 by
φ 1sequential control, M14 and M17 by
φ 2sequential control; Ultimate principle is to work as
φ 2when high level,
φ 1in low level place, now M14 and M17 open, and M15 and M16 close, and the VCTAT of input and the VPTAT of input give respectively capacitor C 3 and C4 charging, the charge Q 3=VCTATC3 of circuit, Q4=VPTATC4; When
φ 1high level, and
φ 2in the time of low level, now M15 and M16 open, and M14 and M17 close, and can obtain:
（14）
Therefore can derive:
（15）
By adjusting C3 and C4 value, can output reference voltage.This summing circuit, without adopting large resistance, has reduced the area of chip, and not consumed DC current of this reference voltage, has characteristic low in energy consumption simultaneously.In CMOS technique, electric capacity has again the matched well characteristic that is superior to resistance.To sum up, this summing circuit has better performance.
Positive temperature coefficient (PTC) voltage generation unit and sum unit share
φ 1with
φ 2sequential, has reduced the complicacy of timing Design.
Can obtain according to formula (6), (13) and (15):
（16）
By adjustment type (16) coefficient value, can draw the reference voltage of low-temperature coefficient; Are all capacitances for its coefficient of formula (16), for CMOS technique, electric capacity has the matched well characteristic that is superior to resistance, and the reference voltage that therefore this invention produces can be realized very low temperature coefficient.
As shown in Figure 2,1. start unit of the present invention, comprises M18 to M20; The source electrode of M18 and the source electrode of M19 are all connected to VDD; The grid of M18 and the grid of M20 are all connected to GND; The drain electrode of M18 is connected with the grid of M19 to drain electrode and the source electrode of M20; The drain electrode of M19 is connected to the grid of M6.
Start unit is made up of M18, M19 and M20, and wherein M20 serves as electric capacity; In the time of power supply electrifying, M18 and M19 conducting, because electric current is injected into M8, therefore M8 starts conducting, circuit is started working thereupon, and the electric current of M18 will charge to electric capacity M20 simultaneously, make the source gate voltage of M20 can increase to gradually Vdd, after this M18, M19 manage cut-off, and therefore, in the time that circuit is normally worked, start-up circuit can consume power consumption hardly; Meanwhile, this start-up circuit is without adopting traditional discrete capacitor, and this has just reduced the area of start-up circuit.
Be more than preferred embodiment of the present invention, all changes of doing according to technical solution of the present invention, when the function producing does not exceed the scope of technical solution of the present invention, all belong to protection scope of the present invention.
Claims (7)
1. a novel low-power consumption non-resistance type reference voltage generating circuit, is characterized in that: comprise a start unit, described start unit is connected to sum unit through positive temperature coefficient (PTC) voltage generation unit and negative temperature coefficient voltage generation unit; One end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected VDD, and the other end of described start unit, positive temperature coefficient (PTC) voltage generation unit, negative temperature coefficient voltage generation unit and sum unit is connected GND; Described positive temperature coefficient (PTC) voltage generation unit output positive temperature coefficient (PTC) voltage is to sum unit; Described negative temperature coefficient voltage cell output negative temperature coefficient voltage is to sum unit; Described sum unit is sued for peace to positive temperature coefficient (PTC) voltage and negative temperature coefficient voltage, and output reference voltage; Described positive temperature coefficient (PTC) voltage generation unit is also for negative temperature coefficient voltage generation unit provides bias current; Described start unit provides open function for whole circuit.
2. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 1, is characterized in that: described positive temperature coefficient (PTC) voltage generation unit comprises the first metal-oxide-semiconductor to the 14 metal-oxide-semiconductors; The drain electrode of described the first metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor, the 6th source electrode of metal-oxide-semiconductor and the source electrode of the 13 metal-oxide-semiconductor are all connected to VDD; The source electrode of described the first metal-oxide-semiconductor is connected to the drain electrode of the second metal-oxide-semiconductor, and the source electrode of described the first metal-oxide-semiconductor is also connected to GND through the first electric capacity; The source electrode of described the second metal-oxide-semiconductor is connected with the source electrode of the 7th metal-oxide-semiconductor; The drain and gate of described the 7th metal-oxide-semiconductor is connected to the drain electrode of the tenth metal-oxide-semiconductor, the 8th grid of metal-oxide-semiconductor and the grid of the 14 metal-oxide-semiconductor; The grid of described the 5th metal-oxide-semiconductor is connected to the source electrode of the 8th metal-oxide-semiconductor with drain electrode; The drain electrode of described the 8th metal-oxide-semiconductor is connected with the drain electrode of the 11 metal-oxide-semiconductor with the grid of the 9th metal-oxide-semiconductor; The grid of described the 6th metal-oxide-semiconductor is connected to the source electrode of the 9th metal-oxide-semiconductor with drain electrode; The grid of described the 9th drain electrode of metal-oxide-semiconductor and the drain electrode of the 12 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor is connected to start unit with the grid of the tenth metal-oxide-semiconductor; The grid of described the 13 metal-oxide-semiconductor is connected to the source electrode of the 14 metal-oxide-semiconductor with drain electrode; The drain electrode of described the 14 metal-oxide-semiconductor is connected to sum unit with the drain electrode of the 3rd metal-oxide-semiconductor; The source electrode of described the 3rd metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, and is connected to GND through the second electric capacity; The source electrode of described the 4th metal-oxide-semiconductor meets GND.
3. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 2, is characterized in that: also comprise a pulse signal generator; Described pulse signal generator comprises exports the first clock signal output terminal of the first clock signal and the second clock signal output terminal of output the second clock signal; The sequential non-overlapping copies of described the first clock signal and the second clock signal.
4. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 3, is characterized in that: the grid of the grid of described the first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is all connected to the first clock signal output terminal; The grid of the grid of described the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is all connected to the second clock signal output terminal.
5. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 3, is characterized in that: described negative temperature coefficient voltage generation unit comprises the 15 metal-oxide-semiconductor to the 17 metal-oxide-semiconductors; The source electrode of described the 15 metal-oxide-semiconductor is connected to VDD, the grid of described the 15 metal-oxide-semiconductor is connected to the grid of the 13 metal-oxide-semiconductor, and the grid of described the 15 drain electrode of metal-oxide-semiconductor and the drain electrode of the 16 metal-oxide-semiconductor, the 16 metal-oxide-semiconductor is connected with the grid of the 17 metal-oxide-semiconductor; The source electrode of described the 16 metal-oxide-semiconductor is connected to sum unit with the drain electrode of the 17 metal-oxide-semiconductor; The source electrode of described the 17 metal-oxide-semiconductor meets GND.
6. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 5, is characterized in that: described sum unit comprises the 18 metal-oxide-semiconductor to the 21 metal-oxide-semiconductors; Described the 18 grid of metal-oxide-semiconductor and the grid of the 21 metal-oxide-semiconductor are all connected to the second clock signal output terminal; Described the 19 grid of metal-oxide-semiconductor and the grid of the 20 metal-oxide-semiconductor are all connected to the first clock signal output terminal; The source electrode of described the 18 metal-oxide-semiconductor is connected to the source electrode of the 16 metal-oxide-semiconductor; Described the 18 drain electrode of metal-oxide-semiconductor and the source electrode of the 19 metal-oxide-semiconductor are connected to GND through the 3rd electric capacity; The drain electrode of described the 19 metal-oxide-semiconductor is connected to reference voltage output end with the drain electrode of the 20 metal-oxide-semiconductor; Described the 20 source electrode of metal-oxide-semiconductor and the source electrode of the 21 metal-oxide-semiconductor are connected to GND through the 4th electric capacity; The source electrode of described the 21 metal-oxide-semiconductor connects the drain electrode of the 14 metal-oxide-semiconductor.
7. a kind of novel low-power consumption non-resistance type reference voltage generating circuit according to claim 6, is characterized in that: described start unit comprises the 22 metal-oxide-semiconductor to the 24 metal-oxide-semiconductors; Described the 22 source electrode of metal-oxide-semiconductor and the source electrode of the 23 metal-oxide-semiconductor are all connected to VDD; Described the 22 grid of metal-oxide-semiconductor and the grid of the 24 metal-oxide-semiconductor are all connected to GND; The drain electrode of described the 22 metal-oxide-semiconductor is connected with the grid of the 23 metal-oxide-semiconductor to drain electrode and the source electrode of the 24 metal-oxide-semiconductor; The drain electrode of described the 23 metal-oxide-semiconductor is connected to the grid of the tenth metal-oxide-semiconductor.
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| CN201410074785.7A CN103809644A (en) | 2014-03-04 | 2014-03-04 | Novel low-power-consumption resistor-free type reference voltage generation circuit |
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| CN201410074785.7A CN103809644A (en) | 2014-03-04 | 2014-03-04 | Novel low-power-consumption resistor-free type reference voltage generation circuit |
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| CN103809644A true CN103809644A (en) | 2014-05-21 |
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| CN201410074785.7A Withdrawn CN103809644A (en) | 2014-03-04 | 2014-03-04 | Novel low-power-consumption resistor-free type reference voltage generation circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107066006A (en) * | 2017-05-05 | 2017-08-18 | 中国科学院微电子研究所 | Novel band gap reference circuit structure |
| CN112327990A (en) * | 2020-11-06 | 2021-02-05 | 电子科技大学 | Output voltage adjustable low-power consumption sub-threshold reference voltage generating circuit |
| CN113655842A (en) * | 2021-09-23 | 2021-11-16 | 华东光电集成器件研究所 | Zero temperature drift reference source circuit device |
| CN114281144A (en) * | 2020-09-28 | 2022-04-05 | 深圳英集芯科技股份有限公司 | Constant-temperature current source applicable to low power supply voltage, chip and electronic equipment |
| CN114594821A (en) * | 2022-03-03 | 2022-06-07 | 珠海澳大科技研究院 | Reference source circuit and electronic device |
-
2014
- 2014-03-04 CN CN201410074785.7A patent/CN103809644A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107066006A (en) * | 2017-05-05 | 2017-08-18 | 中国科学院微电子研究所 | Novel band gap reference circuit structure |
| CN107066006B (en) * | 2017-05-05 | 2018-07-20 | 中国科学院微电子研究所 | Novel band gap reference circuit structure |
| CN114281144A (en) * | 2020-09-28 | 2022-04-05 | 深圳英集芯科技股份有限公司 | Constant-temperature current source applicable to low power supply voltage, chip and electronic equipment |
| CN114281144B (en) * | 2020-09-28 | 2023-08-29 | 深圳英集芯科技股份有限公司 | Constant-temperature current source, chip and electronic equipment applicable to low power supply voltage |
| CN112327990A (en) * | 2020-11-06 | 2021-02-05 | 电子科技大学 | Output voltage adjustable low-power consumption sub-threshold reference voltage generating circuit |
| CN112327990B (en) * | 2020-11-06 | 2021-07-09 | 电子科技大学 | Output voltage adjustable low-power consumption sub-threshold reference voltage generating circuit |
| CN113655842A (en) * | 2021-09-23 | 2021-11-16 | 华东光电集成器件研究所 | Zero temperature drift reference source circuit device |
| CN114594821A (en) * | 2022-03-03 | 2022-06-07 | 珠海澳大科技研究院 | Reference source circuit and electronic device |
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Application publication date: 20140521 |