CN101557215B - Voltage comparator - Google Patents
Voltage comparator Download PDFInfo
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- CN101557215B CN101557215B CN200810128137XA CN200810128137A CN101557215B CN 101557215 B CN101557215 B CN 101557215B CN 200810128137X A CN200810128137X A CN 200810128137XA CN 200810128137 A CN200810128137 A CN 200810128137A CN 101557215 B CN101557215 B CN 101557215B
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- 150000001875 compounds Chemical class 0.000 claims abstract description 23
- 230000000052 comparative effect Effects 0.000 claims description 22
- 238000007493 shaping process Methods 0.000 claims description 21
- 238000005070 sampling Methods 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
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Abstract
The invention discloses a voltage comparator comprising a compound circuit. The compound circuit comprises a first PMOS tube, a second PMOS tube, a first NPN tube, a second NPN tube, a first resistor and a second resistor. Source electrodes of the first PMOS tube and the second PMOS tube are connected with power supply, a grid electrode and a drain electrode of the first PMOS tube are in a short circuit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube so as to form a current mirror; the drain electrode of the first PMOS tube is connected with a collector of the first NPN tube, the drain electrode of the second PMOS tube is connected with a collector of the second NPN tube, base electrodes of the first NPN tube and the second NPN tube are connected with sampling voltage, an emitter electrode of the second NPN tube is connected with a positive electrode of a third resistor, the emitter electrode of the first NPN tube is connectedwith a negative electrode of the third resistor, the positive electrode of a fourth resistor is connected with the negative electrode of the third resistor, and the negative electrode of the fourth r esistor is grounded. A reference voltage source and the comparator are combined into one, thus reducing number of devices in the circuit, static power consumption and dynamic power consumption, and effective area of an integrated circuit chip.
Description
Technical field
The present invention relates generally to field of analog integrated circuit, relates in particular to the voltage comparator of the self-built a reference source in a kind of inside.
Background technology
(Integrated circuit IC) develops into millions of devices from the minority interconnect devices that is manufactured on the silicon single-chip to integrated circuit.Present integrated circuit provides considerably beyond the performance of the initial imagination and complexity.For the improvement of implementation complexity and current densities (that is, can be closed to the device count on the given chip area), minimum device feature size diminishes for differentiation along with each of integrated circuit.
Increase current densities and not only improved the complexity and the performance of integrated circuit, also more low cost components is provided the consumer.IDE is worth several hundred million even multi-million dollar, and each facility has certain number of wafers, and each wafer has the integrated circuit of some above that.Therefore, littler through the individual devices that makes integrated circuit, can on each wafer, make more device.Make the littler very challenging property of device, because given technology, device layout and/or system design are only effective to certain characteristic size usually.
The example of this restriction is a voltage comparator, and voltage comparator can be integrated in the different integrated circuits.Voltage comparator is an integrated transporting discharging nonlinear application circuit; It often is applied in the various electronic equipments, and voltage comparator is widely used in composite signal integrated circuits, particularly power integrated circuit; Be one of most important analog integrated circuit module, have important function.In power integrated circuit; Voltage comparator is commonly used in the circuit modules such as electrification reset, overvoltage detection, under-voltage detection, under-voltage locking, overvoltage protection, overcurrent protection, overheat protector, and these circuit modules shield to power integrated circuit, late-class circuit system.
In existing circuit engineering; Great majority are used in the voltage comparator in the circuit such as electrification reset, overvoltage detection, under-voltage detection, all adopt independently Bandgap Reference Voltage Generation Circuit generation reference voltage, and passing through independently again, comparator compares sampled voltage and reference voltage; Therefore existing voltage comparator has bigger quiescent dissipation and dynamic power consumption; Have more device count, also therefore increased the effective area of chip, can't further reduce cost.
Summary of the invention
In view of this, the object of the present invention is to provide the voltage comparator of building a reference source in a kind of, reduce the device count in the circuit, reduce quiescent dissipation and dynamic power consumption, dwindle the effective area of chip.
The invention provides a kind of voltage comparator, comprise compound circuit, build reference voltage source and comparator in the said compound circuit, said compound circuit is used to receive sampled voltage, exports comparative voltage in the back with the internal reference voltage ratio.
Preferably, said compound circuit comprises a PMOS transistor, the 2nd PMOS transistor, first NPN transistor, second NPN transistor and first resistance and second resistance;
Transistorized source electrode of a said PMOS and the transistorized source electrode of said the 2nd PMOS connect power supply; A transistorized grid of a said PMOS and a said PMOS transistor drain short circuit; The transistorized grid of said the 2nd PMOS is connected with the transistorized grid of a said PMOS, constitutes current mirror;
A said PMOS transistor drain connects the collector electrode of said first NPN transistor, and said the 2nd PMOS transistor drain connects the collector electrode of said second NPN transistor;
The base stage of the base stage of said first NPN transistor and said second NPN transistor receives sampled voltage as input; The emitter of said second NPN transistor connects the positive pole of said first resistance; The emitter of said first NPN transistor connects the negative pole of said first resistance; The positive pole of said second resistance connects the negative pole of said first resistance, the minus earth of said second resistance;
The collector electrode of said the 2nd PMOS transistor drain and said second NPN transistor is exported comparative voltage as output.
Preferably, the emitter area of said second NPN transistor is 4 times of emitter area of said first NPN transistor.
Preferably, also comprise:
The comparative result amplifying circuit is used for said comparative voltage is amplified, the output amplifying voltage.
Preferably, said comparative result amplifying circuit comprises the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor;
The transistorized grid of said the 3rd PMOS receives comparative voltage as input, and the transistorized source electrode of said the 3rd PMOS connects power supply, and the drain electrode of said the 3rd PMOS transistor drain and said the 5th nmos pass transistor is connected, as output output amplifying voltage;
Connect current offset behind the grid of said the 4th nmos pass transistor and the drain electrode short circuit, the source ground of said the 4th nmos pass transistor, the grid of said the 5th nmos pass transistor connects the grid of said the 4th nmos pass transistor, the source ground of said the 5th nmos pass transistor.
Preferably, also comprise:
Shaping circuit is used for said amplifying voltage is carried out shaping output Shaping voltage.
Preferably, said shaping circuit comprises the 7th PMOS transistor and the 8th nmos pass transistor;
The source ground of said the 8th nmos pass transistor, the grid of transistorized grid of said the 7th PMOS and said the 8th nmos pass transistor is connected, and receives amplifying voltage as input;
The transistorized source electrode of said the 7th PMOS connects power supply, and the drain electrode of said the 7th PMOS transistor drain and said the 8th nmos pass transistor is connected, as output output Shaping voltage.
Preferably, the rise time of the output of said shaping circuit and fall time are less than predetermined threshold value, and the level of output is power supply and ground level.
Preferably, also comprise:
Sample circuit is used to receive external voltage, external voltage is sampled the linear sampled voltage that dwindles of output.
Preferably, said sample circuit comprises the 3rd resistance and the 4th resistance;
The positive pole of said the 3rd resistance connects external voltage, and the negative pole of said the 3rd resistance links to each other with the positive pole of said the 4th resistance, as output output sampled voltage, the minus earth of said the 4th resistance.
Compare with the voltage comparator of prior art, the present invention does not need independently comparator comparison sampled voltage and reference voltage, but unites two into one reference voltage source and comparator; Reduced the device count in the circuit; Simplify design, reduced quiescent dissipation and dynamic power consumption, dwindled the effective area of IC chip; Reduce manufacturing cost, can better satisfy the needs of IC industry production.
Description of drawings
Fig. 1 preferably implements a kind of circuit diagram of compound circuit of voltage comparator for the present invention;
Fig. 2 is the composition structured flowchart of a kind of voltage comparator of the preferred embodiment of the present invention;
Fig. 3 is the physical circuit schematic diagram of the said voltage comparator of Fig. 2;
Fig. 4 is the physical circuit schematic diagram of shaping circuit among Fig. 3.
Embodiment
For making the object of the invention, technical scheme and advantage express clearlyer, the present invention is remake further detailed explanation below in conjunction with accompanying drawing and specific embodiment.
At first, technical term involved in the present invention is described:
PMOS:P-channel metal oxide semiconductor FET, the P-channel metal-oxide-semiconductor field-effect transistor;
NMOS:N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor.
A kind of voltage comparator of the present invention comprises compound circuit, builds reference voltage source and comparator in the said compound circuit, and said compound circuit is used to receive sampled voltage, exports comparative voltage in the back with the internal reference voltage ratio.
With reference to Fig. 1, show the circuit diagram that the present invention preferably implements a kind of compound circuit of voltage comparator.Said compound circuit comprises: a PMOS transistor M1, the 2nd PMOS transistor M2, the first NPN transistor Q1, the second NPN transistor Q2 and first resistance R 1 and first resistance R 2.
Wherein, The source electrode of the source electrode of a said PMOS transistor M1 and said the 2nd PMOS transistor M2 connects power supply; The drain electrode short circuit of the grid of a said PMOS transistor M1 and a said PMOS transistor M1; The grid of said the 2nd PMOS transistor M2 is connected with the grid of a said PMOS transistor M1, constitutes current mirror.The drain electrode of a said PMOS transistor M1 connects the collector electrode of the said first NPN transistor Q1, and the drain electrode of said the 2nd PMOS transistor M2 connects the collector electrode of the said second NPN transistor Q2.The base stage of the base stage of the said first NPN transistor Q1 and the said second NPN transistor Q2 receives sampled voltage as input; The emitter of the said second NPN transistor Q2 connects the positive pole of said first resistance R 1; The emitter of the said first NPN transistor Q1 connects the negative pole of said first resistance R 1; The positive pole of said first resistance R 2 connects the negative pole of said first resistance R 1, the minus earth of said first resistance R 2.The drain electrode of said the 2nd PMOS transistor M2 is connected with the collector electrode of the said second NPN transistor Q2, as output output comparative voltage.
Said compound circuit serves as bandgap voltage reference on the one hand; Its reference voltage is the base voltage of the said first NPN transistor Q1 and the second NPN transistor Q2; In embodiments of the present invention, the emitter area of the said second NPN transistor Q2 is 4 times of emitter area of the said first NPN transistor Q1.Draw by following expression:
Wherein
Said V
BgExpression reference voltage, V
BE1Emitter junction (base-emitter) voltage of representing the first NPN transistor Q1, V
TThe expression thermal voltage.
Utilize said reference voltage in the embodiment of the invention, compare, realize the effect of voltage comparator with sampled voltage after the sampling.When sampled voltage less than the V in the formula
BgThe time, the collector current that flow through the first NPN transistor Q1 this moment is greater than the collector current that flows through the second NPN transistor Q2, and this kind result will be that the source voltage of the 2nd PMOS transistor M2 raises.When sampled voltage greater than the V in the formula
BgThe time, the collector current that flow through the first NPN transistor Q1 this moment is less than the collector current that flows through the second NPN transistor Q2, and this kind result will be that the source voltage of the 2nd PMOS transistor M2 reduces.
A kind of form of the compound circuit of voltage comparator of the present invention has below just been described; Those having ordinary skill in the art will appreciate that; Said compound circuit can also comprise other various ways, as changing the connected mode of resistance, increases one or more resistance and connects with said first resistance R 1 or second resistance R 2; In order to practice thrift length, be not described in detail the connected mode of various circuit at this.
The embodiment of the invention does not need independently, and comparator compares sampled voltage and reference voltage; But unite two into one reference voltage source and comparator, reduced the device count in the circuit, simplified design; Quiescent dissipation and dynamic power consumption have been reduced; Dwindle the effective area of IC chip, reduced manufacturing cost, can better satisfy the needs of IC industry production.
Referring to Fig. 2, show the composition structured flowchart of a kind of voltage comparator of the preferred embodiment of the present invention.Said voltage comparator comprises:
The compound circuit 20 that is connected with sample circuit 10, be used to receive sampled voltage, and said sampled voltage and internal reference voltage are compared, the output comparative voltage.
The comparative result amplifying circuit 30 that is connected with compound circuit 20, be used for said comparative voltage is amplified the output amplifying voltage.
And the shaping circuit 40 that is connected with said comparative result amplifying circuit 30, be used for said amplifying voltage is carried out shaping output Shaping voltage.
Wherein, the sampled voltage of said sample circuit 10 outputs is equal to or less than external voltage.The rise time of the output of said shaping circuit 40 and fall time are less than predetermined threshold value, and the level of output is power supply and ground level.Said predetermined threshold value can limit according to actual needs; The present invention does not limit this; In embodiments of the present invention; The rise time (t_rise) and the fall time (t_fall) of preferably said shaping circuit output are respectively 5ns and 10ns, and this parameter can be set according to the requirement of subsequent conditioning circuit.
Please combine with reference to Fig. 2, Fig. 3 and Fig. 4, Fig. 3 shows the physical circuit schematic diagram of the said voltage comparator of Fig. 2, and Fig. 4 shows the physical circuit schematic diagram of shaping circuit among Fig. 3.
Wherein, The base stage of the base stage of the said first NPN transistor Q1 and the said second NPN transistor Q2 receives the sampled voltage of sample circuit 10 outputs output as input; The source electrode of the source electrode of a said PMOS transistor M1 and said the 2nd PMOS transistor M2 connects power supply; The drain electrode short circuit of the grid of a said PMOS transistor M1 and a said PMOS transistor M1, the grid of a said PMOS transistor M1 of the grid of said the 2nd PMOS transistor M2 connects, and constitutes current mirror.The drain electrode of a said PMOS transistor M1 connects the collector electrode of the said first NPN transistor Q1, and the drain electrode of said the 2nd PMOS transistor M2 connects the collector electrode of the said second NPN transistor Q2.The base stage of said first, second NPN transistor Q1, Q2 is connected, and connects sampled voltage.The emitter of the said second NPN transistor Q2 connects the positive pole of said first resistance R 1; The emitter of the said first NPN transistor Q1 connects the negative pole of said first resistance R 1; The positive pole of said first resistance R 2 connects the negative pole of said first resistance R 1, the minus earth of said first resistance R 2.The drain electrode of said the 2nd PMOS transistor M2 is connected with the collector electrode of the said second NPN transistor Q2, as output output comparative voltage.
Comparative result amplifying circuit 30 comprises the 3rd PMOS transistor M3, the 4th nmos pass transistor M4, the 5th nmos pass transistor M5.
Wherein, The grid of said the 3rd PMOS transistor M3 receives the comparative voltage that compound circuit 20 outputs are exported as input, and the source electrode of said the 3rd PMOS transistor M3 connects power supply, and the drain electrode of said the 3rd PMOS transistor M3 is connected with the drain electrode of said the 5th nmos pass transistor M5; As output output amplifying voltage; The grid of said the 4th nmos pass transistor M4 and drain electrode short circuit meet current offset Ibs, the source ground of said the 4th nmos pass transistor M4; The grid of said the 5th nmos pass transistor M5 connects the grid of said the 4th nmos pass transistor M4, the source ground of said the 5th nmos pass transistor M5.
Wherein, The grid of said the 7th PMOS transistor M7 is connected with the grid of said the 8th nmos pass transistor M8; Receive the amplifying voltage that comparative result amplifying circuit 30 outputs are exported as input, the source ground of said the 8th nmos pass transistor M8, the source electrode of said the 7th PMOS transistor M7 connects power supply; The drain electrode of said the 7th PMOS transistor M7 is connected with the drain electrode of said the 8th nmos pass transistor M8, as output output Shaping voltage.
Wherein, Said compound circuit 20 serves as bandgap voltage reference on the one hand; Its reference voltage is the base voltage of the said first NPN transistor Q1 and the second NPN transistor Q2; In embodiments of the present invention, the emitter area of the said second NPN transistor Q2 is 4 times of emitter area of the said first NPN transistor Q1.Draw by following expression:
Wherein, said V
BgExpression reference voltage, V
BE1Emitter junction (base-emitter) voltage of representing the first NPN transistor Q1, V
TThe expression thermal voltage.
Utilize said reference voltage in the embodiment of the invention, compare, realize the effect of voltage comparator with sampled voltage after the sampling.When sampled voltage less than the V in the formula
BgThe time, the collector current that flow through the first NPN transistor Q1 this moment is greater than the collector current that flows through the second NPN transistor Q2, and this kind result will be that the source voltage of the 2nd PMOS transistor M2 raises.When sampled voltage greater than the V in the formula
BgThe time, the collector current that flow through the first NPN transistor Q1 this moment is less than the collector current that flows through the second NPN transistor Q2, and this kind result will be that the source voltage of the 2nd PMOS transistor M2 reduces.
The embodiment of the invention does not need independently, and comparator compares sampled voltage and reference voltage; But unite two into one reference voltage source and comparator, reduced the device count in the circuit, simplified design; Quiescent dissipation and dynamic power consumption have been reduced; Dwindle the effective area of IC chip, reduced manufacturing cost, can better satisfy the needs of IC industry production.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a voltage comparator is characterized in that, builds the compound circuit of reference voltage source and comparator in comprising, said compound circuit comprises first NPN transistor, second NPN transistor, a PMOS transistor, the 2nd PMOS transistor;
The base stage of the base stage of said first NPN transistor and said second NPN transistor receives sampled voltage as input, and the base voltage of said first NPN transistor and said second NPN transistor is a reference voltage;
A said PMOS transistor and said the 2nd PMOS transistor constitute current mirror, and said sampled voltage and said reference voltage are compared and export comparative voltage.
2. voltage comparator according to claim 1 is characterized in that, said compound circuit also comprises first resistance and second resistance;
Transistorized source electrode of a said PMOS and the transistorized source electrode of said the 2nd PMOS connect power supply; A transistorized grid of a said PMOS and a said PMOS transistor drain short circuit; The transistorized grid of said the 2nd PMOS is connected with the transistorized grid of a said PMOS, constitutes current mirror;
A said PMOS transistor drain connects the collector electrode of said first NPN transistor, and said the 2nd PMOS transistor drain connects the collector electrode of said second NPN transistor;
The base stage of the base stage of said first NPN transistor and said second NPN transistor receives sampled voltage as input; The emitter of said second NPN transistor connects the positive pole of said first resistance; The emitter of said first NPN transistor connects the negative pole of said first resistance; The positive pole of said second resistance connects the negative pole of said first resistance, the minus earth of said second resistance;
The collector electrode of said the 2nd PMOS transistor drain and said second NPN transistor is exported comparative voltage as output.
3. voltage comparator according to claim 2 is characterized in that:
The emitter area of said second NPN transistor is 4 times of emitter area of said first NPN transistor.
4. voltage comparator according to claim 2 is characterized in that, also comprises:
The comparative result amplifying circuit is used for said comparative voltage is amplified, the output amplifying voltage.
5. voltage comparator according to claim 4 is characterized in that, said comparative result amplifying circuit comprises the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor;
The transistorized grid of said the 3rd PMOS receives comparative voltage as input, and the transistorized source electrode of said the 3rd PMOS connects power supply, and the drain electrode of said the 3rd PMOS transistor drain and said the 5th nmos pass transistor is connected, as output output amplifying voltage;
The grid of said the 4th nmos pass transistor and drain electrode short circuit; Drain electrode connects current offset; The source ground of said the 4th nmos pass transistor, the grid of said the 5th nmos pass transistor connects the grid of said the 4th nmos pass transistor, the source ground of said the 5th nmos pass transistor.
6. voltage comparator according to claim 5 is characterized in that, also comprises:
Shaping circuit is used for said amplifying voltage is carried out shaping output Shaping voltage.
7. voltage comparator according to claim 6 is characterized in that, said shaping circuit comprises the 7th PMOS transistor and the 8th nmos pass transistor;
The source ground of said the 8th nmos pass transistor, the grid of transistorized grid of said the 7th PMOS and said the 8th nmos pass transistor is connected, and receives amplifying voltage as input;
The transistorized source electrode of said the 7th PMOS connects power supply, and the drain electrode of said the 7th PMOS transistor drain and said the 8th nmos pass transistor is connected, as output output Shaping voltage.
8. voltage comparator according to claim 7 is characterized in that:
The rise time of the output of said shaping circuit and fall time are less than predetermined threshold value, and the level of output is power supply and ground level.
9. voltage comparator according to claim 8 is characterized in that, also comprises:
Sample circuit is used to receive external voltage, external voltage is sampled the linear sampled voltage that dwindles of output.
10. voltage comparator according to claim 9 is characterized in that, said sample circuit comprises the 3rd resistance and the 4th resistance;
The positive pole of said the 3rd resistance connects external voltage, and the negative pole of said the 3rd resistance links to each other with the positive pole of said the 4th resistance, as output output sampled voltage, the minus earth of said the 4th resistance.
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| CN200810128137XA CN101557215B (en) | 2008-07-07 | 2008-07-07 | Voltage comparator |
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| CN200810128137XA CN101557215B (en) | 2008-07-07 | 2008-07-07 | Voltage comparator |
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| CN101557215B true CN101557215B (en) | 2012-06-13 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571044A (en) * | 2010-12-22 | 2012-07-11 | 无锡华润上华半导体有限公司 | Voltage comparator |
| CN103036209B (en) * | 2012-12-04 | 2016-03-30 | 嘉兴禾润电子科技有限公司 | Under-voltage protecting circuit in a kind of novel motor drive ic |
| CN105021862A (en) * | 2014-12-09 | 2015-11-04 | 北京中电华大电子设计有限责任公司 | Ultra-low power consumption voltage detection circuit |
| CN106292813B (en) * | 2015-05-14 | 2018-11-16 | 快捷半导体(苏州)有限公司 | Hysteresis comparator, integrated circuit and voltage comparative approach |
| CN108152566B (en) * | 2017-12-04 | 2020-04-07 | 南京中感微电子有限公司 | Voltage detection comparator |
| CN108120871B (en) * | 2017-12-04 | 2020-03-20 | 合肥中感微电子有限公司 | Low offset voltage comparator |
| CN108233900B (en) * | 2017-12-25 | 2019-07-19 | 无锡中感微电子股份有限公司 | Improved voltage comparator |
| CN108649939B (en) * | 2018-04-16 | 2022-07-29 | 芯原微电子(上海)股份有限公司 | Power supply detection circuit and method |
| CN109474263A (en) * | 2018-12-17 | 2019-03-15 | 上海贝岭股份有限公司 | A kind of electrification reset circuit |
| CN112649657B (en) * | 2020-11-25 | 2021-10-29 | 西南大学 | Undervoltage indicating system |
| CN113364436B (en) * | 2021-06-24 | 2023-11-07 | 中颖电子股份有限公司 | Voltage comparison circuit |
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| US4622512A (en) * | 1985-02-11 | 1986-11-11 | Analog Devices, Inc. | Band-gap reference circuit for use with CMOS IC chips |
| US5781043A (en) * | 1993-04-30 | 1998-07-14 | Sgs-Thomson Microelectronics, Inc. | Direct current sum bandgap voltage comparator |
| CN1194502A (en) * | 1997-03-21 | 1998-09-30 | 日本电气株式会社 | Semiconductor device and its input and output circuit |
| US6198312B1 (en) * | 1999-11-19 | 2001-03-06 | Impala Linear Corporation | Low level input voltage comparator |
| CN1311443A (en) * | 2000-02-18 | 2001-09-05 | 密克罗奇普技术公司 | Band-gas voltage comparator used for low voltage testing circuit |
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2008
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4622512A (en) * | 1985-02-11 | 1986-11-11 | Analog Devices, Inc. | Band-gap reference circuit for use with CMOS IC chips |
| US5781043A (en) * | 1993-04-30 | 1998-07-14 | Sgs-Thomson Microelectronics, Inc. | Direct current sum bandgap voltage comparator |
| CN1194502A (en) * | 1997-03-21 | 1998-09-30 | 日本电气株式会社 | Semiconductor device and its input and output circuit |
| US6198312B1 (en) * | 1999-11-19 | 2001-03-06 | Impala Linear Corporation | Low level input voltage comparator |
| CN1311443A (en) * | 2000-02-18 | 2001-09-05 | 密克罗奇普技术公司 | Band-gas voltage comparator used for low voltage testing circuit |
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Owner name: XI'AN POWER-RAIL MICROELECTRONIC TECHNOLOGY CO., L Free format text: FORMER OWNER: XI'AN CHIP-RAIL MICRO. CO., LTD. Effective date: 20130408 |
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Effective date of registration: 20130408 Address after: 710075 A305 room, Xi'an photoelectric Park, No. two, 77 science and technology road, Shaanxi, Xi'an Patentee after: XI'AN ZHANXIN MICROELECTRONICS TECHNOLOGY CO.,LTD. Address before: 710075 A308 room, Xi'an photoelectric Park, No. two, 77 science and technology road, Shaanxi, Xi'an Patentee before: Xi'an Power-Rail Micro Co.,Ltd. |
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Address after: 710075 room A305 of Xi'an hi tech Zone No. 77, No. 77 optoelectronics incubator building, Xi'an high tech Zone, Shaanxi Patentee after: XI'AN ZHANXIN MICROELECTRONIC TECHNOLOGY CO.,LTD. Address before: 710075 A305 room, Xi'an photoelectric Park, No. two, 77 science and technology road, Shaanxi, Xi'an Patentee before: XI'AN ZHANXIN MICROELECTRONICS TECHNOLOGY CO.,LTD. |
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Effective date of registration: 20180207 Address after: Shenzhen Nanshan District City, Guangdong streets High-tech Industrial Park in Guangdong province 518000 Shenzhen Software Park 3 building 201 Patentee after: Shenzhen zhic Microelectronic Technology Co.,Ltd. Address before: 710075 room A305 of Xi'an hi tech Zone No. 77, No. 77 optoelectronics incubator building, Xi'an high tech Zone, Shaanxi Patentee before: XI'AN ZHANXIN MICROELECTRONIC TECHNOLOGY CO.,LTD. |
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