CN108233900B - Improved voltage comparator - Google Patents
Improved voltage comparator Download PDFInfo
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- CN108233900B CN108233900B CN201711415601.9A CN201711415601A CN108233900B CN 108233900 B CN108233900 B CN 108233900B CN 201711415601 A CN201711415601 A CN 201711415601A CN 108233900 B CN108233900 B CN 108233900B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The present invention provides a kind of voltage comparator comprising: current mirroring circuit, 3rd resistor, the 4th resistance, the first bipolar junction transistor, the second bipolar junction transistor, the second current source and third MOS transistor.The mismatch that there are the current mirroring circuit mirror currents of very little to replicate, has very high current copy precision, the precision of the internal reference voltage threshold of voltage comparator can be improved in this way.
Description
[technical field]
The present invention relates to electronic circuit technology field, in particular to a kind of improved voltage comparator.
[background technique]
Current mirror is widely used in various analog circuits, for example, generating current offset or as operation amplifier
The load of device.But due to process deviation, it will lead to output electric current not equal to input current, that is, show as the mismatch of current mirror.
It please refers to shown in Fig. 1, is a kind of circuit diagram of current mirror in the prior art comprising PMOS
(positive channel Metal Oxide Semiconductor) transistor MP1 and MP2, input current source I1 is by electricity
Stream mirror can produce output electric current Io.Due to process deviation, cause when producing in enormous quantities, between PMOS transistor MP1 and MP2
There are mismatches, so that current value of the current value greater than input current source I1 of the output electric current Io of some chips, and some chips
Output electric current Io current value be less than input current source I1 current value.Wish that output electric current Io is more quasi- in some applications
The current value of true duplication input current source I1, for example, accurately duplication can be improved the precision of output electric current or improve electricity
Press the precision of the internal reference voltage threshold of comparator.
Therefore, it is necessary to provide a kind of improved technical solution to reduce the mismatch problems of mirror currents duplication, in turn
Improve the precision of the internal reference voltage threshold of voltage comparator.
[summary of the invention]
The purpose of the present invention is to provide a kind of voltage comparator, with the very high current mirroring circuit of accuracy of repetition, from
And the precision of the internal reference voltage threshold of voltage comparator can be improved.
To solve the above-mentioned problems, the present invention provides a kind of voltage comparator comprising: current mirroring circuit comprising the
One output end and second output terminal；3rd resistor；4th resistance；First bipolar junction transistor, collector and current mirroring circuit
The first output end be connected, emitter is connected with one end of 3rd resistor；Second bipolar junction transistor, base stage with first pair
The base stage of bipolar transistor is connected, and collector is connected with the second output terminal of current mirroring circuit, emitter and 3rd resistor
The other end and one end of the 4th resistance be connected, the other end of the 4th resistance ground connection；Second current source, input terminal is as voltage
The output end of comparator, output end ground connection；Third MOS transistor, the first connecting pin are connected with power end, the second connection
End is connected with the input terminal of the second current source, and grid is connected with the collector of the second bipolar junction transistor.The wherein electric current
Mirror circuit includes the first MOS transistor, the second MOS transistor, first resistor, second resistance, the first adjustable resistance, second adjustable
Resistance, switching circuit and calibration circuit, one end of the first resistor are connected with power end, the other end and the first MOS
First connecting pin of transistor is connected, one end of the second connection end of first MOS transistor and first adjustable resistance
It is connected, the other end of first adjustable resistance is connected with one end of second adjustable resistance, second adjustable resistance
First output end of the other end as the current mirroring circuit；The control terminal and the first adjustable resistance of first MOS transistor
And the second connecting node between adjustable resistance is connected；One end of the second resistance is connected with the power end, the other end
It is connected with the first connecting pin of second MOS transistor, the second connection end of second MOS transistor is as the electric current
The second output terminal of mirror circuit, the switching circuit include that first switch, second switch and third switch, the first switch
One end is connected with the control terminal of the second MOS transistor, the company between the other end and the first adjustable resistance and the second adjustable resistance
Node is connect to be connected；The second switch be connected to the second MOS transistor control terminal and first adjustable resistance one end it
Between, third switch is connected between the control terminal of the second MOS transistor and the other end of the second adjustable resistance, the calibration circuit
It is defeated including first input end, the second input terminal, the first output end, second output terminal, third output end, the 4th output end and the 5th
Outlet, wherein the first input end of the calibration circuit is connected with the other end of the first resistor, the second input terminal and institute
The other end for stating second resistance is connected, and the first output end is connected with the control terminal of first switch, second output terminal and second
The control terminal of switch is connected, and third output end is connected with the control terminal that third switchs, the 4th output end and the first adjustable electric
The adjustable side of resistance is connected, and the 5th output end is connected with the adjustable side of the second adjustable resistance.
Further, the calibration circuit first controls the switching circuit and is in first state, so that first switch is led
Logical, second switch and third switch OFF；At this point, the voltage of the other end of first resistor described in the calibration circuit sampling is to obtain
To the first sampled voltage, the voltage of the other end of the second resistance is sampled to obtain the second sampled voltage；The calibration circuit
Compare the first sampled voltage and the second sampled voltage, it is described when first sampled voltage is greater than second sampled voltage
Difference of the circuit based on the first sampled voltage and the second sampled voltage is calibrated, by the 4th output end by the first adjustable resistance
Effective resistance value be adjusted to first effective resistance value, and the calibration circuit controling switch circuit is in the second state, so that
Two switch conductions, first switch and third switch OFF；When first sampled voltage is less than second sampled voltage, institute
Calibration difference of the circuit based on the second sampled voltage and the first sampled voltage is stated, by the 5th output end by the second adjustable electric
The effective resistance value of resistance is adjusted to second effective resistance value, and the calibration circuit controling switch circuit is in the third state, so that
Third switch conduction, first switch and the second switch shutdown.
Further, first MOS transistor and the matching setting of the second MOS transistor, the first resistor and second
Resistors match setting, and the resistance value of first resistor is equal to the resistance value of second resistance, the liner body end of first MOS transistor and electricity
Source is connected, and the liner body end of second MOS transistor is connected with power end.
Further, the calibration circuit includes the first analog-digital converter, the second analog-digital converter and processor, and described the
One analog-digital converter is used to sample the voltage of the first resistor other end, to obtain the first sampled voltage of analog signal, and
It is converted into the first sampled voltage of digital signal；Second analog-digital converter is for sampling the second resistance other end
Voltage, to obtain the second sampled voltage of analog signal, and be converted into the second sampled voltage of digital signal；The place
Reason device compares the first sampled voltage of digital signal and the second sampled voltage of digital signal, and first when the digital signal is adopted
Sample voltage be greater than the digital signal the second sampled voltage when, first sampled voltage of the processor based on digital signal and
The effective resistance value of first adjustable resistance is adjusted to first effective resistance value by the difference of the second sampled voltage of the digital signal,
And the processor control switch circuit is in the second state；When the first sampled voltage of the digital signal is less than the number
When the second sampled voltage of signal, second sampled voltage and the digital signal of the processor based on the digital signal
The effective resistance value of second adjustable resistance is adjusted to second effective resistance value, and the processor control by the difference of the first sampled voltage
Switching circuit processed is in the third state.
Further, when the first sampled voltage of the digital signal is greater than the second sampled voltage of the digital signal
When, the processor calculates first effective resistance value R3' that the first adjustable resistance needs to be adjusted to according to formula (1),
The processor generates corresponding first adjustment signal according to be calculated first effective resistance value R3', with control
Effective resistance value of first adjustable resistance is equal to first effective resistance value；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processing
Device calculates second effective resistance value R4' that the second adjustable resistance needs to be adjusted to according to formula (2),
The processor generates corresponding second adjustment signal according to be calculated second effective resistance value R4', with control
Effective resistance value of second adjustable resistance is equal to second effective resistance value；Wherein, wherein DV2 is that the second sampling of the digital signal is electric
It presses, the first sampled voltage of digital signal described in DV1, Vs is the quantization voltage steps of the analog-digital converter, and R is first resistor
The resistance value of R1 or second resistance R2, I are the current value of current source I1, and gm is the mutual conductance of the first MOS transistor.
Further, the first MOS transistor MP1 and the second MOS transistor MP2 is PMOS transistor,
The first connecting pin, second connection end and the control terminal of first MOS transistor MP1 is respectively the source of PMOS transistor
Pole, drain and gate；The first connecting pin, second connection end and the control terminal of second MOS transistor MP2 is respectively PMOS transistor
Source electrode, drain and gate.
Compared with prior art, the voltage comparator in the present invention uses improved current mirroring circuit, the current mirror
It is provided with calibration circuit in circuit, can reduce the mismatch of mirror currents duplication, improve the accuracy of repetition of current mirror, in turn
Improve the precision of the internal reference voltage threshold of voltage comparator.
[Detailed description of the invention]
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without any creative labor, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is a kind of circuit diagram of current mirror in the prior art；
Fig. 2 is the circuit diagram of the current mirroring circuit of the present invention in one embodiment；
Fig. 3 is the circuit diagram of the voltage comparator of the present invention in one embodiment.
[specific embodiment]
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
" one embodiment " or " embodiment " referred to herein, which refers to, may be included at least one implementation of the invention
A particular feature, structure, or characteristic." in one embodiment " that different places occur in the present specification not refers both to same
A embodiment, nor the individual or selective embodiment mutually exclusive with other embodiments.Unless stated otherwise, herein
In connection, be connected, connect expression be electrically connected word indicate directly or indirectly to be electrical connected.
It please refers to shown in Fig. 2, for the circuit diagram of the improved current mirroring circuit of the present invention in one embodiment.
Current mirroring circuit shown in Fig. 2 includes the first MOS (metal oxide semiconductor) transistor MP1, the 2nd MOS brilliant
Body pipe MP2, first resistor R1, second resistance R2, the first adjustable resistance R3, the second adjustable resistance R4, switching circuit 210 and calibration
Circuit 220.
One end of the first resistor R1 is connected with power end VIN, and the other end is with the first MOS transistor MP1's
First connecting pin is connected, one end phase of the second connection end of the first MOS transistor MP1 and the first adjustable resistance R3
Even, the other end of the first adjustable resistance R3 is connected with one end of the second adjustable resistance R4, second adjustable resistance
The other end of R4 is connected as the first output end of current mirroring circuit with the input terminal of current source I1, the output of the current source I1
End ground connection；Connection between the control terminal and the first adjustable resistance R3 and the second adjustable resistance R4 of the first MOS transistor MP1
Node is connected；One end of the second resistance R2 is connected with the power end VIN, the other end and second MOS transistor
The first connecting pin of MP2 is connected, the second connection end of the second MOS transistor MP2 as the current mirroring circuit second
Output end Io.
The switching circuit 210 includes first switch S0, second switch S1 and third switch S2, the first switch S0's
One end is connected with the control terminal of the second MOS transistor MP2, the other end and the first adjustable resistance R3 and the second adjustable resistance R4 it
Between connecting node be connected.The second switch S1 is connected to the control terminal and first adjustable electric of the second MOS transistor MP2
Between the one end for hindering R3.Third switch S2 be connected to the second MOS transistor MP2 control terminal and the second adjustable resistance R4 it is another
Between end.
The calibration circuit 220 includes first input end V1, the second input terminal V2, the first output end C0, second output terminal
C1, third output end C2, the 4th output end D1 and the 5th output end D2, wherein the first input end V1 of the calibration circuit 220
It is connected with the other end of the first resistor R1, the second input terminal V2 is connected with the other end of the second resistance R2, the
One output end C0 is connected with the control terminal of first switch S0, and second output terminal C1 is connected with the control terminal of second switch S1,
Third output end C2 is connected with the control terminal of third switch S2, the adjustable side phase of the 4th output end D1 and the first adjustable resistance R3
Even, the 5th output end D2 is connected with the adjustable side of the second adjustable resistance R4.
In the embodiment shown in Figure 2, the first MOS transistor MP1 and the second MOS transistor MP2 matching setting；Institute
First resistor R1 and second resistance R2 matching setting is stated, and the resistance value of first resistor R1 and second resistance R2 are equal.It is shown in Fig. 2
Specific embodiment in, the first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistor, described first
The liner body end of MOS transistor MP1 is connected with power end VIN, liner body end and the power end VIN phase of the second MOS transistor MP2
Even；The first connecting pin, second connection end and the control terminal of first MOS transistor MP1 is respectively the source electrode of PMOS transistor, drain electrode
And grid；The first connecting pin, second connection end and the control terminal of second MOS transistor MP2 be respectively PMOS transistor source electrode,
Drain and gate.
It is understood that the effect of the first current source I1 in Fig. 2 is to provide a reference current for current mirroring circuit
I1, so that the current mirroring circuit can replicate reference current I1, therefore the first current source I1 can be it is any can
The circuit of electric current is provided.
The course of work of the switching circuit 210 and calibration circuit 220 in Fig. 2 is introduced in detail below.
The calibration circuit 220 first controls the switching circuit 210 and is in first state, so that first switch S0 is led
Logical, second switch S2 and third switch S3 shutdown；At this point, the calibration circuit 220 samples the other end of the first resistor R1
Voltage to obtain the first sampled voltage V1, sample the voltage of the other end of the second resistance R2 to obtain the second sampled voltage
V2.When the first sampled voltage V1 is greater than the second sampled voltage V2, the calibration circuit 220 is defeated by the described 4th
The effective resistance value of first adjustable resistance R3 is adjusted to first effective resistance value R3 ' by outlet D1, and the calibration circuit 220 control is opened
Powered-down road 210 is in the second state, so that second switch S1 conducting, first switch S0 and third switch S2 shutdown；When described
When first sampled voltage V1 is less than the second sampled voltage V2, the calibration circuit 220 will by the 5th output end D2
The effective resistance value of second adjustable resistance R4 is adjusted to second effective resistance value R4 ', and the 220 control switch circuit of calibration circuit
210 are in the third state, so that third switch S2 conducting, first switch S0 and second switch S1 shutdown.
In specific embodiment shown in Fig. 2, the calibration circuit 220 includes the first analog-digital converter ADC1 (Analog-
To-Digital Converter), the second analog-digital converter ADC2 and processor CPU (Central Processing Unit,
Central processing unit).
The processor CPU first controls the switching circuit 210 and is in first state, for example, processor CPU control first
Output end C0 exports high level, controls second output terminal C1 and third output end C2 and exports low level, so that first switch S0
Conducting, second switch S2 and third switch S3 shutdown.At this point, the first analog-digital converter ADC1 samples the first resistor R1
The voltage of the other end to obtain the first sampled voltage V1 of analog signal, and is converted into the first sampling electricity of digital signal
Press DV1；The second analog-digital converter ADC2 samples the voltage of the second resistance R2 other end, to obtain the of analog signal
Two sampled voltage V2, and it is converted into the second sampled voltage DV2 of digital signal.
The processor CPU compares the first sampled voltage DV1 of digital signal and the second sampled voltage of digital signal
DV2。
If the second sampled voltage DV2 of digital signal is larger, mean the second sampling of the analog signal sampled
Voltage V2 is greater than the first sampled voltage V1 of analog signal, it is meant that the voltage drop on second resistance R2 is less than on first resistor R1
Voltage drop, show the electric current that electric current on second resistance R2 is less than on first resistor R1, the i.e. leakage of the second MOS transistor MP2
Drain current value of the electrode current value less than the first MOS transistor MP1.The second of digital signal is calculated by the processor CPU
The difference (i.e. DV2-DV1) of sampled voltage DV2 and the first sampled voltage DV1 of digital signal, then according to following formula (2)
The second adjustable resistance R4 is calculated to need the effective resistance value R4'(that is adjusted to it can be described as second effective resistance value R4'):
Wherein DV2 is the second sampled voltage of the digital signal, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter (ADC1, ADC2), R is the resistance of first resistor R1 (or second resistance R2)
Value, I are the current value of current source I1, and gm is the mutual conductance of the second MOS transistor MP2.
The processor CPU generates corresponding second adjustment signal according to above-mentioned second effective resistance value R4' being calculated,
Effective resistance value that second adjustment signal controls the second adjustable resistance R4 by the 5th output end D2, which is equal to second, to be had
Imitate resistance value R4'.And the processor CPU control third output end C2 exports high level, controls the first output end C0 and second
Output end C1 exports low level, so that third switch S2 conducting, first switch S0 and second switch S1 shutdown.This is equivalent to increasing
The gate source voltage of the second MOS transistor MP2 is added, therefore, the drain current of the second MOS transistor MP2 has been increased, so that MP2
Drain current closer to current source I1 current value, to improve the accuracy of repetition of current mirror.
If the first sampled voltage DV1 of digital signal is larger, mean the first sampling of the analog signal sampled
Voltage V1 is greater than the second sampled voltage V2 of analog signal, it is meant that the voltage drop on first resistor R1 is less than on second resistance R2
Voltage drop, show the electric current that electric current on first resistor R1 is less than on second resistance R2, the i.e. leakage of the second MOS transistor MP2
Electrode current value is greater than the drain current value of the first MOS transistor MP1, calculates the first of digital signal by the processor CPU
The difference (i.e. DV1-DV2) of sampled voltage DV1 and the second sampled voltage DV2 of digital signal, then according to following formula (1)
The first adjustable resistance R3 is calculated to need the effective resistance value R3'(that is adjusted to it can be described as first effective resistance value R3'):
Wherein DV2 is the second sampled voltage of the digital signal, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter (ADC1, ADC2), R is the resistance of first resistor R1 (or second resistance R2)
Value, I are the current value of current source I1, and gm is the mutual conductance of the second MOS transistor MP2.
The processor CPU generates corresponding first adjustment signal according to above-mentioned first effective resistance value R3' being calculated,
Effective resistance value that first adjustment signal controls the first adjustable resistance R3 by the 4th output end D1 is equal to first effectively
Resistance value R3'.And the processor CPU control second output terminal C1 exports high level, controls the first output end C0 and third is defeated
Outlet C2 exports low level, so that second switch S1 conducting, first switch S0 and third switch S2 shutdown.This is equivalent to reduction
Therefore the gate source voltage of second MOS transistor MP2 reduces the drain current of the second MOS transistor MP2, so that the leakage of MP2
Electrode current closer to current source I1 current value, to improve the accuracy of repetition of current mirror.
Fig. 3 is the circuit diagram of the voltage comparator 300 of the present invention in one embodiment, wherein the voltage compares
Device 300 is the voltage comparator of internal reference voltage.It is as shown in Figure 3, the voltage comparator 300 include current mirroring circuit 310,
First bipolar junction transistor Q1, the second bipolar junction transistor Q2, the second current source I2,3rd resistor R12, the 4th resistance R11,
Three MOS transistor MP3.The current mirroring circuit 310 can be using the current mirroring circuit in Fig. 2.
The collector of first bipolar junction transistor Q1 is connected with the first output end of current mirroring circuit 310, emitter with
One end of 3rd resistor R12 is connected.The base stage of second bipolar junction transistor Q2 is connected with the base stage of the first bipolar junction transistor Q1,
Voltage input end as voltage comparator 300 later, collector are connected with the second output terminal of current mirroring circuit 310,
Emitter is connected with one end of the other end of 3rd resistor R12 and the 4th resistance R11, the other end ground connection of the 4th resistance R11.The
Output end of the input terminal of two current source I2 as voltage comparator, the output end ground connection of the second current source I2.3rd MOS crystal
The first connecting pin of pipe MP3 is connected with power end VIN, and second connection end is connected with the input terminal of the second current source I2, grid
Pole is connected with the collector of the second bipolar junction transistor Q2.
Wherein the first bipolar junction transistor Q1, the second bipolar junction transistor Q2 are bipolar npn transistor npn npn.3rd MOS
Transistor MP3 is PMOS transistor, and the first connecting pin is the source electrode of PMOS transistor, and second connection end is PMOS transistor
Drain electrode.
With reference to Fig. 3, the emitter area of Q1 and Q2 is usually designed as M:1, the emitter area of Q1 is larger, the two
The difference of Vbe (base-emitter voltage difference) is proportional to lnM, and M is positive number.Vbe2-Vbe1=(KT/q) .lnM, wherein M be Q1 and
The ratio between emitter area of Q2, K are Boltzmann constant, and T is temperature, and q is electron charge, and Vbe1 is the base-emitter of Q1
Voltage, Vbe2 are the base emitter voltage of Q2.At this point, voltage comparator turnover voltage (or be internal reference voltage threshold
Value) are as follows: Vbe2+ (R11/R12) (Vbe2-Vbe1).This formula is ideal situation, if current mirroring circuit 310 there are deviation,
Then cause turnover voltage to deviate this design value, leads to inaccuracy.Mirror currents accuracy of repetition is improved, voltage can be improved and compare
The precision of the turnover voltage of device.
In this embodiment, the part of the first bipolar junction transistor Q1 and 3rd resistor R12 is used for as the in Fig. 2
One current source I1.
Voltage comparator 300 in the present invention uses improved current mirroring circuit, is provided in the current mirroring circuit
Circuit is calibrated, can reduce the mismatch of mirror currents duplication, improves the accuracy of repetition of current mirror, and then improves voltage and compares
The precision of the internal reference voltage threshold of device.
In the present invention, the word that the expressions such as " connection ", connected, " company ", " connecing " are electrical connected, unless otherwise instructed, then
Indicate direct or indirect electric connection.
It should be pointed out that any change that one skilled in the art does a specific embodiment of the invention
All without departing from the range of claims of the present invention.Correspondingly, the scope of the claims of the invention is also not merely limited to
In previous embodiment.
Claims (5)
1. a kind of voltage comparator, characterized in that it comprises:
Current mirroring circuit comprising the first MOS transistor, the second MOS transistor, first resistor, second resistance, the first adjustable electric
Resistance, the second adjustable resistance, switching circuit and calibration circuit, one end of the first resistor is connected with power end, the other end and
First connecting pin of first MOS transistor is connected, the second connection end of first MOS transistor and described first adjustable
One end of resistance is connected, and the other end of first adjustable resistance is connected with one end of second adjustable resistance, and described second
First output end of the other end of adjustable resistance as the current mirroring circuit；The control terminal of first MOS transistor and the
Connecting node between one adjustable resistance and the second adjustable resistance is connected；One end of the second resistance and the power end phase
Even, the other end is connected with the first connecting pin of second MOS transistor, the second connection end of second MOS transistor
As the second output terminal of the current mirroring circuit, the switching circuit includes first switch, second switch and third switch, institute
The one end for stating first switch is connected with the control terminal of the second MOS transistor, and the other end and the first adjustable resistance and second are adjustable
Connecting node between resistance is connected；The second switch is connected to the control terminal of the second MOS transistor and described first adjustable
Between one end of resistance, third switch is connected between the control terminal of the second MOS transistor and the other end of the second adjustable resistance,
The calibration circuit includes first input end, the second input terminal, the first output end, second output terminal, third output end, the 4th defeated
Outlet and the 5th output end, wherein the first input end of the calibration circuit is connected with the other end of the first resistor, the
Two input terminals are connected with the other end of the second resistance, and the first output end is connected with the control terminal of first switch, and second
Output end is connected with the control terminal of second switch, and third output end is connected with the control terminal that third switchs, the 4th output end
It is connected with the adjustable side of the first adjustable resistance, the 5th output end is connected with the adjustable side of the second adjustable resistance；
3rd resistor；
4th resistance；
First bipolar junction transistor, collector are connected with the first output end of current mirroring circuit, emitter and 3rd resistor
One end be connected；
Second bipolar junction transistor, base stage are connected with the base stage of the first bipolar junction transistor, collector and current mirroring circuit
Second output terminal be connected, emitter is connected with one end of the other end of 3rd resistor and the 4th resistance, the 4th resistance it is another
One end ground connection；
Second current source, output end of the input terminal as voltage comparator, output end ground connection；
Third MOS transistor, the first connecting pin are connected with power end, the input terminal phase of second connection end and the second current source
Even, grid is connected with the collector of the second bipolar junction transistor,
First MOS transistor and the second MOS transistor are PMOS transistor,
The first connecting pin, second connection end and the control terminal of first MOS transistor be respectively PMOS transistor source electrode, drain electrode and
Grid；
The first connecting pin, second connection end and the control terminal of second MOS transistor be respectively PMOS transistor source electrode, drain electrode and
Grid.
2. voltage comparator according to claim 1, which is characterized in that
The calibration circuit first controls the switching circuit and is in first state so that first switch conducting, second switch and
Third switch OFF；At this point, the voltage of the other end of first resistor described in the calibration circuit sampling is to obtain the first sampling electricity
Pressure, samples the voltage of the other end of the second resistance to obtain the second sampled voltage；
The calibration circuit compares the first sampled voltage and the second sampled voltage, when first sampled voltage is greater than described second
When sampled voltage, the calibration difference of the circuit based on the first sampled voltage and the second sampled voltage passes through the 4th output
The effective resistance value of first adjustable resistance is adjusted to first effective resistance value by end, and the calibration circuit controling switch circuit is in the
Two-state, so that second switch conducting, first switch and third switch OFF；When first sampled voltage is less than described the
When two sampled voltages, the calibration difference of the circuit based on the second sampled voltage and the first sampled voltage is defeated by the described 5th
The effective resistance value of second adjustable resistance is adjusted to second effective resistance value by outlet, and the calibration circuit controling switch circuit is in
The third state, so that third switch conduction, first switch and the second switch turn off.
3. voltage comparator according to claim 2, which is characterized in that
First MOS transistor and the matching setting of the second MOS transistor,
The first resistor and second resistance matching setting, and the resistance value of first resistor is equal to the resistance value of second resistance,
The liner body end of first MOS transistor is connected with power end, liner body end and the power end phase of second MOS transistor
Even.
4. voltage comparator according to claim 3, which is characterized in that
The calibration circuit includes the first analog-digital converter, the second analog-digital converter and processor,
First analog-digital converter is used to sample the voltage of the first resistor other end, adopts with obtain analog signal first
Sample voltage, and it is converted into the first sampled voltage of digital signal；Second analog-digital converter is for sampling described second
The voltage of the resistance other end to obtain the second sampled voltage of analog signal, and is converted into the second sampling of digital signal
Voltage；
The processor compares the first sampled voltage of digital signal and the second sampled voltage of digital signal,
When the first sampled voltage of the digital signal is greater than the second sampled voltage of the digital signal, the processor base
In the difference of the second sampled voltage of the first sampled voltage and digital signal of digital signal, by having for the first adjustable resistance
Effect resistance value is adjusted to first effective resistance value, and the processor control switch circuit is in the second state；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processor base
In the difference of the first sampled voltage of the second sampled voltage and digital signal of the digital signal, by the second adjustable resistance
Effective resistance value be adjusted to second effective resistance value, and the processor control switch circuit is in the third state.
5. voltage comparator according to claim 4, which is characterized in that
When the first sampled voltage of the digital signal is greater than the second sampled voltage of the digital signal, the processor root
First effective resistance value R3' that the first adjustable resistance needs to be adjusted to is calculated according to formula (1),
The processor generates corresponding first adjustment signal according to be calculated first effective resistance value R3', to control first
Effective resistance value of adjustable resistance is equal to first effective resistance value；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processor root
Second effective resistance value R4' that the second adjustable resistance needs to be adjusted to is calculated according to formula (2),
The processor generates corresponding second adjustment signal according to be calculated second effective resistance value R4', to control second
Effective resistance value of adjustable resistance is equal to second effective resistance value；
Wherein, wherein DV2 be the digital signal the second sampled voltage, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter, R is the resistance value of first resistor R1 or second resistance R2, and I is current mirror electricity
The current value of the first output end output on road, gm are the mutual conductance of the first MOS transistor.
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| CN110471482B (en) * | 2019-08-12 | 2020-10-02 | 兆讯恒达微电子技术(北京)有限公司 | Voltage calibration method and calibration circuit |
| CN113252949B (en) * | 2021-05-13 | 2021-11-05 | 北京芯格诺微电子有限公司 | High-precision current sampling circuit with on-chip real-time calibration |
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| CN101557215A (en) * | 2008-07-07 | 2009-10-14 | 西安民展微电子有限公司 | Voltage comparator |
| CN101630175A (en) * | 2008-12-31 | 2010-01-20 | 曹先国 | Matching current mirror |
| CN102890522A (en) * | 2012-10-24 | 2013-01-23 | 广州润芯信息技术有限公司 | Current reference circuit |
| CN102970789A (en) * | 2011-09-01 | 2013-03-13 | 点晶科技股份有限公司 | Driver circuit and related error detection circuit and method |
| CN104917369A (en) * | 2014-03-14 | 2015-09-16 | 台湾积体电路制造股份有限公司 | Voltage supply unit and method for operating the same |
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| TWI601378B (en) * | 2016-11-17 | 2017-10-01 | 瑞昱半導體股份有限公司 | Resistance calibration circuit and device |
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| KR20150098434A (en) * | 2014-02-20 | 2015-08-28 | 에스케이하이닉스 주식회사 | Current generation circuit and semiconductor device |
| US9413231B2 (en) * | 2014-12-03 | 2016-08-09 | Fairchild Semiconductor Corporation | Charge pump circuit for providing voltages to multiple switch circuits |
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| CN101557215A (en) * | 2008-07-07 | 2009-10-14 | 西安民展微电子有限公司 | Voltage comparator |
| CN101630175A (en) * | 2008-12-31 | 2010-01-20 | 曹先国 | Matching current mirror |
| EP2472723B1 (en) * | 2011-01-04 | 2015-12-16 | ams AG | Amplifier with non-linear current mirror |
| CN102970789A (en) * | 2011-09-01 | 2013-03-13 | 点晶科技股份有限公司 | Driver circuit and related error detection circuit and method |
| CN102890522A (en) * | 2012-10-24 | 2013-01-23 | 广州润芯信息技术有限公司 | Current reference circuit |
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