CN108233900A - Improved voltage comparator - Google Patents
Improved voltage comparator Download PDFInfo
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- CN108233900A CN108233900A CN201711415601.9A CN201711415601A CN108233900A CN 108233900 A CN108233900 A CN 108233900A CN 201711415601 A CN201711415601 A CN 201711415601A CN 108233900 A CN108233900 A CN 108233900A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The present invention provides a kind of voltage comparator, including：Current mirroring circuit, 3rd resistor, the 4th resistance, the first bipolar transistor, the second bipolar transistor, the second current source and third MOS transistor.The current mirroring circuit has the mismatch that the mirror currents of very little replicate, and has very high current copy precision, can improve the precision of the internal reference voltage threshold of voltage comparator in this way.
Description
【Technical field】
The present invention relates to electronic circuit technology field, more particularly to a kind of improved voltage comparator.
【Background technology】
Current mirror is widely used in various analog circuits, for example, generating current offset or as operation amplifier
The load of device.But due to process deviation, output current can be caused to show as the mismatch of current mirror not equal to input current.
It is a kind of circuit diagram of current mirror of the prior art, including PMOS shown in please referring to Fig.1
(positive channel Metal Oxide Semiconductor) transistor MP1 and MP2, input current source I1 is by electricity
Stream mirror can generate output current Io.Due to process deviation, cause when producing in enormous quantities, between PMOS transistor MP1 and MP2
There are mismatches so that current value of the current value of the output current Io of some chips more than input current source I1, and some chips
Output current Io current value be less than input current source I1 current value.Wish that output current Io is more accurate in some applications
The true current value for replicating input current source I1, for example, accurately replicating the precision that can improve output current or improving electricity
Press the precision of the internal reference voltage threshold of comparator.
Therefore, it is necessary to a kind of improved technical solution is provided to reduce the mismatch problems of mirror currents duplication, and then
Improve the precision of the internal reference voltage threshold of voltage comparator.
【Invention content】
The purpose of the present invention is to provide a kind of voltage comparator, with the very high current mirroring circuit of accuracy of repetition, from
And the precision of the internal reference voltage threshold of voltage comparator can be improved.
To solve the above-mentioned problems, the present invention provides a kind of voltage comparator, including：Current mirroring circuit, including
One output terminal and second output terminal；3rd resistor；4th resistance；First bipolar transistor, collector and current mirroring circuit
The first output terminal be connected, emitter is connected with one end of 3rd resistor；Second bipolar transistor, base stage with first pair
The base stage of bipolar transistor is connected, and collector is connected with the second output terminal of current mirroring circuit, emitter and 3rd resistor
The other end and one end of the 4th resistance be connected, the other end ground connection of the 4th resistance；Second current source, input terminal is as voltage
The output terminal of comparator, output terminal ground connection；Third MOS transistor, the first connecting pin are connected with power end, the second connection
End is connected with the input terminal of the second current source, and grid is connected with the collector of the second bipolar transistor.Wherein described electric current
Mirror circuit includes the first MOS transistor, the second MOS transistor, first resistor, second resistance, the first adjustable resistance, second adjustable
Resistance, switching circuit and calibration circuit, one end of the first resistor are connected with power end, the other end and the first MOS
First connecting pin of transistor is connected, the second connection end of first MOS transistor and one end of first adjustable resistance
It is connected, the other end of first adjustable resistance is connected with one end of second adjustable resistance, second adjustable resistance
First output terminal of the other end as the current mirroring circuit；The control terminal of first MOS transistor and the first adjustable resistance
And the second connecting node between adjustable resistance is connected；One end of the second resistance is connected with the power end, the other end
It is connected with the first connecting pin of second MOS transistor, the second connection end of second MOS transistor is as the electric current
The second output terminal of mirror circuit, the switching circuit include first switch, second switch and third switch, the first switch
One end is connected with the control terminal of the second MOS transistor, the company between the other end and the first adjustable resistance and the second adjustable resistance
Node is connect to be connected；The second switch be connected to the second MOS transistor control terminal and first adjustable resistance one end it
Between, third switch is connected between the control terminal of the second MOS transistor and the other end of the second adjustable resistance, the calibration circuit
It is defeated including first input end, the second input terminal, the first output terminal, second output terminal, third output terminal, the 4th output terminal and the 5th
Outlet, wherein, the first input end of the calibration circuit is connected with the other end of the first resistor, the second input terminal and institute
The other end for stating second resistance is connected, and the first output terminal is connected with the control terminal of first switch, second output terminal and second
The control terminal of switch is connected, and third output terminal is connected with the control terminal that third switchs, the 4th output terminal and the first adjustable electric
The adjustable side of resistance is connected, and the 5th output terminal is connected with the adjustable side of the second adjustable resistance.
Further, the calibration circuit first controls the switching circuit to be in first state, so that first switch is led
Logical, second switch and third switch OFF；At this point, it is described calibration circuit sampling described in first resistor the other end voltage with
To the first sampled voltage, the voltage of the other end of the second resistance is sampled to obtain the second sampled voltage；The calibration circuit
Compare the first sampled voltage and the second sampled voltage, it is described when first sampled voltage is more than second sampled voltage
Difference of the circuit based on the first sampled voltage and the second sampled voltage is calibrated, by the 4th output terminal by the first adjustable resistance
Effective resistance value be adjusted to first effective resistance value, and the calibration circuit controling switch circuit is in the second state so that the
Two switch conductions, first switch and third switch OFF；When first sampled voltage is less than second sampled voltage, institute
Calibration difference of the circuit based on the second sampled voltage and the first sampled voltage is stated, by the 5th output terminal by the second adjustable electric
The effective resistance value of resistance is adjusted to second effective resistance value, and the calibration circuit controling switch circuit is in the third state, so that
Third switch conduction, first switch and second switch shutdown.
Further, first MOS transistor and the matching setting of the second MOS transistor, the first resistor and second
Resistors match set, and the resistance value of first resistor be equal to second resistance resistance value, the liner body end of first MOS transistor with
Power end is connected, and the liner body end of second MOS transistor is connected with power end.
Further, the calibration circuit includes the first analog-digital converter, the second analog-digital converter and processor, and described the
One analog-digital converter is used to sample the voltage of the first resistor other end, to obtain the first sampled voltage of analog signal, and
It is converted into the first sampled voltage of digital signal；Second analog-digital converter is used to sample the second resistance other end
Voltage, to obtain the second sampled voltage of analog signal, and be converted into the second sampled voltage of digital signal；The place
Reason device compares the first sampled voltage of digital signal and the second sampled voltage of digital signal, and first when the digital signal is adopted
Sample voltage be more than the digital signal the second sampled voltage when, first sampled voltage of the processor based on digital signal and
The effective resistance value of first adjustable resistance is adjusted to first effective resistance value by the difference of the second sampled voltage of the digital signal,
And the processor control switching circuit is in the second state；When the first sampled voltage of the digital signal is less than the number
During the second sampled voltage of signal, second sampled voltage and the digital signal of the processor based on the digital signal
The effective resistance value of second adjustable resistance is adjusted to second effective resistance value, and the processor control by the difference of the first sampled voltage
Switching circuit processed is in the third state.
Further, when the first sampled voltage of the digital signal is more than the second sampled voltage of the digital signal
When, the processor calculates the first adjustable resistance according to formula (1) needs first effective resistance value R3' being adjusted to,
The processor generates corresponding first Regulate signal according to be calculated first effective resistance value R3', with control
Effective resistance value of first adjustable resistance is equal to first effective resistance value；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processing
Device calculates the second adjustable resistance according to formula (2) needs second effective resistance value R4' being adjusted to,
The processor generates corresponding second Regulate signal according to be calculated second effective resistance value R4', with control
Effective resistance value of second adjustable resistance is equal to second effective resistance value；Wherein, wherein DV2 is the second sampling electricity of the digital signal
Pressure, the first sampled voltage of digital signal described in DV1, Vs is the quantization voltage steps of the analog-digital converter, and R is first resistor
The resistance value of R1 or second resistance R2, I are the current value of current source I1, and gm is the mutual conductance of the first MOS transistor.
Further, the first MOS transistor MP1 and the second MOS transistor MP2 is PMOS transistors,
The first connecting pin, second connection end and the control terminal of first MOS transistor MP1 is respectively the source of PMOS transistor
Pole, drain and gate；The first connecting pin, second connection end and the control terminal of second MOS transistor MP2 is respectively PMOS transistor
Source electrode, drain and gate.
Compared with prior art, the voltage comparator in the present invention employs improved current mirroring circuit, the current mirror
Calibration circuit is provided in circuit, the mismatch of mirror currents duplication can be reduced, improves the accuracy of repetition of current mirror, and then
Improve the precision of the internal reference voltage threshold of voltage comparator.
【Description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these attached drawings other
Attached drawing.Wherein：
Fig. 1 is a kind of circuit diagram of current mirror of the prior art；
Fig. 2 is the circuit diagram of the current mirroring circuit of the present invention in one embodiment；
Fig. 3 is the circuit diagram of the voltage comparator of the present invention in one embodiment.
【Specific embodiment】
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one realization method of the present invention
A particular feature, structure, or characteristic." in one embodiment " that different places occur in the present specification not refers both to same
A embodiment, nor the individual or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected word represent directly or indirectly to be electrical connected.
Shown in please referring to Fig.2, the circuit diagram for the improved current mirroring circuit of the present invention in one embodiment.
It is brilliant that current mirroring circuit shown in Fig. 2 includes the first MOS (metal oxide semiconductor) transistor MP1, the 2nd MOS
Body pipe MP2, first resistor R1, second resistance R2, the first adjustable resistance R3, the second adjustable resistance R4, switching circuit 210 and calibration
Circuit 220.
One end of the first resistor R1 is connected with power end VIN, and the other end is with the first MOS transistor MP1's
First connecting pin is connected, the second connection end of the first MOS transistor MP1 and one end phase of the first adjustable resistance R3
Even, the other end of the first adjustable resistance R3 is connected with one end of the second adjustable resistance R4, second adjustable resistance
The other end of R4 is connected as the first output terminal of current mirroring circuit with the input terminal of current source I1, the output of the current source I1
End ground connection；Company between the control terminal of the first MOS transistors MP1 and the first adjustable resistance R3 and the second adjustable resistance R4
Node is connect to be connected；One end of the second resistance R2 is connected with the power end VIN, the other end and the 2nd MOS crystal
The first connecting pin of pipe MP2 is connected, the second connection end of the second MOS transistor MP2 as the current mirroring circuit
Two output terminal Io.
The switching circuit 210 includes first switch S0, second switch S1 and third switch S2, the first switch S0's
One end is connected with the control terminal of the second MOS transistor MP2, the other end and the first adjustable resistance R3 and the second adjustable resistance R4 it
Between connecting node be connected.The second switch S1 is connected to the control terminal of the second MOS transistor MP2 and described first adjustable
Between one end of resistance R3.Third switch S2 is connected to the control terminal and the second adjustable resistance R4 of the second MOS transistor MP2
Between the other end.
The calibration circuit 220 includes first input end V1, the second input terminal V2, the first output terminal C0, second output terminal
C1, third output terminal C2, the 4th output terminal D1 and the 5th output terminal D2, wherein, the first input end V1 of the calibration circuit 220
It is connected with the other end of the first resistor R1, the second input terminal V2 is connected with the other end of the second resistance R2, the
One output terminal C0 is connected with the control terminal of first switch S0, and second output terminal C1 is connected with the control terminal of second switch S1,
Third output terminal C2 is connected with the control terminal of third switch S2, the adjustable side of the 4th output terminal D1 and the first adjustable resistance R3
It is connected, the 5th output terminal D2 is connected with the adjustable side of the second adjustable resistance R4.
In the embodiment shown in Figure 2, the first MOS transistor MP1 and the second MOS transistor MP2 matchings setting；
The first resistor R1 and second resistance R2 matching settings, and the resistance value of first resistor R1 and second resistance R2 are equal.In Fig. 2 institutes
In the specific embodiment shown, the first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistor, and described
The liner body end of one MOS transistor MP1 is connected with power end VIN, the liner body end of the second MOS transistor MP2 and power end
VIN is connected；The first connecting pin, second connection end and the control terminal of first MOS transistor MP1 is respectively the source of PMOS transistors
Pole, drain and gate；The first connecting pin, second connection end and the control terminal of second MOS transistor MP2 is respectively PMOS transistor
Source electrode, drain and gate.
It is understood that the effect of the first current source I1 in Fig. 2 is to provide a reference current for current mirroring circuit
I1, so that the current mirroring circuit can replicate reference current I1, therefore the first current source I1 can be it is any can
The circuit of electric current is provided.
The course of work of the switching circuit 210 and calibration circuit 220 in Fig. 2 is introduced in detail below.
The calibration circuit 220 first controls the switching circuit 210 to be in first state, so that first switch S0 is led
Logical, second switch S2 and third switch S3 shutdowns；At this point, the calibration circuit 220 samples the other end of the first resistor R1
Voltage to obtain the first sampled voltage V1, sample the voltage of the other end of the second resistance R2 to obtain the second sampling electricity
Press V2.When the first sampled voltage V1 is more than the second sampled voltage V2, the calibration circuit 220 passes through the described 4th
The effective resistance value of first adjustable resistance R3 is adjusted to first effective resistance value R3 ＇ by output terminal D1, and the calibration circuit 220 is controlled
Switching circuit 210 processed is in the second state, so that second switch S1 conductings, first switch S0 and third switch S2 shutdowns；When
When the first sampled voltage V1 is less than the second sampled voltage V2, the calibration circuit 220 passes through the 5th output terminal
The effective resistance value of second adjustable resistance R4 is adjusted to second effective resistance value R4 ＇, and the calibration circuit 220 control switch electricity by D2
Road 210 is in the third state, so that third switch S2 conductings, first switch S0 and second switch S1 shutdowns.
In specific embodiment shown in Fig. 2, the calibration circuit 220 includes the first analog-digital converter ADC1
(Analog-to-Digital Converter), the second analog-digital converter ADC2 and processor CPU (Central
Processing Unit, central processing unit).
The processor CPU first controls the switching circuit 210 to be in first state, for example, processor CPU controls the
One output terminal C0 exports high level, second output terminal C1 and third output terminal C2 output low levels is controlled, so that first switch
S0 conductings, second switch S2 and third switch S3 shutdowns.At this point, the first analog-digital converter ADC1 samples the first resistor
The voltage of the R1 other ends to obtain the first sampled voltage V1 of analog signal, and is converted into the first sampling of digital signal
Voltage DV1；The second analog-digital converter ADC2 samples the voltage of the second resistance R2 other ends, to obtain analog signal
Second sampled voltage V2, and it is converted into the second sampled voltage DV2 of digital signal.
The processor CPU compares the first sampled voltage DV1 of digital signal and the second sampled voltage of digital signal
DV2。
If the second sampled voltage DV2 of digital signal is larger, mean the second sampling of the analog signal sampled
Voltage V2 is more than the first sampled voltage V1 of analog signal, it is meant that the voltage drop on second resistance R2 is less than on first resistor R1
Voltage drop, show the leakage of electric current, i.e. the second MOS transistor MP2 that electric current on second resistance R2 is less than on first resistor R1
Electrode current value is less than the drain current value of the first MOS transistor MP1.The second of digital signal is calculated by the processor CPU
The difference (i.e. DV2-DV1) of sampled voltage DV2 and the first sampled voltage DV1 of digital signal, then according to following formula (2)
Calculating the effective resistance value R4'(that is adjusted to of the second adjustable resistance R4 needs, it can be described as second effective resistance value R4'):
Wherein DV2 is the second sampled voltage of the digital signal, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter (ADC1, ADC2), R is the resistance of first resistor R1 (or second resistance R2)
Value, I are the current value of current source I1, and gm is the mutual conductance of the second MOS transistor MP2.
The processor CPU generates corresponding second Regulate signal according to above-mentioned second effective resistance value R4' being calculated,
Second Regulate signal has by the 5th output terminal D2 effective resistance value of the second adjustable resistance R4 to be controlled to be equal to second
Imitate resistance value R4'.And the processor CPU control third output terminals C2 output high level, controls the first output terminal C0 and second
Output terminal C1 exports low level, so that third switch S2 conductings, first switch S0 and second switch S1 shutdowns.This is equivalent to
The gate source voltage of the second MOS transistor MP2 is increased, therefore, increases the drain current of the second MOS transistor MP2 so that
The drain current of MP2 closer to current source I1 current value, so as to improve the accuracy of repetition of current mirror.
If the first sampled voltage DV1 of digital signal is larger, mean the first sampling of the analog signal sampled
Voltage V1 is more than the second sampled voltage V2 of analog signal, it is meant that the voltage drop on first resistor R1 is less than on second resistance R2
Voltage drop, show the leakage of electric current, i.e. the second MOS transistor MP2 that electric current on first resistor R1 is less than on second resistance R2
Electrode current value is more than the drain current value of the first MOS transistor MP1, and the first of digital signal is calculated by the processor CPU
The difference (i.e. DV1-DV2) of sampled voltage DV1 and the second sampled voltage DV2 of digital signal, then according to following formula (1)
Calculating the effective resistance value R3'(that is adjusted to of the first adjustable resistance R3 needs, it can be described as first effective resistance value R3'):
Wherein DV2 is the second sampled voltage of the digital signal, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter (ADC1, ADC2), R is the resistance of first resistor R1 (or second resistance R2)
Value, I are the current value of current source I1, and gm is the mutual conductance of the second MOS transistor MP2.
The processor CPU generates corresponding first Regulate signal according to above-mentioned first effective resistance value R3' being calculated,
Effective resistance value that first Regulate signal controls the first adjustable resistance R3 by the 4th output terminal D1 is equal to first effectively
Resistance value R3'.And the processor CPU control second output terminals C1 output high level, controls the first output terminal C0 and third defeated
Outlet C2 exports low level, so that second switch S1 conductings, first switch S0 and third switch S2 shutdowns.This, which is equivalent to, subtracts
Therefore the small gate source voltage of second MOS transistor MP2, reduces the drain current of the second MOS transistor MP2 so that MP2's
Drain current closer to current source I1 current value, so as to improve the accuracy of repetition of current mirror.
Fig. 3 is the circuit diagram of the voltage comparator 300 of the present invention in one embodiment, wherein the voltage compares
Device 300 is the voltage comparator of internal reference voltage.As shown in Figure 3, the voltage comparator 300 includes current mirroring circuit
310th, the first bipolar transistor Q1, the second bipolar transistor Q2, the second current source I2,3rd resistor R12, the 4th resistance
R11, third MOS transistor MP3.The current mirroring circuit in Fig. 2 may be used in the current mirroring circuit 310.
The collector of first bipolar transistor Q1 is connected with the first output terminal of current mirroring circuit 310, emitter with
One end of 3rd resistor R12 is connected.The base stage of second bipolar transistor Q2 is connected with the base stage of the first bipolar transistor Q1,
Voltage input end as voltage comparator 300 later, collector are connected with the second output terminal of current mirroring circuit 310,
Emitter is connected with the other end of 3rd resistor R12 and one end of the 4th resistance R11, the other end ground connection of the 4th resistance R11.
Output terminal of the input terminal of second current source I2 as voltage comparator, the output terminal ground connection of the second current source I2.3rd MOS is brilliant
The first connecting pin of body pipe MP3 is connected with power end VIN, and second connection end is connected with the input terminal of the second current source I2,
Grid is connected with the collector of the second bipolar transistor Q2.
Wherein the first bipolar transistor Q1, the second bipolar transistor Q2 are bipolar npn transistor npn npn.3rd MOS
Transistor MP3 is PMOS transistor, and the first connecting pin is the source electrode of PMOS transistor, and second connection end is PMOS transistor
Drain electrode.
With reference to figure 3, the emitter area of Q1 and Q2 are usually designed as M:1, Q1 emitter area is larger, the two
The difference of Vbe (base-emitter voltage difference) is proportional to lnM, and M is positive number.Vbe2-Vbe1=(KT/q) .lnM, wherein M are Q1
The ratio between with the emitter area of Q2, K is Boltzmann constant, and T is temperature, and q is electron charge, and Vbe1 is the base emitter of Q1
Pole tension, Vbe2 are the base emitter voltage of Q2.At this point, the turnover voltage of voltage comparator is (or for internal reference voltage
Threshold value) be：Vbe2+(R11/R12).(Vbe2-Vbe1).This formula is ideal situation, if current mirroring circuit 310 exists partially
Difference then causes turnover voltage to deviate this design value, leads to inaccuracy.Mirror currents accuracy of repetition is improved, voltage can be improved
The precision of the turnover voltage of comparator.
In this embodiment, the part of the first bipolar transistor Q1 and 3rd resistor R12 is used for as in Fig. 2
First current source I1.
Voltage comparator 300 in the present invention employs improved current mirroring circuit, is provided in the current mirroring circuit
Circuit is calibrated, the mismatch of mirror currents duplication can be reduced, improves the accuracy of repetition of current mirror, and then improves voltage and compares
The precision of the internal reference voltage threshold of device.
In the present invention, the word that the expressions such as " connection ", connected, " company ", " connecing " are electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It should be pointed out that any change that one skilled in the art does the specific embodiment of the present invention
All without departing from the range of claims of the present invention.Correspondingly, the scope of the claims of the invention is also not merely limited to
In previous embodiment.
Claims (6)
1. a kind of voltage comparator, which is characterized in that it includes：
Current mirroring circuit, including the first MOS transistor, the second MOS transistor, first resistor, second resistance, the first adjustable electric
Resistance, the second adjustable resistance, switching circuit and calibration circuit, one end of the first resistor is connected with power end, the other end and
First connecting pin of first MOS transistor is connected, the second connection end of first MOS transistor and described first adjustable
One end of resistance is connected, and the other end of first adjustable resistance is connected with one end of second adjustable resistance, and described second
First output terminal of the other end of adjustable resistance as the current mirroring circuit；The control terminal of first MOS transistor and the
Connecting node between one adjustable resistance and the second adjustable resistance is connected；One end of the second resistance and the power end phase
Even, the other end is connected with the first connecting pin of second MOS transistor, the second connection end of second MOS transistor
As the second output terminal of the current mirroring circuit, the switching circuit includes first switch, second switch and third switch, institute
The one end for stating first switch is connected with the control terminal of the second MOS transistor, and the other end and the first adjustable resistance and second are adjustable
Connecting node between resistance is connected；The second switch is connected to the control terminal of the second MOS transistor and described first adjustable
Between one end of resistance, third switch is connected between the control terminal of the second MOS transistor and the other end of the second adjustable resistance,
The calibration circuit includes first input end, the second input terminal, the first output terminal, second output terminal, third output terminal, the 4th defeated
Outlet and the 5th output terminal, wherein, the first input end of the calibration circuit is connected with the other end of the first resistor, the
Two input terminals are connected with the other end of the second resistance, and the first output terminal is connected with the control terminal of first switch, and second
Output terminal is connected with the control terminal of second switch, and third output terminal is connected with the control terminal that third switchs, the 4th output terminal
It is connected with the adjustable side of the first adjustable resistance, the 5th output terminal is connected with the adjustable side of the second adjustable resistance；
3rd resistor；
4th resistance；
First bipolar transistor, collector are connected with the first output terminal of current mirroring circuit, emitter and 3rd resistor
One end be connected；
Second bipolar transistor, base stage are connected with the base stage of the first bipolar transistor, collector and current mirroring circuit
Second output terminal be connected, emitter is connected with the other end of 3rd resistor and one end of the 4th resistance, the 4th resistance it is another
One end is grounded；
Second current source, output terminal of the input terminal as voltage comparator, output terminal ground connection；
Third MOS transistor, the first connecting pin are connected with power end, second connection end and the input terminal phase of the second current source
Even, grid is connected with the collector of the second bipolar transistor.
2. voltage comparator according to claim 1, which is characterized in that
It is described calibration circuit the switching circuit is first controlled be in first state so that first switch be connected, second switch and
Third switch OFF；At this point, the voltage of the other end of first resistor is electric to obtain the first sampling described in the calibration circuit sampling
Pressure samples the voltage of the other end of the second resistance to obtain the second sampled voltage；
The calibration circuit compares the first sampled voltage and the second sampled voltage, when first sampled voltage is more than described second
During sampled voltage, the calibration difference of the circuit based on the first sampled voltage and the second sampled voltage passes through the described 4th output
The effective resistance value of first adjustable resistance is adjusted to first effective resistance value by end, and the calibration circuit controling switch circuit is in the
Two-state, so that second switch conducting, first switch and third switch OFF；When first sampled voltage is less than described the
During two sampled voltages, the calibration difference of the circuit based on the second sampled voltage and the first sampled voltage is defeated by the described 5th
The effective resistance value of second adjustable resistance is adjusted to second effective resistance value by outlet, and the calibration circuit controling switch circuit is in
The third state, so that third switch conduction, first switch and second switch shutdown.
3. voltage comparator according to claim 2, which is characterized in that
First MOS transistor and the matching setting of the second MOS transistor,
The first resistor and second resistance matching setting, and the resistance value of first resistor is equal to the resistance value of second resistance,
The liner body end of first MOS transistor is connected with power end, liner body end and the power end phase of second MOS transistor
Even.
4. voltage comparator according to claim 3, which is characterized in that
The calibration circuit includes the first analog-digital converter, the second analog-digital converter and processor,
First analog-digital converter is used to sample the voltage of the first resistor other end, is adopted with obtain analog signal first
Sample voltage, and it is converted into the first sampled voltage of digital signal；Second analog-digital converter is used to sample described second
The voltage of the resistance other end to obtain the second sampled voltage of analog signal, and is converted into the second sampling of digital signal
Voltage；
The processor compares the first sampled voltage of digital signal and the second sampled voltage of digital signal,
When the first sampled voltage of the digital signal is more than the second sampled voltage of the digital signal, the processor base
In the difference of the second sampled voltage of the first sampled voltage and digital signal of digital signal, by having for the first adjustable resistance
Effect resistance value is adjusted to first effective resistance value, and processor control switching circuit is in the second state；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processor base
In the difference of the first sampled voltage of the second sampled voltage and digital signal of the digital signal, by the second adjustable resistance
Effective resistance value be adjusted to second effective resistance value, and processor control switching circuit is in the third state.
5. voltage comparator according to claim 4, which is characterized in that
When the first sampled voltage of the digital signal is more than the second sampled voltage of the digital signal, the processor root
Calculating the first adjustable resistance according to formula (1) needs first effective resistance value R3' being adjusted to,
The processor generates corresponding first Regulate signal according to be calculated first effective resistance value R3', to control first
Effective resistance value of adjustable resistance is equal to first effective resistance value；
When the first sampled voltage of the digital signal is less than the second sampled voltage of the digital signal, the processor root
Calculating the second adjustable resistance according to formula (2) needs second effective resistance value R4' being adjusted to,
The processor generates corresponding second Regulate signal according to be calculated second effective resistance value R4', to control second
Effective resistance value of adjustable resistance is equal to second effective resistance value；
Wherein, wherein DV2 is the second sampled voltage of the digital signal, the first sampled voltage of digital signal described in DV1, Vs
It is the quantization voltage steps of the analog-digital converter, R is the resistance value of first resistor R1 or second resistance R2, and I is current mirror electricity
The current value of the first output terminal output on road, gm are the mutual conductance of the first MOS transistor.
6. voltage comparator according to claim 1, which is characterized in that
First MOS transistor and the second MOS transistor are PMOS transistor,
The first connecting pin, second connection end and the control terminal of first MOS transistor be respectively PMOS transistor source electrode, drain electrode and
Grid；
The first connecting pin, second connection end and the control terminal of second MOS transistor be respectively PMOS transistor source electrode, drain electrode and
Grid.
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