CN108120871B - Low offset voltage comparator - Google Patents

Low offset voltage comparator Download PDF

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CN108120871B
CN108120871B CN201711261484.5A CN201711261484A CN108120871B CN 108120871 B CN108120871 B CN 108120871B CN 201711261484 A CN201711261484 A CN 201711261484A CN 108120871 B CN108120871 B CN 108120871B
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resistor
mos tube
bipolar transistor
transistor
mos
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CN108120871A (en
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姜伟
田文博
王钊
王晓帅
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Hefei Sino Microelectronics Co Ltd
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    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold

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Abstract

The invention provides a low offset voltage comparator, which comprises: the third resistor and the fourth resistor are sequentially connected in series between the voltage input end and the grounding end; the third feedback resistor, the fourth MOS tube, the second bipolar transistor, the first resistor and the second resistor are sequentially connected between a power supply end and a ground end; the first feedback resistor, the first MOS tube and the first bipolar transistor are sequentially connected between a power supply end and a connecting node between the first resistor and the second resistor, and the control ends of the first bipolar transistor and the second bipolar transistor are connected with a connecting node between the third resistor and the fourth resistor; the second feedback resistor, the second MOS tube and the active load are sequentially connected between the power supply end and the grounding end, and the control end of the second MOS tube is connected with the second connecting end of the first MOS tube. Compared with the prior art, the invention can reduce the influence of the mismatch voltage on the switching threshold value by increasing the feedback resistor, thereby ensuring that the influence of the mismatch voltage on the switching threshold value is within an acceptable range.

Description

Low offset voltage comparator
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of electronic circuits, in particular to a low offset voltage comparator.
[ background of the invention ]
The battery protection circuit includes a voltage comparator and a current comparator. The voltage comparator is divided into an overcharge voltage comparator and an overdischarge voltage comparator. With the progress of lithium battery protection technology, the accuracy of an overcharge protection threshold (VOC) and an overdischarge protection threshold (VOD) is more and more required. Referring to fig. 1, a circuit diagram of an overcharge voltage comparator in the prior art is shown, in which the circuit structure of the overcharge voltage comparator is similar to that of the overcharge voltage comparator, and different overcharge protection thresholds VOC and VOD are generated by resistors Rd1 and Rd2 with different ratios.
In the actual production and processing of the chip, due to the influence of process deviation and post-package stress, the MOS transistors M4, M1, and M2 in fig. 1 are mismatched, random mismatch (equivalently, mismatch voltages Vos1 and Vos2) is introduced, and finally, the actual value of the charge protection threshold VOC deviates from the designed value. Simulation results show that Vos1 of +/-3mv causes VOC to deviate from the design value of +100/-96mv, which cannot be tolerated in high precision designs.
Therefore, there is a need to provide an improved solution to the above problems.
[ summary of the invention ]
It is an object of the present invention to provide a voltage comparator that can reduce the influence of a mismatch voltage Vos on a rollover threshold (e.g., an overcharge protection threshold VOC or an overdischarge protection threshold VOD) so that the influence of the mismatch voltage Vos on the rollover threshold is within an acceptable range.
In order to solve the above problem, the present invention provides a voltage comparator, which includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first feedback resistor, a second feedback resistor, a third feedback resistor, a first MOS transistor, a second MOS transistor, a fourth MOS transistor, a first bipolar transistor, a second bipolar transistor, and an active load. The third resistor and the fourth resistor are sequentially connected in series between the voltage input end and the grounding end, the third feedback resistor is connected between the power supply end and the first connection end of the fourth MOS tube, the control end of the fourth MOS tube is connected with the second connection end of the fourth MOS tube, the second connection end of the fourth MOS tube is connected with the first connection end of the second bipolar transistor, the control end of the second bipolar transistor is connected with a connection node between the third resistor and the fourth resistor, and the second connection end of the second bipolar transistor is grounded through the first resistor and the second resistor which are sequentially connected in series; the first feedback resistor is connected between a power supply end and a first connecting end of the first MOS tube, a control end of the first MOS tube is connected with a control end of the fourth MOS tube, a second connecting end of the first MOS tube is connected with a first connecting end of the first bipolar transistor, a control end of the first bipolar transistor is connected with a control end of the second bipolar transistor, and a second connecting end of the first bipolar transistor is connected with a connecting node between the first resistor and the second resistor; the second feedback resistor is connected between a power supply end VDD and a first connecting end of a second MOS tube, a control end of the second MOS tube is connected with a connecting node between the first MOS tube and the first bipolar transistor, and a second connecting end of the second MOS tube is connected with an output end of the voltage comparator; one end of the active load is connected with the output end of the voltage comparator, the other end of the active load is grounded, and the active load generates constant current flowing from the output end of the voltage comparator to the ground.
Furthermore, the first MOS transistor, the second MOS transistor and the fourth MOS transistor are all PMOS transistors, and the first connection end, the second connection end and the control end of the first MOS transistor, the second MOS transistor and the fourth MOS transistor are respectively a source electrode, a drain electrode and a gate electrode of the PMOS transistor.
Further, the first bipolar transistor and the second bipolar transistor are both NPN transistors, and the first connection end, the second connection end, and the control end of the first bipolar transistor and the second bipolar transistor are respectively a collector, an emitter, and a base of the NPN transistor.
Furthermore, the active load includes a third MOS transistor, a first connection end of the third MOS transistor is connected to the output end of the voltage comparator, a second connection end of the third MOS transistor is connected to ground, and a control end of the third MOS transistor is connected to the bias voltage.
Further, the third MOS transistor is an NMOS transistor, and the first connection end, the second connection end, and the control end of the third MOS transistor are a drain electrode, a source electrode, and a gate electrode of the NMOS transistor, respectively.
Compared with the prior art, the influence of the mismatch voltage Vos on the turnover threshold value can be reduced by adding the feedback resistor, so that the influence of the mismatch voltage Vos on the turnover threshold value is within an acceptable range.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a circuit diagram of a voltage comparator in the prior art;
FIG. 2 is a schematic diagram of an equivalent circuit of the voltage comparator shown in FIG. 1;
FIG. 3 is a circuit schematic of a voltage comparator according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an equivalent circuit of the voltage comparator shown in fig. 3.
[ detailed description ] embodiments
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.
Fig. 2 is a schematic diagram of an equivalent circuit of the voltage comparator shown in fig. 1. The voltage comparator may be used as an overcharge voltage comparator, where the voltage comparator is configured to invert the output signal when the detection terminal voltage VM is equal to the overcharge protection threshold VOC. The voltage comparator may be used as an over-discharge voltage comparator, when the voltage comparator is used to flip the output signal when the detection terminal voltage VM is equal to the over-discharge protection threshold VOD. The following description will be given taking the voltage comparator as an overcharge voltage comparator as an example, where the rollover threshold of the voltage comparator is the overcharge protection threshold VOC.
In fig. 2, the collector resistance of the bipolar transistor N1 is denoted as Rce, the drain resistances of the MOS transistors M1, M2 and M3 are denoted as Rds1, Rds2 and Rds3, respectively, the equivalent transconductances of the bipolar transistor N1, the MOS transistors M1, M2 and M3 are denoted as gm0, gm1, gm2 and gm3, respectively, wherein the transconductances of the bipolar transistor N1 itself are denoted as gmn, and there are:
Figure BDA0001493703230000031
the first stage output resistance Ro1 is:
Ro1=Rds1//Rce*(1+gmn*Re)
the second stage output resistance Ro2 is:
Ro2=Rds2//Rds3
the first stage gain Av1 is:
Figure BDA0001493703230000032
effect of equivalent mismatch voltage Vos1 on input voltage Vin:
Figure BDA0001493703230000041
effect of equivalent mismatch voltage Vos2 on input voltage Vin:
ΔVin2=Vos2/Av1。
as can be seen from fig. 1 and 2, the relationship between the overcharge protection threshold value VOC and the input voltage Vin is:
Vin=Voc*Rd2/(Rd1+Rd2)
where, Re is the equivalent resistance from the emitter of the bipolar transistor N1 to ground in fig. 1, Rd1 and Rd2 are the resistance values of the resistors Rd1 and Rd2 in fig. 1, respectively, Vos1 is the equivalent mismatch voltage Vos1 (or called as current mirror mismatch voltage) in fig. 2, Vos2 is the equivalent mismatch voltage Vos2 (or called as second stage mismatch voltage) in fig. 2, Vin is the input voltage of the base of the bipolar transistor N1 when the output of the voltage comparator in fig. 2 is inverted, and is in proportion to the charging protection threshold VOC, and Δ Vin is the variation of the input voltage Vin of the base, and corresponds to the variation of the charging protection threshold VOC.
In order to reduce the influence of the mismatch voltages Vos1 and Vos2 on the accuracy of the overcharge protection threshold VOC, the invention improves the prior overcharge voltage comparator.
Referring to fig. 3, a circuit diagram of an overcharge voltage comparator according to an embodiment of the invention is shown. The main difference between fig. 3 and fig. 1 is that fig. 3 adds a first degeneration resistor Rs1 connected between the power supply terminal VDD and the source of the MOS transistor M1, a second degeneration resistor Rs2 connected between the power supply terminal VDD and the source of the MOS transistor M2, and a third degeneration resistor Rs3 connected between the power supply terminal VDD and the source of the MOS transistor M3 to the overcharge voltage comparator shown in fig. 1.
The overcharge voltage comparator shown in fig. 3 includes a first resistor R1, a second resistor R2, a third resistor Rd1, a fourth resistor Rd2, a first feedback resistor Rs1, a second feedback resistor Rs2, a third feedback resistor Rs3, a first MOS transistor M1, a second MOS transistor M2, a fourth MOS transistor M4, a first bipolar transistor N1, a second bipolar transistor N2, and an active load 110. The third resistor Rd1 and the fourth resistor Rd2 are sequentially connected in series between the voltage input end VM and the ground end, the third feedback resistor Rs3 is connected between the power supply end VDD and the first connection end of the fourth MOS transistor M4, the control end of the fourth MOS transistor M4 is connected with the second connection end of the fourth MOS transistor M4, the second connection end of the fourth MOS transistor M4 is connected with the first connection end of the second bipolar transistor N2, the control end of the second bipolar transistor N2 is connected with a connection node between the third resistor Rd1 and the fourth resistor Rd2, and the second connection end of the second bipolar transistor N2 is grounded through the first resistor R1 and the second resistor R2 which are sequentially connected in series; the first feedback resistor Rs1 is connected between a power supply end VDD and a first connection end of a first MOS transistor M1, a control end of the first MOS transistor M1 is connected with a control end of a fourth MOS transistor M4, a second connection end of the first MOS transistor M1 is connected with a first connection end of a first bipolar transistor N1, a control end of the first bipolar transistor N1 is connected with a control end of a second bipolar transistor N2, and a second connection end of the first bipolar transistor N1 is connected with a connection node between a first resistor R1 and a second resistor R2; the second feedback resistor Rs2 is connected between a power supply terminal VDD and a first connection terminal of the second MOS transistor M2, a control terminal of the second MOS transistor M2 is connected with a connection node between the first MOS transistor M1 and the first bipolar transistor N1, and a second connection terminal of the second MOS transistor M2 is connected with an output terminal Vout of the voltage comparator; one end of the active load 110 is connected to the output terminal Vout of the voltage comparator, and the other end of the active load 110 is grounded.
In the specific embodiment shown in fig. 3, the active load 110 includes a third MOS transistor M3, a first connection terminal of the third MOS transistor M3 is connected to the output terminal Vout of the voltage comparator, a second connection terminal thereof is connected to ground, and a control terminal thereof is connected to the bias voltage Vbias, so that the active load 110 generates a constant current Ibias flowing from the output terminal Vout to ground; the third MOS transistor M3 is an NMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor M3 are a drain, a source and a gate of the NMOS transistor, respectively; the MOS transistors M1, M2 and M4 are all POS transistors, and the first connection end, the second connection end and the control end of each of the MOS transistors M1, M2 and M4 are respectively a source electrode, a drain electrode and a grid electrode of a PMOS transistor; the bipolar transistors N1 and N2 are both NPN transistors, and the first connection end, the second connection end, and the control end of the bipolar transistors N1 and N2 are the collector, the emitter, and the base of the NPN transistor, respectively.
Fig. 4 is a schematic diagram of an equivalent circuit of the overcharge voltage comparator shown in fig. 3. The main differences between fig. 4 and fig. 2 are: fig. 4 is an equivalent circuit of the overcharge voltage comparator shown in fig. 2, in which a first degeneration resistor Rs1 connected between a power supply terminal VDD and the source of the MOS transistor M1 and a second degeneration resistor Rs2 connected between the power supply terminal VDD and the source of the MOS transistor M2 are added.
Due to the mismatch of the MOS transistors M1, M2, and M4 in fig. 3, equivalent mismatch voltages Vos1 and Vos1 are generated, which belong to parasitic voltage sources. In fig. 4, the anode of the equivalent mismatch voltage Vos1 is connected to the control terminal of the first MOS transistor M1, and the cathode thereof is grounded; the anode of the equivalent mismatch voltage Vos2 is connected to the connection node between the first MOS transistor M1 and the first bipolar transistor N1, and the cathode thereof is connected to the control terminal of the second MOS transistor M2. In other embodiments, the cathode of the equivalent mismatch voltage Vos1 may be connected to the control terminal of the first MOS transistor M1, and the anode thereof is grounded; the cathode of the equivalent mismatch voltage Vos2 is connected to the connection node between the first MOS transistor M1 and the first bipolar transistor N1, and the anode thereof is connected to the control terminal of the second MOS transistor M2. This is mainly determined by the specifics of the device mismatch.
The analysis is performed below with respect to fig. 4.
With the addition of the first degeneration resistor Rs1, the equivalent transconductance gm 1' of the MOS transistor M1 is:
Figure BDA0001493703230000061
the equivalent transconductance gm 0' of the bipolar transistor N1 is:
gm0′=gm0,
the first stage output resistance Ro 1' is:
Ro1′=Rds1(1+gm1*Rs1)//Rce*(1+gmn*Re)
the second stage output resistance Ro 2' is:
Ro2′=Rds2(1+gm2*Rs2)//Rds3
the first stage gain Av 1' is:
Figure BDA0001493703230000062
effect of equivalent mismatch voltage Vos1 on input voltage Vin:
Figure BDA0001493703230000063
in this way it is possible to obtain,
Figure BDA0001493703230000064
that is, the influence of Vos1 on the input voltage Vin becomes original
Figure BDA0001493703230000065
Effect of equivalent mismatch voltage Vos2 on input voltage Vin:
ΔVin2′=Vos2/Av1′,
since Ro 1' > Ro1, the first stage gain becomes large and the effect of the equivalent mismatch voltage Vos2 on the input voltage Vin is also reduced.
The performance comparison before and after improvement.
Table 1: analysis of VOC value before and after improvement influenced by Vos1
Figure BDA0001493703230000066
Figure BDA0001493703230000071
The Delta Voc column refers to the difference between the mismatch (Vos1 ═ +/-3mv) versus the Voc without mismatch.
As can be seen from the above table, without Rs1, a Vos1 of +/-3mv causes the VOC value to deviate from the design value of +100/-96 mv; increasing Rs1, Vos1 caused VOC deviation values to become smaller, and the larger Rs1, the smaller 1/(1+ gm1 Rs1), the smaller the effect of Vos1 on VOC; when Rs1 is 300k, +/-3mv of Vos1 causes VOC deviations from the design value of only +7/-8 mv.
Table 2: analysis of VOC value before and after improvement influenced by Vos2
Figure BDA0001493703230000072
The Delta Voc column refers to the difference between the mismatch (Vos2 ═ 100mv) versus the Voc without mismatch.
As can be seen from the above table, the VOC deviation caused by Vos2 becomes smaller when Rs1 is increased. It can also be concluded from Table 1 that the effect of Vos2 on VOC is much less than the effect of Vos1 on VOC, since the effect of Vos2 on VOC is divided by the first stage gain.
Compared with the prior art, the voltage comparator has the advantages that:
reducing the effect of the current mirror mismatch Vos1 on the overcharge protection threshold VOC (or the overdischarge protection threshold VOD);
increasing the first stage comparator gain, decreasing the second stage mismatch Vos2 versus the overcharge protection threshold VOC (or over-discharge protection threshold VOD);
the influence of random mismatch on the overcharge protection threshold value VOC (or the overdischarge protection threshold value VOD) is reduced with a relatively small cost (only the source degeneration resistance Rs is increased), and the effect is relatively remarkable.
In the present invention, the terms "connected", connected, "connecting," and "connecting" mean electrically connected, and if not specifically stated, directly or indirectly indicate electrically connected.
It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.

Claims (5)

1. A voltage comparator is characterized in that the voltage comparator comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first feedback resistor, a second feedback resistor, a third feedback resistor, a first MOS (metal oxide semiconductor) transistor, a second MOS transistor, a fourth MOS transistor, a first bipolar transistor, a second bipolar transistor and an active load,
the third resistor and the fourth resistor are sequentially connected in series between the voltage input end and the grounding end, the third feedback resistor is connected between the power supply end and the first connection end of the fourth MOS tube, the control end of the fourth MOS tube is connected with the second connection end of the fourth MOS tube, the second connection end of the fourth MOS tube is connected with the first connection end of the second bipolar transistor, the control end of the second bipolar transistor is connected with a connection node between the third resistor and the fourth resistor, and the second connection end of the second bipolar transistor is grounded through the first resistor and the second resistor which are sequentially connected in series;
the first feedback resistor is connected between a power supply end and a first connecting end of the first MOS tube, a control end of the first MOS tube is connected with a control end of the fourth MOS tube, a second connecting end of the first MOS tube is connected with a first connecting end of the first bipolar transistor, a control end of the first bipolar transistor is connected with a control end of the second bipolar transistor, and a second connecting end of the first bipolar transistor is connected with a connecting node between the first resistor and the second resistor;
the second feedback resistor is connected between a power supply end and a first connecting end of a second MOS tube, a control end of the second MOS tube is connected with a connecting node between the first MOS tube and the first bipolar transistor, and a second connecting end of the second MOS tube is connected with an output end of the voltage comparator;
one end of the active load is connected with the output end of the voltage comparator, the other end of the active load is grounded, and the active load generates constant current flowing from the output end of the voltage comparator to the ground.
2. The voltage comparator as claimed in claim 1,
the first MOS tube, the second MOS tube and the fourth MOS tube are all PMOS transistors, and the first connecting end, the second connecting end and the control end of the first MOS tube, the second MOS tube and the fourth MOS tube are respectively a source electrode, a drain electrode and a grid electrode of the PMOS transistors.
3. The voltage comparator as claimed in claim 2,
the first bipolar transistor and the second bipolar transistor are both NPN transistors, and the first connecting end, the second connecting end and the control end of the first bipolar transistor and the second bipolar transistor are respectively a collector electrode, an emitter electrode and a base electrode of the NPN transistors.
4. The voltage comparator as claimed in claim 1, wherein the active load comprises a third MOS transistor, a first connection terminal of the third MOS transistor is connected to the output terminal of the voltage comparator, a second connection terminal of the third MOS transistor is connected to ground, and a control terminal of the third MOS transistor is connected to the bias voltage.
5. The voltage comparator as claimed in claim 4,
the third MOS transistor is an NMOS transistor, and the first connecting end, the second connecting end and the control end of the third MOS transistor are respectively a drain electrode, a source electrode and a grid electrode of the NMOS transistor.
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