CN100580606C - Band-gap reference circuit - Google Patents

Abstract

The invention discloses a belt difference reference circuit which comprises an input circuit with two end points, a mirror image circuit which can control two output currents of two end points and maintains the invariable current proportion between the two output currents and a calculation amplifier which is connected with the two end points and the mirror image circuit to control the mirror image circuit so that the voltage between the two end points has voltage relation; wherein a first end point is connected with a first field effect transistor with a first critical voltage; a first resistance is connected between a second end point and a second field effect transistor with a second critical voltage; the first field effect transistor and the second field effect transistor are both operated in sub critical area; the first critical voltage is huger than the second critical voltage; the two output currents don't vary with the variable temperature.

Description

The band gap reference circuit

Technical field

The present invention relates to a kind of band gap reference circuit (Bandgap Reference Circuit), and be particularly related to a kind of band gap reference circuit of low operating voltage.

Background technology

As everyone knows, the function of band gap reference circuit provides a reference voltage (Vref) stable, that can not change along with technology, temperature, supply voltage, therefore, in the field of hybrid circuit, be designed in many circuit widely, for example, voltage adjuster (Voltage Regulator), digital revolving die are intended circuit and low drift amplifier (Low Drift Amplifier).

Please refer to Fig. 1, it is depicted as the known band gap reference circuit synoptic diagram of forming by pmos fet, PNP bipolar transistor, with operational amplifier.In general, the band gap reference circuit comprises mirror image circuit (Mirroring Circuit) 12, operational amplifier (Operation Amplifier) 15 and input circuit 20.Comprise three pmos fets (FET) M1, M2, M3 in the mirror image circuit 12, in this example, M1, M2, M3 have identical length breadth ratio (W/L).Wherein, the grid of M1, M2 and M3 interconnects, and the source electrode of M1, M2 and M3 is connected to power supply (Vss), and the drain electrode of M1, M2 and M3 can be exported the electric current of Ix, Iy and Iz respectively.In addition, the output terminal of operational amplifier 15 can be connected to the grid of M1, M2 and M3, and the electrode input end of operational amplifier 15 is connected to the drain electrode of M2, and the negative input of operational amplifier 15 is connected to the drain electrode of M1.Moreover input circuit 20 comprises two PNP bipolar transistors (BJT) Q1, Q2; Wherein, the Q1 area is m a times of Q2 area, Q1 is connected to earth terminal with the base stage of Q2 with the collection utmost point makes Q1 and Q2 formation diode be connected (Diode Connect), the emitter-base bandgap grading of Q2 is connected to the negative input of operational amplifier 15, is connected first resistance (R1) between the electrode input end of the emitter-base bandgap grading of Q1 and operational amplifier 15.Moreover PNP bipolar transistor (BJT) Q3 area is identical with the Q2 area, and the base stage of Q3 is connected to earth terminal with the collection utmost point, and the emitter-base bandgap grading of Q3 and M3 are connected second resistance (R2) between draining, the M3 exportable reference voltage (Vref) that drains.

By band gap reference circuit shown in Figure 1 as can be known.Because M1, M2, M3 have identical length breadth ratio, therefore, the output current Iy of output current Ix, the M2 drain electrode of M1 drain electrode is identical with the output current Iz of M3 drain electrode, just, and I _x=I _y=I _z---(1).

Moreover, having under the infinitely-great gain at operational amplifier 15, the negative input voltage (Vx) of operational amplifier 15 can equate with electrode input end voltage (Vy).Therefore, R ₁I _y+ V _EB1=V _EB2---(2).

To be connected (Diode Connect) and Q1 area be m times of Q2 area because Q1 and Q2 form diode, so, $I_x=I_s{e}^{\frac{V_{\mathrm{EB}2}}{V_T}}$ With $I_y=m{I}_s{e}^{\frac{V_{\mathrm{EB}1}}{V_T}},$ And then derive V _BE1=V _TLn (I _y/ mI _s)---(3) and V _BE2=V _TLn (I _x/ I _s)---(4).Wherein, I _sBe the saturation current (Saturation Current) of Q2, V _TBe thermal voltage (Thermal Voltage).

In conjunction with (1), (2), (3), (4), finally can obtain I _y=(1/R ₁) V _TLn m---(5), and, reference voltage V _Ref=(R ₂/ R ₁) V _TLn m+V _EB3---(6).

Please refer to Fig. 2 A, reference voltage synoptic diagram that provides in band gap reference circuit is provided for it.According to equation (6) as can be known, reference voltage (Vref) can be considered a base and penetrates voltage generator (base-emittervoltage generator) 32 and press (V in order to the basic radio between base stage that the PNP bipolar transistor is provided and the emitter-base bandgap grading _BE) add thermal voltage (V _T) generator (thermal voltage generator) 34 generation thermal voltage (V _T) multiply by the result of temperature independent constant K (temperature-independent scalar) 36.Just, Vref=V _BE+ KV _T, compared to the band gap reference circuit of Fig. 1, K=(R ₂/ R ₁) lnm.

Please refer to Fig. 2 B, it is depicted as reference voltage (Vref) and temperature relation figure.By among the figure as can be known, base is penetrated the basic radio of voltage generator 32 and is pressed (V _BE) have the characteristic of negative temperature coefficient (negative temperaturecoefficient), on the contrary, the thermal voltage (V of thermal voltage generator 34 _T) have the characteristic of positive temperature coefficient (PTC) (positive temperature coefficient).Therefore, in thermal voltage (V _T) weight of fixed coefficient (K) is provided and presses (V with basic radio _BE) can obtain any value of zero-temperature coefficient (zero temperaturecoefficient) after the addition.That is to say that reference voltage under the arbitrary temp (Vref) can be almost a definite value.

In general, the forward bias voltage drop of bipolar transistor (forward-voltage drop) is about 0.83V in-40 ℃, and power supply (Vss) to the bias voltage of the mirror image circuit between the input circuit 20 12 and operational amplifier 15 needs 0.17V at least.That is to say,, need the supply voltage (Vss) of 1V (0.83V+0.17V) at least in order to make the band gap reference circuit normal operation of Fig. 1.That is to say that known band gap reference circuit needs the operating voltage of 1V at least.

Yet, since the differentiation of semiconductor technology by early stage 0.13 μ m technology evolution to 90nm technology, 60nm technology, following 45nm, 30nm technology even, therefore, the operating voltage of analog IC chip also must be along with technology is progressive more and more and more lower.Yet low excessively operating voltage will impact the normal operation of known band gap reference circuit.

In order to solve the problem of known band gap reference circuit higher operation voltage, in the input circuit 20 of band gap reference circuit, replace bipolar transistor, in order to reduce the operating voltage of band gap reference circuit with the lower schottky diode of forward bias voltage drop (Schottky Diode).Perhaps, utilize metal oxide half (dynamic threshold MOS the is called for short DT MOS) field effect transistor of dynamic critical voltage to replace bipolar transistor, also can reduce the operating voltage of band gap reference circuit.

Yet, the technology of schottky diode or DT MOS is not compatible with the semiconductor technology of general standard, so must increase special processing step in addition in standard technology and provide the required light shield of this special process can finish schottky diode or DT MOS.So, produce the required cost of chip with increasing.

Please refer to Fig. 3 A, it is depicted as the drain current root of mos field effect transistor

With gate source voltage (V _GS) between graph of a relation.In general, as the gate source voltage (V of mos field effect transistor _GS) less than voltage (V _ON) time, can be considered mos field effect transistor and operate in subcritical district (subthreshold region), or be referred to as weak inversion regime (weakinversion region), otherwise, as the gate source voltage (V of mos field effect transistor _GS) greater than cut-in voltage (V _ON) time, can be considered mos field effect transistor and operate in strong inversion district (strong inversion region).Please refer to Fig. 3 B, it is depicted as the drain current logarithm value (log (I of mos field effect transistor _D)) and gate source voltage (V _GS) between graph of a relation.By Fig. 3 B as can be known, when subcritical district, the logarithm value of drain current (log (I _D)) and gate source voltage (V _GS) between be linear relationship, that is to say that when mos field effect transistor was operated in subcritical district, the property class of mos field effect transistor was similar to diode.

Therefore, in order to make all component of band in the gap reference circuit all be compatible with the semiconductor technology of general standard, the mos field effect transistor that known utilization is general replaces the bipolar transistor in the input circuit 20, and mos field effect transistor operated in subcritical district, make mos field effect transistor in the property class in subcritical district like general diode, in order to reduce the operating voltage of band gap reference circuit output.

When metal-oxide semiconductor (MOS) (MOS) field effect transistor faces when operation limit district inferior, $I_D\≅I_{D0}\left(\frac{W}{L}\right)\exp \left(\frac{V_{\mathrm{GS}}}{\mathrm{\ξ}\·V_T}\right).$ Wherein, I _D0Be technology interdependent parameter (process-dependentparameter), V _TFor thermal voltage (thermal voltage) and $(V_T=\frac{\mathrm{kT}}{q}),$ ξ is that the numerical value of imperfect parameter (non-ideality factor) and ξ is between 1～3.

Please refer to Fig. 4, it is depicted as the known band gap reference circuit synoptic diagram of being made up of pmos fet, nmos fet and operational amplifier.The band gap reference circuit comprises mirror image circuit 42, operational amplifier 45 and input circuit 50.Comprise three pmos fet M1, M2, M3 in the mirror image circuit 42, in this example, M1, M2, M3 have identical length breadth ratio (W/L).Wherein, the grid of M1, M2 and M3 interconnects, and the source electrode of M1, M2 and M3 is connected to power supply (Vss), and the drain electrode of M1, M2 and M3 can be exported the electric current of Ix, Iy and Iz respectively.In addition, the output terminal of operational amplifier 45 can be connected to the grid of M1, M2 and M3, and the negative input of operational amplifier 45 is connected to the drain electrode of M1, and the electrode input end of operational amplifier 45 is connected to the drain electrode of M2.Moreover input circuit 50 comprises two nmos fet M4, M5; Wherein, the length breadth ratio of M4 is n a times of M5 length breadth ratio, M4 is connected with drain electrode with the grid of M5, the source electrode of M4 and M5 is connected to earth terminal, moreover, the drain electrode of M5 is connected to the negative input of operational amplifier 45, is connected first resistance (R1) between the electrode input end of the drain electrode of M4 and operational amplifier 45.Moreover the length breadth ratio of nmos fet M6 is identical with the length breadth ratio of M5, and grid and the drain electrode of M6 interconnect, and the source electrode of M6 is connected to earth terminal, is connected second resistance (R2) between the drain electrode of M6 and the M3 drain electrode, the M3 exportable reference voltage (Vref) that drains.

By band gap reference circuit shown in Figure 4 as can be known.Because M1, M2, M3 have identical length breadth ratio, therefore, the output current Iy of output current Ix, the M2 drain electrode of M1 drain electrode is identical with the output current Iz of M3 drain electrode, just, and I _x=I _y=I _z---(7).

Moreover, having under the infinitely-great gain at operational amplifier 45, the negative input voltage (Vx) of operational amplifier 45 can equate with electrode input end voltage (Vy).Therefore, R ₁I _y+ V _GS5=V _GS4---(8).

The length breadth ratio that operates in subcritical when district and M4 when pmos fet be the M5 length breadth ratio n doubly, so, $I_x=I_{D0}\left(\frac{W}{L}\right)\exp \left(\frac{V_{\mathrm{GS}5}}{\mathrm{\ξ}\·V_T}\right)$ With $I_y=I_{D0}\left(\frac{\mathrm{nW}}{L}\right)\exp \left(\frac{V_{\mathrm{GS}4}}{\mathrm{\ξ}\·V_T}\right),$ And then derive $V_{\mathrm{GS}5}=\mathrm{\ξ}\·V_T\ln \left[\frac{I_x}{I_{D0}(W/L)}\right]---\left(9\right)$ With $V_{\mathrm{GS}4}=\mathrm{\ξ}\·V_T\ln \left[\frac{I_y}{I_{D0}(\mathrm{nW}/L)}\right]---\left(10\right).$

In conjunction with (7), (8), (9), (10), finally can obtain I _y=(ξ V _T/ R ₁) ln (n)---(11), and, reference voltage V _Ref=(R ₂/ R ₁) ξ V _TLn (n)+V _GS6---(12).That is to say that according to equation (12) as can be known, reference voltage (Vref) can be considered combining by the thermal voltage generator of positive temperature coefficient (PTC) and the gate source voltage generator of a negative temperature coefficient (gate-source voltage generator).Therefore, reference voltage (Vref) almost can be a definite value under arbitrary temp.

Moreover, according to periodical IEEE J.Solid-State Circuits, vol.38, no.1, pp.151-154,2003 and periodical Integrated Circuit Design and Technology, 2006.ICICDT apos; 06.2006IEEE International Conference on Volume, Issue, 24-26May 2006Page (s): 1-4 as can be known, mos field effect transistor in the critical voltage model (Modeling the threshold voltage) that subcritical district the time is set up is: $V_{\mathrm{TH}}\≅V_{\mathrm{TH}}\left(T_0\right)+K_T(\frac{T}{T_0}-1)---\left(13\right),$ K wherein _T＜0.

Moreover, gate source voltage (V _GS), critical voltage (V _TH) and temperature between the pass be $V_{\mathrm{GS}}\left(T\right)\≅V_{\mathrm{TH}}\left(T\right)+V_{\mathrm{OFF}}+[V_{\mathrm{GS}}\left(T_0\right)-V_{\mathrm{TH}}\left(T_0\right)-V_{\mathrm{OFF}}]\frac{T}{T_0}---\left(14\right),$ Wherein, V _OFFCan be considered the meter constant item (corrective constant term) of critical voltage between weak inversion regime and strong inversion district.And can obtain in conjunction with equation (13) and (14): $V_{\mathrm{GS}}\left(T\right)\≅V_{\mathrm{GS}}\left(T_0\right)+K_G(\frac{T}{T_0}-1)---\left(15\right),$ Wherein, K _G＜0 and $K_G\≅K_T+V_{\mathrm{GS}}\left(T_0\right)-V_{\mathrm{TH}}\left(T_0\right)-V_{\mathrm{OFF}}$ 。By equation (13), (15) as can be known, gate source voltage (V _GS) and critical voltage (V _TH) all have a characteristic of negative temperature coefficient, and by equation (14) gate source voltage (V as can be known _GS) be critical voltage (V _TH) with the function of temperature.

Though the technology of the band gap reference circuit of Fig. 4 can meet semi-conductive standard technology, yet, therefore cause the difference of the critical voltage of mos field effect transistor owing to the characterisitic parameter of mos field effect transistor can change along with the skew (deviation) of semiconductor technology.For instance, under identical semiconductor technology, the extreme situation of technology can be divided into transistor area " slow process corner (slow corner; S corner) " transistor, " fast process corner (fast corner; Fcorner) " transistor and " typical process corner (typical corner, T corner) " transistor.So-called " slow process corner " transistor is promptly represented the first transistor that utilizes in a plurality of transistors that semiconductor technology finishes, and this first transistor has the drive strength performance (drive strength performance) of the most weak (weakest), the slowest (slowest).Moreover so-called " fast process corner " transistor is promptly represented the transistor seconds that utilizes in a plurality of transistors that this semiconductor technology finishes, and this transistor seconds has the drive strength performance of the strongest (strongest), the fastest (fastest).So-called " typical process corner " transistor is promptly represented the transistor that has the performance of driven intensity in a plurality of transistors that utilize this semiconductor technology to finish.

Please refer to Fig. 5 A, its illustrate is the relation between " slow process corner ", " fast process corner ", " typical process corner " transistorized critical voltage and the temperature under the standard semiconductor technology.By among the figure as can be known, in the time of-20 ℃, the slow transistorized critical voltage (V of process corner _TH) be about 625mV, along with the rising of temperature, in the time of 100 ℃, the slow transistorized critical voltage (V of process corner _TH) be about 525mV; In the time of-20 ℃, the transistorized critical voltage (V in typical process corner _TH) be about 520mV, along with the rising of temperature, in the time of 100 ℃, the transistorized critical voltage (V in typical process corner _TH) be about 425mV; In the time of-20 ℃, the fast transistorized critical voltage (V of process corner _TH) be about 420mV, along with the rising of temperature, in the time of 100 ℃, the fast transistorized critical voltage (V of process corner _TH) be about 325mV.

By equation (14) as can be known, gate source voltage (V _GS) be critical voltage (V _TH) with the function of temperature.Therefore, utilize identical technology to produce the result that band gap reference circuit shown in Figure 4 can cause different reference voltages (Vref).As Fig. 5 B, the reference voltage of the band gap reference circuit that its illustrate is finished for " slow process corner ", " fast process corner ", " typical process corner " transistor under the standard semiconductor technology and the relation between the temperature.As shown in the figure, the reference voltage (Vref) that provided of the band gap reference circuit finished of slow process corner transistor can be considered the temperature independent 280mV of being about; The reference voltage (Vref) that the band gap reference circuit that typical process corner transistor is finished is provided can be considered the temperature independent 240mV of being about; The reference voltage (Vref) that the band gap reference circuit that fast process corner transistor is finished is provided can be considered the temperature independent 205mV of being about.

Because the reference voltage (Vref) that the skew of semiconductor technology can cause providing with gap reference circuit produces ± 15% error approximately, causes the band gap reference circuit of Fig. 4 because reference voltage (Vref) accurately can't be provided.Therefore, how to improve the skew of known semiconductor technology and cause to provide accurately the problem of reference voltage (Vref) is fundamental purpose of the present invention with gap reference circuit.

Summary of the invention

The objective of the invention is to propose a kind of band gap reference circuit, this band gap reference circuit can the conformance with standard semiconductor technology, and the exportable reference voltage accurately of this band gap reference circuit (Vref) and haveing nothing to do in the skew of semiconductor technology.

Therefore, the present invention proposes a kind of band gap reference circuit, comprise: input circuit, have two end points, wherein first end points is connected to first field effect transistor and this first field effect transistor has first critical voltage, second end points connects an end of first resistance, and the other end and this second field effect transistor that second field effect transistor connects first resistance have second critical voltage; Mirror image circuit, two output currents on these two end points of its may command make between these two output currents and keep fixing current ratio; And operational amplifier, be connected to these two end points and this mirror image circuit and make the voltage on this two-end-point have voltage relationship in order to control this mirror image circuit; Wherein, this first field effect transistor and this second field effect transistor be all in the operation of subcritical district, and this first critical voltage is greater than this second critical voltage, and these two output currents can not change along with temperature variation.

According to band gap reference circuit of the present invention, wherein this first field effect transistor and this second field effect transistor are all n type field effect transistor, and the grid of this first field effect transistor and drain electrode are connected to this first end points, the source electrode of this first field effect transistor is connected to earth terminal, the grid of this second field effect transistor and drain electrode are connected to this first resistance, and the source electrode of this second field effect transistor is connected to this earth terminal.

According to band gap reference circuit of the present invention, wherein this mirror image circuit also is used to produce its ratio of the 3rd output current in these two output currents.

According to band gap reference circuit of the present invention, wherein the 3rd output current is flowed through second resistance in order to produce reference voltage.

According to band gap reference circuit of the present invention, wherein this first field effect transistor is different with the oxidated layer thickness of this second field effect transistor.

According to band gap reference circuit of the present invention, wherein this mirror image circuit comprises two p type field effect transistors, the grid of these two p type field effect transistors interconnects, the source electrode of these two p type field effect transistors is connected to voltage source, and the drain electrode of these two p type field effect transistors then is these two end points.

According to band gap reference circuit of the present invention, wherein the output terminal of this operational amplifier is connected to the grid of these two p type field effect transistors, and two input ends of this operational amplifier are connected to this two end points.

According to band gap reference circuit of the present invention, wherein the difference of two of these two p type field effect transistors length breadth ratios is used to determine the current ratio that this is fixing.

The present invention also proposes a kind of band gap reference circuit, comprise: input circuit, have two end points, wherein first end points is connected to first field effect transistor and this first field effect transistor has first critical voltage, second end points connects an end of load component, and the other end and this second field effect transistor that second field effect transistor connects load component have second critical voltage; Operational amplifier, it is used for controlling this mirror image circuit according to voltage difference between these two end points; And mirror image circuit, it is used for adjusting two output current sizes on these two end points according to the control of this operational amplifier, and makes between these two output currents and keep fixing current ratio; Wherein, this first field effect transistor and this second field effect transistor be all in the operation of subcritical district, and this first critical voltage is greater than this second critical voltage, and this two output current can not change along with temperature variation.

According to band gap reference circuit of the present invention, wherein this load component is a resistance.

For feature of the present invention and technology contents are further understood, see also following about detailed description of the present invention and accompanying drawing, yet accompanying drawing only provide with reference to and explanation, be not to be used for the present invention is limited.

Description of drawings

Figure 1 shows that the known band gap reference circuit synoptic diagram of forming by pmos fet, PNP bipolar transistor, with operational amplifier.

The reference voltage synoptic diagram that provides in the band gap reference circuit is provided Fig. 2 A.

Fig. 2 B is depicted as reference voltage (Vref) and temperature relation figure.

Fig. 3 A is depicted as the drain current root of mos field effect transistor

With gate source voltage (V _GS) between graph of a relation.

Fig. 3 B is depicted as the drain current logarithm value (log (i of mos field effect transistor _D)) and gate source voltage (V _GS) between graph of a relation.

Figure 4 shows that the known band gap reference circuit synoptic diagram of forming by pmos fet, nmos fet and operational amplifier.

Fig. 5 A is depicted as the relation between " slow process corner " under the standard semiconductor technology, " fast process corner ", " typical process corner " transistorized critical voltage and the temperature.

Fig. 5 B is depicted as the reference voltage of the band gap reference circuit that " process corner slowly ", " fast process corner ", " typical process corner " transistor are finished under the standard semiconductor technology and the relation between the temperature.

Figure 6 shows that band gap reference circuit synoptic diagram of the present invention.

Fig. 7 A is depicted as the critical voltage difference of two transistors when process shifts with different critical voltage.

Fig. 7 B is depicted as the reference voltage synoptic diagram of two transistors when process shifts with different critical voltage.

Wherein, description of reference numerals is as follows:

12 mirror image circuits, 15 operational amplifiers

20 input circuits, 32 basic radio are pressed (V _BE) generator

34 thermal voltage (V _T) the temperature independent constant (K) of generator 36

42 mirror image circuits, 45 operational amplifiers

50 input circuits, 142 mirror image circuits

145 operational amplifiers, 150 input circuits

Embodiment

Please refer to Fig. 6, it is depicted as band gap reference circuit synoptic diagram of the present invention.The band gap reference circuit comprises mirror image circuit 142, operational amplifier 145 and input circuit 150.Comprise three pmos fet M1, M2, M3 in the mirror image circuit 142, in this example, M1, M2, M3 have identical length breadth ratio (W/L).Wherein, the grid of M1, M2 and M3 interconnects, and the source electrode of M1, M2 and M3 is connected to power supply (Vss), and the drain electrode of M1, M2 and M3 can be exported the electric current of Ix, Iy and Iz respectively.In addition, the output terminal of operational amplifier 145 can be connected to the grid of M1, M2 and M3, and the negative input of operational amplifier 145 is connected to the drain electrode of M1, and the electrode input end of operational amplifier 145 is connected to the drain electrode of M2.Moreover input circuit 150 comprises two nmos fet M4, M5; Wherein, the M4 transistor has higher critical voltage (V _Th4), the M5 transistor has lower critical voltage (V _Th5), that is to say V _Th4＞V _Th5Grid and the drain electrode of M4 and M5 interconnect, the source electrode of M4 and M5 is connected to earth terminal, the drain electrode of M4 is connected to the negative input of operational amplifier 145, is connected first resistance (R1) between the electrode input end of the drain electrode of M5 and operational amplifier 145, as load component.Be connected second resistance (R2) between M3 drain electrode and the earth terminal, the M3 exportable reference voltage (Vref) that drains.

By band gap reference circuit shown in Figure 6 as can be known.Because M1, M2, M3 have identical length breadth ratio, therefore, the output current Iy of output current Ix, the M2 drain electrode of M1 drain electrode is identical with the output current Iz of M3 drain electrode, just, and I _x=I _y=I _z---(16).Perhaps, suppose that M1, M2, M3 have length breadth ratio inequality, then I _x, I _y, I _zBetween fixing proportionate relationship can be arranged.Have under the infinitely-great gain at operational amplifier 145, the negative input voltage (Vy) of operational amplifier 145 can equate with electrode input end voltage (Vx).Therefore, R ₁I _y+ V _SG5=V _SG4---(17).That is to say I _y=(V _SG4-V _SG5)/R ₁=Δ V _GS/ R ₁

Moreover, according to equation (13) as can be known, at transistor M4 and its critical voltage difference of M5 (Δ V of subcritical district operation _TH(T)) can be expressed as: $\mathrm{\Δ}{V}_{\mathrm{TH}}\left(T\right)\≅\mathrm{\Δ}{V}_{\mathrm{TH}}\left(T_0\right)+\mathrm{\Δ}{K}_T(\frac{T}{T_0}-1),$ Δ K wherein _T＜0.

And according to equation (14) as can be known, the gate source voltage of transistor M4 and M5 can be expressed as:

$V_{\mathrm{GS}4}\left(T\right)\≅V_{\mathrm{TH}4}\left(T\right)+V_{\mathrm{OFF}4}+[V_{\mathrm{GS}4}\left(T_0\right)-V_{\mathrm{TH}4}\left(T_0\right)-V_{\mathrm{OFF}4}]\frac{T}{T_0}---\left(18\right)$

$V_{\mathrm{GS}5}\left(T\right)\≅V_{\mathrm{TH}5}\left(T\right)+V_{\mathrm{OFF}5}+[V_{\mathrm{GS}5}\left(T_0\right)-V_{\mathrm{TH}5}\left(T_0\right)-V_{\mathrm{OFF}5}]\frac{T}{T_0}---\left(19\right)$

Equation (18) is deducted (19), can get:

$\mathrm{\Δ}{V}_{\mathrm{GS}}\left(T\right)\≅[\mathrm{\Δ}{V}_{\mathrm{TH}}\left(T_0\right)+|\mathrm{\Δ}{K}_T\left|\right]+[\mathrm{\Δ}{V}_{\mathrm{GS}}\left(T_0\right)+|\mathrm{\Δ}{V}_{\mathrm{OFF}}\left|\right]\·\left(\frac{T}{T_0}\right)-[\mathrm{\Δ}{V}_{\mathrm{TH}}\left(T_0\right)+|\mathrm{\Δ}{K}_T\left|\right]\·\left(\frac{T}{T_0}\right)---\left(20\right)$

Wherein, Δ V _GS(T)=V _GS4(T)-V _GS5(T), Δ V _TH(T ₀)=V _TH4(T ₀)-V _TH5(T ₀), Δ V _GS(T ₀)=V _GS4(T ₀)-V _GS5(T ₀), Δ V _OFF=V _OFF4-V _OFF5

By equation (20) as can be known, first [Δ V _TH(T ₀)+| Δ K _T|] be temperature independent fixed value, second $+[\mathrm{\&Delta;}{V}_{\mathrm{GS}}\left(T_0\right)+|\mathrm{\&Delta;}{V}_{\mathrm{OFF}}\left|\right]\&CenterDot;\left(\frac{T}{T_0}\right)$ Be the positive temperature coefficient (PTC) item, the 3rd $-[\mathrm{\&Delta;}{V}_{\mathrm{TH}}\left(T_0\right)+|\mathrm{\&Delta;}{K}_T\left|\right]\&CenterDot;\left(\frac{T}{T_0}\right)$ Be the negative temperature coefficient item.That is to say, can make positive temperature coefficient (PTC) item and the addition of negative temperature coefficient item become any value of zero-temperature coefficient afterwards via the transistorized size of suitable selection (as transistorized channel length, width and length breadth ratio), resistance value.That is to say I _y=Δ V _GS/ R ₁Be a temperature independent electric current, therefore, reference voltage (Vref) is $V_{\mathrm{ref}}=\frac{R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C2007101471580020H1.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\&CenterDot;\mathrm{\&Delta;}{V}_{\mathrm{GS}}.$

The band gap reference circuit of Fig. 6 has more the advantage that does not change reference voltage with semiconductor process variation.Please refer to Fig. 7 A, it is depicted as the critical voltage difference of two transistors when process shifts with different critical voltage.By Fig. 7 A as can be known, no matter how semiconductor technology produces skew, " slow process corner ", " fast process corner ", " typical process corner " transistorized critical voltage difference (Δ V _TH) with the relation of temperature much at one.That is to say that the present invention utilizes identical semiconductor technology to produce two transistors that critical voltage is different, no matter how semiconductor technology produces skew, critical voltage difference (the Δ V of two-transistor _TH) can keep fixing relation with temperature.For instance, in order in standard semiconductor technology, to produce two transistors that critical voltage is different, can promptly can obtain two transistors that critical voltage is different via the thickness of two transistorized grid oxic horizons of control.

Moreover, please refer to Fig. 7 B, its illustrate is two transistors with different critical voltage reference voltage synoptic diagram when the process shifts.According to Fig. 7 B as can be known, compare with process corner worst, reference voltage (Vref) only can change approximately ± 2%.That is to say that the reference voltage of band gap reference circuit of the present invention hardly can be along with process shifts and temperature variation and changed.

Therefore, the band gap reference circuit that provides standard semiconductor technology to realize is provided the advantage of band gap reference circuit of the present invention, and the band gap reference circuit can operate in low operating voltage, and, utilize the critical voltage difference that transistor produced (Δ V with different critical voltage _TH) come the skew of compensation standard semiconductor technology to make the reference voltage of band gap reference circuit can change along with process shifts and temperature variation hardly.

In sum; though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; when can doing various variations and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.

Claims (10)

1. be with gap reference circuit for one kind, comprise:

Input circuit, have two end points, wherein first end points is connected to the grid and the drain electrode of first field effect transistor, the source electrode of this first field effect transistor is connected to earth terminal and this first field effect transistor has first critical voltage, second end points connects an end of first resistance, the grid of second field effect transistor is connected the other end of first resistance with drain electrode, the source electrode of this second field effect transistor is connected to this earth terminal and this second field effect transistor has second critical voltage;

Mirror image circuit, two output currents on these two end points of its may command make between these two output currents and keep fixing current ratio; And

Operational amplifier is connected to these two end points and this mirror image circuit and makes the voltage on this two-end-point have voltage relationship in order to control this mirror image circuit;

Wherein, this first field effect transistor and this second field effect transistor be all in the operation of subcritical district, and this first critical voltage is greater than this second critical voltage, and these two output currents can not change along with temperature variation.

2. band gap reference circuit as claimed in claim 1, wherein this first field effect transistor and this second field effect transistor are all n type field effect transistor.

3. band gap reference circuit as claimed in claim 1, wherein this mirror image circuit also is used to produce its ratio of the 3rd output current in these two output currents.

4. band gap reference circuit as claimed in claim 3, wherein the 3rd output current is flowed through second resistance in order to produce reference voltage.

5. band gap reference circuit as claimed in claim 1, wherein this first field effect transistor is different with the oxidated layer thickness of this second field effect transistor.

6. band gap reference circuit as claimed in claim 1, wherein this mirror image circuit comprises two p type field effect transistors, the grid of these two p type field effect transistors interconnects, the source electrode of these two p type field effect transistors is connected to voltage source, and the drain electrode of these two p type field effect transistors then is these two end points.

7. band gap reference circuit as claimed in claim 6, wherein the output terminal of this operational amplifier is connected to the grid of these two p type field effect transistors, and two input ends of this operational amplifier are connected to this two end points.

8. band gap reference circuit as claimed in claim 6, wherein the difference of two of these two p type field effect transistors length breadth ratios is used to determine the current ratio that this is fixing.

9. be with gap reference circuit for one kind, comprise:

Input circuit, have two end points, wherein first end points is connected to the grid and the drain electrode of first field effect transistor, the source electrode of this first field effect transistor is connected to earth terminal and this first field effect transistor has first critical voltage, second end points connects an end of load component, the grid of second field effect transistor is connected the other end of load component with drain electrode, the source electrode of this second field effect transistor is connected to this earth terminal and this second field effect transistor has second critical voltage;

Operational amplifier, it is used for controlling this mirror image circuit according to voltage difference between these two end points; And

Mirror image circuit, it is used for adjusting two output current sizes on these two end points according to the control of this operational amplifier, and makes between these two output currents and keep fixing current ratio;

Wherein, this first field effect transistor and this second field effect transistor be all in the operation of subcritical district, and this first critical voltage is greater than this second critical voltage, and these two output currents can not change along with temperature variation.

10. band gap reference circuit as claimed in claim 9, wherein this load component is a resistance.

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