CN101105698A - Band-gap reference circuit - Google Patents
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Abstract
The invention discloses a belt difference reference circuit which comprises an input circuit with two end points, a mirror image circuit which can control two output currents of two end points and maintains the invariable current proportion between the two output currents and a calculation amplifier which is connected with the two end points and the mirror image circuit to control the mirror image circuit so that the voltage between the two end points has voltage relation; wherein a first end point is connected with a first field effect transistor with a first critical voltage; a first resistance is connected between a second end point and a second field effect transistor with a second critical voltage; the first field effect transistor and the second field effect transistor are both operated in sub critical area; the first critical voltage is huger than the second critical voltage; the two output currents don't vary with the variable temperature.
Description
Technical Field
The present invention relates to a Bandgap Reference Circuit (Bandgap Reference Circuit), and more particularly, to a Bandgap Reference Circuit with a low operating voltage.
Background
It is known that the function of the bandgap reference circuit is to provide a stable reference Voltage (Vref) which does not change with the process, temperature and power supply Voltage, and therefore, the bandgap reference circuit is widely designed in many circuits in the field of hybrid circuits, such as a Voltage Regulator (Voltage Regulator), a digital-to-analog circuit, and a Low Drift Amplifier (Low Drift Amplifier).
Referring to fig. 1, a schematic diagram of a conventional bandgap reference circuit comprising a PMOS fet, a PNP bipolar transistor, and an operational amplifier is shown. Generally, the bandgap reference Circuit includes a mirror Circuit (Mirroring Circuit) 12, an operational Amplifier (Operation Amplifier) 15, and an input Circuit 20. The mirror circuit 12 includes three PMOS Field Effect Transistors (FETs) M1, M2, M3, in this example, M1, M2, M3 having the same aspect ratio (W/L). The gates of M1, M2 and M3 are connected to each other, the sources of M1, M2 and M3 are connected to a power supply (Vss), and the drains of M1, M2 and M3 can respectively output the currents Ix, iy and Iz. In addition, the output terminal of the operational amplifier 15 can be connected to the gates of M1, M2 and M3, the positive input terminal of the operational amplifier 15 is connected to the drain of M2, and the negative input terminal of the operational amplifier 15 is connected to the drain of M1. Furthermore, the input circuit 20 includes two PNP bipolar transistors (BJTs) Q1, Q2; wherein, the area of Q1 is m times of the area of Q2, the base and collector of Q1 and Q2 are connected to the ground terminal to make Q1 and Q2 form Diode connection (Diode connection), the emitter of Q2 is connected to the negative input terminal of the operational amplifier 15, and a first resistor (R1) is connected between the emitter of Q1 and the positive input terminal of the operational amplifier 15. Furthermore, the area of a PNP bipolar transistor (BJT) Q3 is the same as that of Q2, the base and the collector of Q3 are connected to the ground, a second resistor (R2) is connected between the emitter of Q3 and the drain of M3, and the drain of M3 can output a reference voltage (Vref).
As can be seen from the bandgap reference circuit shown in fig. 1. Since M1, M2, M3 have the same aspect ratio, the output current Ix of M1 drain, the output current Iy of M2 drain and the output current of M3 drainThe current Iz is the same, i.e., I x ＝I y ＝I z ---(1)。
Further, when the operational amplifier 15 has an infinite gain, the negative input terminal voltage (Vx) and the positive input terminal voltage (Vy) of the operational amplifier 15 are equal to each other. Thus, R 1 I y +V EB1 ＝V EB2 ---(2)。
Since Q1 and Q2 form a diode connection (diodebonnect) and Q1 has an area m times as large as that of Q2, therefore,
and
further deducing V BE1 ＝V T ln(I y /mI s ) - - (3) and V BE2 ＝V T ln(I x /I s ) - - - (4). Wherein, I s Saturation current of Q2 (SaturationCurrent), V T Is a thermal voltage (ThermalVoltage).
Combining (1), (2), (3) and (4) to finally obtain I y ＝(1/R 1 )V T lnm- - (5), and, a reference voltage V ref ＝(R 2 /R 1 )V T lnm+V EB3 ---(6)。
Fig. 2A is a schematic diagram of a reference voltage provided in a bandgap reference circuit. According to equation (6), the reference voltage (Vref) can be regarded as a base-emitter voltage generator (32) for providing a base-emitter voltage (V) between the base and emitter of the PNP bipolar transistor BE ) Applying a thermal voltage (V) T ) The generator (thermolvatagger) 34 generates a thermal voltage (V) T ) Multiplied by a temperature-independent constant K (temperature-independent scale) 36. That is, vref = V BE +KV T In comparison with the bandgap reference circuit of fig. 1, K = (R) 2 /R 1 )lnm。
Referring to FIG. 2B, a graph of the relationship between the reference voltage (Vref) and temperature is shown. As can be seen from the figure, the fundamental Voltage (VBE) of the fundamental voltage generator 32 has a characteristic of a negative temperature coefficient (negative temperature coefficient), and conversely, the thermal voltage (V) of the thermal voltage generator 34 T ) Has the characteristic of positive temperature coefficient (posiTeterTeturethecoeffecificient). Therefore, at thermal voltage (V) T ) Providing a weight of a fixed coefficient (K) and a base radio voltage (V) BE ) After the addition can beAny value of zero temperature coefficient (zero temperature coefficient) is obtained. That is, the reference voltage (Vref) may be almost a constant value at any temperature.
Generally, the forward-bias voltage (forward-bias) of the bipolar transistor is about 0.83V at-40 ℃, and the bias voltage of the mirror circuit 12 and the operational amplifier 15 between the power supply (Vss) and the input circuit 20 needs at least 0.17V. That is, in order for the band difference reference circuit of FIG. 1 to function properly, at least 1V (0.83V + 0.17V) of supply voltage (Vss) is required. That is, known bandgap reference circuits require an operating voltage of at least 1V.
However, since the evolution of semiconductor technology has evolved from the early 0.13 μm process to the 90nm process, the 60nm process, and even the future 45nm, 30nm process, the operating voltage of analog IC chips must also be lower and lower as the process advances. However, too low an operating voltage will impact the proper operation of the known bandgap reference circuit.
In order to solve the problem of higher operating voltage of the conventional bandgap reference circuit, a bipolar transistor is replaced by a Schottky Diode (Schottky Diode) with a lower forward bias voltage in the input circuit 20 of the bandgap reference circuit, so as to reduce the operating voltage of the bandgap reference circuit. Alternatively, the operating voltage of the bandgap reference circuit can be reduced by replacing the bipolar transistor with a dynamic threshold voltage metal oxide semiconductor (DT MOS) field effect transistor.
However, the schottky diode or DT MOS process is not compatible with the standard semiconductor process, and therefore a special process step must be added to the standard process and a mask required by the special process is provided to complete the schottky diode or DT MOS. Thus, the cost required for producing the chip will be increased.
Referring to FIG. 3A, the drain current root of a MOSFET is shown
And gate source voltage (V) GS ) A graph of the relationship between them. In general, when the gate source voltage (V) of the MOSFET is high GS ) Is less than voltage (V) ON ) When the mosfet is operated in a sub-threshold region (subthreshold), or referred to as a weak inversion region (weak inversion region), the gate-source voltage (V) of the mosfet is increased, and vice versa GS ) Greater than the turn-on voltage (V) ON ) When the MOS field effect transistor is operated in a strong inversion region (STRONGVERSION REGION), the MOS field effect transistor can be considered to be operated in a strong inversion region (STRONGVERSION REGION). Referring to FIG. 3B, the log (I) of the drain current of the MOSFET is shown D ) And a gate-source voltage (V) GS ) A graph of the relationship between them. As shown in FIG. 3B, the log (I) of the drain current in the sub-threshold region D ) And a gate-source voltage (V) GS ) The characteristic of the mosfet is similar to that of a diode when the mosfet is operated in the sub-threshold region.
Therefore, in order to make all the components in the bandgap reference circuit compatible with the standard semiconductor process, it is known to replace the bipolar transistor in the input circuit 20 with a normal mosfet and operate the mosfet in the sub-threshold region, so that the characteristic of the mosfet in the sub-threshold region is similar to that of a normal diode, so as to reduce the operating voltage output by the bandgap reference circuit.
When a Metal Oxide Semiconductor (MOS) field effect transistor operates at a sub-threshold region,
wherein, I D0 As process-dependent parameters (V) T Is a thermal voltage (thermoholtage) and
xi and xi are not idealParameter(s)(non-ideal factor) and xi has a value of 1 to 3.
Referring to fig. 4, a schematic diagram of a bandgap reference circuit comprising a PMOS fet, an NMOS fet and an operational amplifier is shown. The bandgap reference circuit includes a mirror circuit 42, an operational amplifier 45, and an input circuit 50. The mirror circuit 42 includes three PMOS field effect transistors M1, M2, M3, in this example, M1, M2, M3 have the same aspect ratio (W/L). The gates of M1, M2 and M3 are connected to each other, the sources of M1, M2 and M3 are connected to a power supply (Vss), and the drains of M1, M2 and M3 can respectively output the currents Ix, iy and Iz. In addition, the output terminal of the operational amplifier 45 can be connected to the gates of M1, M2 and M3, the negative input terminal of the operational amplifier 45 is connected to the drain of M1, and the positive input terminal of the operational amplifier 45 is connected to the drain of M2. Further, the input circuit 50 includes two NMOS field effect transistors M4, M5; the length-width ratio of M4 is n times of the length-width ratio of M5, the gates and drains of M4 and M5 are connected, the sources of M4 and M5 are connected to the ground, the drain of M5 is connected to the negative input terminal of the operational amplifier 45, and a first resistor (R1) is connected between the drain of M4 and the positive input terminal of the operational amplifier 45. Furthermore, the aspect ratio of the NMOS field effect transistor M6 is the same as the aspect ratio of M5, the gate and the drain of M6 are connected to each other, the source of M6 is connected to the ground, a second resistor (R2) is connected between the drain of M6 and the drain of M3, and the drain of M3 can output the reference voltage (Vref).
As can be seen from the bandgap reference circuit shown in fig. 4. Since M1, M2, and M3 have the same aspect ratio, the output current Ix of the drain of M1, the output current Iy of the drain of M2, and the output current Iz of the drain of M3 are the same, i.e., I x ＝I y ＝I z ---(7)。
Further, when the operational amplifier 45 has an infinite gain, the negative input terminal voltage (Vx) and the positive input terminal voltage (Vy) of the operational amplifier 45 are equal to each other. Thus, R 1 I y +V GS5 ＝V GS4 ---(8)。
When the PMOS fet is operated in the sub-critical region and M4 has an aspect ratio n times the aspect ratio of M5, therefore,
and
further deducing
And
combining (7), (8), (9) and (10) to finally obtain I y ＝(ξ·V T /R 1 ) ln (n) - - (11), and, a reference voltage V ref ＝(R 2 /R 1 )ξ·V T ln(n)+V GS6 - - - (12). That is, according to equation (12), the reference voltage (Vref) can be regarded as a combination of a positive temperature coefficient thermal voltage generator and a negative temperature coefficient gate-source voltage generator. Therefore, the reference voltage (Vref) can be almost constant at any temperature.
Furthermore, according to the journal IEEEJ.solid-StateCircuits, vol.38, no.1, pp.151-154, 2003 and journal Integrated Circuit design technology,2006.ICICDTapos; 06.2006IEEEInternationaConferenceVolume, issue,24-26May2006 Page(s): 1-4, the critical voltage model (modelingthreshold voltage) established in the sub-threshold region of the mosfet is:wherein K is T ＜0。
Furthermore, the gate-source voltage (V) GS ) Critical voltage (V) TH ) In relation to temperature of
Wherein, V OFF Which can be considered as the correction constant term (coretectant) for the threshold voltage between the weak inversion region and the strong inversion region. To be combined withEquations (13) and (14) can be obtained:
wherein, K G Is < 0 and
. From the equations (13) and (15), the gate-source voltage (V) GS ) And threshold voltage (V) TH ) All have negative temperature coefficient characteristics, and the gate-source voltage (V) can be known from equation (14) GS ) Is critical voltage (V) TH ) As a function of temperature.
Although the process of the bandgap reference circuit of fig. 4 can meet the standard semiconductor process, the characteristic parameters of the mosfet change with the shift (devigion) of the semiconductor process, which results in the difference of the threshold voltage of the mosfet. For example, in the same semiconductor process, the extreme case of the process can divide the transistor regions into "slow corner (S corner)" transistors, "fast corner (F corner)" transistors, and "typical corner (T corner)" transistors. The so-called "slow process corner" transistor represents the first transistor of a plurality of transistors completed with a semiconductor process, which has the weakest (weakost) and the slowest (slowest) drive strength performance. Furthermore, the so-called "fast process corner" transistor represents the second transistor of the plurality of transistors completed by the semiconductor process, which has the strongest (transistor) and fastest (fast) driving strength performance. The term "typical process corner" transistor refers to a transistor with normal driving strength performance among a plurality of transistors completed by the semiconductor process.
Referring to fig. 5A, the relationship between the threshold voltage and the temperature of the "slow process corner", "fast process corner" and "typical process corner" transistors in the standard semiconductor process is illustrated. As can be seen, at-20 deg.C, the corners of the slow processCritical voltage (V) of transistor TH ) About 625mV, with increasing temperature, the threshold voltage (V) of the corner transistor in a slow process at 100 deg.C TH ) About 525mV; at the temperature of-20 ℃, the temperature is controlled,typical Process corner transistor threshold Voltage (V) TH ) About 520mV, with increasing temperature, the threshold voltage (V) of a typical process corner transistor at 100 deg.C TH ) About 425mV; at-20 deg.C, the threshold voltage (V) of the corner transistor is rapidly adjusted TH ) About 420mV, with increasing temperature, the threshold voltage (V) of the fast process corner transistor at 100 deg.C TH ) And about 325mV.
From equation (14), the gate-source voltage (V) GS ) Is the critical voltage (V) TH ) As a function of temperature. Therefore, manufacturing the bandgap reference circuit shown in fig. 4 using the same process may result in different reference voltages (Vref). FIG. 5B illustrates the relationship between the reference voltage and temperature of a bandgap reference circuit implemented by "slow process corner", "fast process corner" and "typical process corner" transistors in a standard semiconductor process. As shown, the reference voltage (Vref) provided by the bandgap reference circuit completed by the slow process corner transistor can be considered to be about 280mV independent of temperature; the reference voltage (Vref) provided by the bandgap reference circuit completed by a typical process corner transistor may be considered to be about 240mV independent of temperature; the reference voltage (Vref) provided by the bandgap reference circuit completed by the fast process corner transistors may be considered to be approximately 205mV independent of temperature.
The reference voltage (Vref) provided by the bandgap reference circuit has an error of about ± 15% due to the offset of the semiconductor process, so that the bandgap reference circuit of fig. 4 cannot provide an accurate reference voltage (Vref). Therefore, the main objective of the present invention is to improve the offset of the conventional semiconductor process and to cause the bandgap reference circuit to fail to provide an accurate reference voltage (Vref).
Disclosure of Invention
An object of the present invention is to provide a bandgap reference circuit which can conform to a standard semiconductor process and which can output an accurate reference voltage (Vref) regardless of a shift of the semiconductor process.
Accordingly, the present invention provides a bandgap reference circuit, comprising: an input circuit having two terminals, wherein a first terminal is connected to a first field effect transistor having a first threshold voltage, a second terminal is connected to a second field effect transistor having a second threshold voltage, and a first resistor is connected between the second terminal and the second field effect transistor; a mirror circuit, which can control two output currents on the two end points to maintain a fixed current ratio between the two output currents; and an operational amplifier connected to the two terminals and the mirror circuit for controlling the mirror circuit such that voltages at the two terminals have a voltage relationship; the first field effect transistor and the second field effect transistor are operated in a sub-critical region, the first critical voltage is larger than the second critical voltage, and the two output currents cannot change along with temperature change.
The bandgap reference circuit according to the present invention, wherein the first and second fets are both N-type fets, and the gate and drain of the first fet are connected to the first node, the source of the first fet is connected to ground, the gate and drain of the second fet are connected to the first resistor, and the source of the second fet is connected to the ground.
The bandgap reference circuit according to the present invention, wherein the mirror circuit is further configured to generate a third output current proportional to the two output currents.
According to the bandgap reference circuit of the present invention, the third output current flows through the second resistor for generating the reference voltage.
The bandgap reference circuit according to the present invention, wherein the oxide layer thickness of the first field effect transistor is different from that of the second field effect transistor.
The bandgap reference circuit according to the present invention, wherein the mirror circuit comprises two P-type field effect transistors, gates of the two P-type field effect transistors are connected to each other, sources of the two P-type field effect transistors are connected to a voltage source, and drains of the two P-type field effect transistors are the two terminals.
The bandgap reference circuit according to the present invention, wherein the output terminal of the operational amplifier is connected to the gates of the two P-type field effect transistors, and the two input terminals of the operational amplifier are connected to the two terminals.
The bandgap reference circuit according to the present invention, wherein the difference between the two aspect ratios of the two PFETs is used to determine the fixed current ratio.
The invention also provides a bandgap reference circuit, comprising: an input circuit having two terminals, wherein a first terminal is connected to a first field effect transistor having a first threshold voltage, and a second terminal is connected to a load element between the first and second field effect transistors having a second threshold voltage; an operational amplifier for controlling the mirror circuit according to a voltage difference between the two terminals; the mirror circuit is used for adjusting the two output currents on the two end points according to the control of the operational amplifier and keeping a fixed current proportion between the two output currents; wherein the first field effect transistor and the second field effect transistor are operated in a sub-threshold region, the first threshold voltage is greater than the second threshold voltage, and the two output currents do not change with temperature change.
The bandgap reference circuit according to the present invention, wherein the load component is a resistor.
For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a schematic diagram of a conventional bandgap reference circuit including a PMOS fet, a PNP bipolar transistor, and an operational amplifier.
FIG. 2A is a schematic diagram of a reference voltage provided in a bandgap reference circuit.
FIG. 2B is a graph of reference voltage (Vref) versus temperature.
FIG. 3A shows the drain current root of a MOSFET
And gate source voltage (V) GS ) The relationship between them.
FIG. 3B shows the log (i) of the drain current of the MOSFET D ) And a gate-source voltage (V) GS ) The relationship between them.
FIG. 4 is a schematic diagram of a conventional bandgap reference circuit including a PMOS FET, an NMOS FET and an operational amplifier.
FIG. 5A illustrates the relationship between the threshold voltage and temperature of a "slow process corner", "fast process corner" and "typical process corner" transistor under standard semiconductor processing.
FIG. 5B is a graph showing the relationship between the reference voltage and temperature of a bandgap reference circuit implemented by "slow process corner", "fast process corner" and "typical process corner" transistors in a standard semiconductor process.
FIG. 6 is a schematic diagram of a bandgap reference circuit of the present invention.
FIG. 7A shows the difference between the threshold voltages of two transistors with different threshold voltages under process drift.
FIG. 7B is a schematic diagram of reference voltages of two transistors with different threshold voltages during process drift.
Wherein the reference numerals are as follows:
12 mirror circuit 15 operational amplifier
20 input circuit 32 base-emitter voltage (V) BE ) Generator
34 thermal voltage (V) T ) Constant (K) of generator 36 independent of temperature
42 mirror circuit 45 operational amplifier
50 input circuit 142 mirror circuit
145 operational amplifier 150 input circuit
Detailed Description
Referring to fig. 6, a schematic diagram of a bandgap reference circuit of the invention is shown. The bandgap reference circuit includes a mirror circuit 142, an operational amplifier 145, and an input circuit 150. The mirror circuit 142 includes three PMOS field effect transistors M1, M2, M3, in this example, M1, M2, M3 have the same aspect ratio (W/L). The gates of M1, M2 and M3 are connected to each other, the sources of M1, M2 and M3 are connected to a power supply (Vss), and the drains of M1, M2 and M3 can respectively output the currents Ix, iy and Iz. In addition, the output terminal of the operational amplifier 145 may be connected to the gates of M1, M2, and M3, the negative input terminal of the operational amplifier 145 is connected to the drain of M1, and the positive input terminal of the operational amplifier 145 is connected to the drain of M2. Furthermore, the input circuit 150 includes two NMOS field effect transistors M4, M5; wherein, the M4 transistor has a higher critical voltage (V) th4 ) M5 transistors have a lower threshold voltage (V) th5 ) That is, V th4 ＞V th5 . The gates and drains of M4 and M5 are connected to each other, the sources of M4 and M5 are connected to the ground, the drain of M4 is connected to the negative input terminal of the operational amplifier 145, and a first resistor (R1) is connected between the drain of M5 and the positive input terminal of the operational amplifier 145 as a load component. A second resistor (R2) is connected between the drain electrode of the M3 and the grounding terminal, and the drain electrode of the M3 can output a reference voltage (Vref).
As can be seen from the band difference reference circuit shown in fig. 6. Since M1, M2, M3 have the same aspect ratio, the output current Ix of M1 drain, the output current Iy of M2 drain and the output current Iz of M3 drain are the same, i.e., I x ＝I y ＝I z - - - (16). Or, assuming that M1, M2, M3 have different aspect ratios, I x 、I y 、I z There may be a fixed proportional relationship between them. With the operational amplifier 145 having infinite gain, the negative input terminal voltage (Vy) and the positive input terminal voltage (Vx) of the operational amplifier 145 will be equal. Thus, R 1 I y +V SG5 ＝V SG4 - - - (17). That is, I y ＝(V SG4 -V SG5 )/R 1 ＝ΔV GS /R 1 。
Furthermore, according to equation (13), the critical voltage difference (Δ V) between transistors M4 and M5 operating in the sub-threshold region TH (T)) can be expressed as:
wherein Δ K T ＜0。
From equation (14), the gate-source voltages of the transistors M4 and M5 can be expressed as:
subtracting (19) from equation (18) yields:
wherein, is Δ V GS (T)＝V GS4 (T)-V GS5 (T)、ΔV TH (T 0 )＝V TH4 (T 0 )-V TH5 (T 0 )、 ΔV GS (T 0 )＝V GS4 (T 0 )-V GS5 (T 0 )、ΔV OFF ＝V OFF4 -V OFF5 。
From equation (20), the first term [ Δ V ] TH (T 0 )+|ΔK T |]A fixed value independent of temperature, a second term
Is a positive temperature coefficient term, a third termIs a negative temperature coefficient term. That is, the resistance value can be any value that the positive temperature coefficient term and the negative temperature coefficient term are added to become zero temperature coefficient by properly selecting the size of the transistor (such as the channel length, width and aspect ratio of the transistor). That is, I y ＝ΔV GS /R 1 I.e., a temperature independent current, and thus the reference voltage (Vref) is
The bandgap reference circuit of fig. 6 has the advantage of not changing the reference voltage with the semiconductor process variation. Fig. 7A shows a threshold voltage difference between two transistors with different threshold voltages in process shift. As can be seen from FIG. 7A, the difference in threshold voltage (Δ V) of the "slow process corner", "fast process corner" and "typical process corner" transistors is not determined by the offset of the semiconductor process TH ) The relationship with temperature is almost the same. That is, the present invention utilizes the same semiconductor process to manufacture two transistors with different threshold voltages, and the threshold voltage difference (Δ V) of the two transistors is not influenced by the deviation of the semiconductor process TH ) Will maintain a fixed relationship with temperature. For example, in order to manufacture two transistors with different threshold voltages in a standard semiconductor process, the thickness of the gate oxide layer of the two transistors can be controlledTwo transistors with different threshold voltages can be obtained.
Referring to fig. 7B, a schematic diagram of reference voltages of two transistors with different threshold voltages during process shift is shown. As can be seen from fig. 7B, the reference voltage (Vref) varies by only about ± 2% compared to the worst process corner. That is, the reference voltage of the bandgap reference circuit of the present invention hardly changes with process drift and temperature variation.
Therefore, the bandgap reference circuit of the present invention is advantageous in that it provides a bandgap reference circuit that can be implemented in a standard semiconductor process, and can be operated at a low operating voltage, and utilizes the threshold voltage difference (Δ V) generated by transistors with different threshold voltages TH ) To compensate for the drift of the standard semiconductor process so that the reference voltage of the bandgap reference circuit hardly changes with the process drift and the temperature variation.
Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that various changes and modifications can be made therein by one skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A bandgap reference circuit comprising:
an input circuit having two terminals, wherein a first terminal is connected to a first field effect transistor having a first threshold voltage, a second terminal is connected to a second field effect transistor having a second threshold voltage, and a first resistor is connected between the second terminal and the second field effect transistor;
a mirror circuit, which can control two output currents at the two terminals to maintain a fixed current ratio between the two output currents; and
an operational amplifier connected to the two terminals and the mirror circuit for controlling the mirror circuit such that voltages at the two terminals have a voltage relationship;
the first field effect transistor and the second field effect transistor are operated in a sub-critical region, the first critical voltage is larger than the second critical voltage, and the two output currents cannot change along with temperature change.
2. The bandgap reference circuit of claim 1, wherein the first and second FETs are N-type FETs, and the first FET has a gate and a drain connected to the first terminal, the first FET has a source connected to ground, the second FET has a gate and a drain connected to the first resistor, and the second FET has a source connected to the ground.
3. The bandgap reference circuit of claim 1, wherein the mirror circuit is further configured to generate a third output current that is proportional to the two output currents.
4. The bandgap reference circuit of claim 3, wherein the third output current flows through a second resistor for generating a reference voltage.
5. The bandgap reference circuit of claim 1, wherein the first field effect transistor and the second field effect transistor have different oxide layer thicknesses.
6. The bandgap reference circuit of claim 1, wherein the mirror circuit comprises two P-type FETs, gates of the two P-type FETs are connected to each other, sources of the two P-type FETs are connected to a voltage source, and drains of the two P-type FETs are the two terminals.
7. The bandgap reference circuit of claim 6, wherein the output of the operational amplifier is connected to the gates of the two PFETs, and the two inputs of the operational amplifier are connected to the two terminals.
8. The bandgap reference circuit as recited in claim 6, wherein the difference between the two aspect ratios of the two PFETs is used to determine the fixed current ratio.
9. A bandgap reference circuit comprising:
an input circuit having two terminals, wherein a first terminal is connected to a first field effect transistor having a first threshold voltage, a second terminal is connected to a load element between the first terminal and a second field effect transistor having a second threshold voltage;
an operational amplifier for controlling the mirror circuit according to a voltage difference between the two terminals; and
the mirror image circuit is used for adjusting the two output currents on the two endpoints according to the control of the operational amplifier and keeping a fixed current proportion between the two output currents;
the first field effect transistor and the second field effect transistor are operated in a sub-critical region, the first critical voltage is larger than the second critical voltage, and the two output currents cannot change along with temperature change.
10. The bandgap reference circuit of claim 9, wherein said load element is a resistor.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101763132A (en) * | 2008-12-24 | 2010-06-30 | 精工电子有限公司 | Reference voltage circuit |
| CN101782789A (en) * | 2008-12-26 | 2010-07-21 | 东部高科股份有限公司 | Bandgap reference voltage generating circuit |
| CN103246310A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | CMOS (complementary metal-oxide-semiconductor) band-gap reference source circuit |
| CN106502301A (en) * | 2016-12-12 | 2017-03-15 | 湖南国科微电子股份有限公司 | Band-gap reference and the compatible circuit of low pressure difference linear voltage regulator |
| CN113741611A (en) * | 2021-08-24 | 2021-12-03 | 杭州深谙微电子科技有限公司 | Band-gap reference voltage source circuit |
-
2007
- 2007-08-30 CN CN200710147158A patent/CN100580606C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101763132A (en) * | 2008-12-24 | 2010-06-30 | 精工电子有限公司 | Reference voltage circuit |
| CN101782789A (en) * | 2008-12-26 | 2010-07-21 | 东部高科股份有限公司 | Bandgap reference voltage generating circuit |
| CN103246310A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | CMOS (complementary metal-oxide-semiconductor) band-gap reference source circuit |
| CN103246310B (en) * | 2013-05-07 | 2015-07-22 | 上海华力微电子有限公司 | CMOS (complementary metal-oxide-semiconductor) band-gap reference source circuit |
| CN106502301A (en) * | 2016-12-12 | 2017-03-15 | 湖南国科微电子股份有限公司 | Band-gap reference and the compatible circuit of low pressure difference linear voltage regulator |
| CN113741611A (en) * | 2021-08-24 | 2021-12-03 | 杭州深谙微电子科技有限公司 | Band-gap reference voltage source circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100580606C (en) | 2010-01-13 |
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