CN102073332B - Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator - Google Patents
Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator Download PDFInfo
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Abstract
The invention discloses a low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of an output belt low drop-out linear voltage regulator. The band-gap reference circuit comprises a start-up circuit module, a band-gap reference module, a clamping operational amplifier and an output driving module based on low drop-out (LDO), wherein an output end of the start-up circuit module is connected with an input end of the band-gap reference module; an output end of the band-gap reference module is connected with an input end of the output driving module; and an output end of the output driving module is used for outputting needed band-gap reference voltage. The low drop-out linear voltage regulator is taken as an output buffer stage by the band-gap reference circuit, so that the requirement of high driving capability is met, and lower voltage output can be obtained.
Description
Technical field
The present invention relates to a kind of circuit; Particularly a kind of low-temperature coefficient CMOS band-gap reference circuit of exporting the band low pressure difference linear voltage regulator; In IC system; Band-gap reference circuit be one requisite; It has advantages such as low-temperature coefficient, high PSRR, long-term stability, and being commonly used to provides accurate electric current and voltage reference source for frequency mixer (Mixer), voltage controlled oscillator (VCO), channel acceptance filter (CSF), analog to digital converter (ADC), programmable gain amplifier modules such as (PGA).
Background technology
Reference voltage source is the very important ingredient of contemporary Analogous Integrated Electronic Circuits, and it has vital role to the application and the development of high-new Analog Electronics Technique.In many integrated circuit, like digital to analog converter.Analog to digital converter, linear voltage regulator all need accurate and stable voltage reference.In the digital communication system of precision measuring instrument instruments and meters and widespread use, all often be used as integrated reference voltage source the benchmark of systematic survey and calibration.Voltage reference circuit and linear voltage-stabilizing circuit have much in common.In fact, linear voltage-stabilizing circuit can be regarded as a kind of voltage reference circuit from function, but output current (or power) is bigger.All technical indicators that almost characterize these two kinds of circuit all have very big versatility, and difference is that voltage reference circuit pair floats with temperature, precision is relevant index request is than higher.Therefore, the principle for high performance system selection reference voltage source is:
It is wide poor that peripheral circuit is held, to reduce system cost;
Temperature coefficient is low, to reduce the influence of temperature variation to precision;
Long-time stability are good, and thermo-lag is little, guarantee the repeatability of system;
Noise is low, reduces the restriction to systemic resolution;
Low in energy consumption, to be suitable for battery power supply system;
The capacitive load driving force is strong, to reduce the dynamic load error.
In view of the These characteristics of reference voltage source, in order to satisfy the requirement of various application scenarios, Analogous Integrated Electronic Circuits manufacturer releases the integrated reference source of high precision of numerous species.From the principle of work angle, the problem of design basis voltage source most critical is that precision height and temperature are floated little.
1971; Robert Widla has proposed the notion of band-gap reference epoch-makingly; Because adopting the voltage source circuit of this technology compares with the voltage source of other types; With standard CMOS (complementary metal-oxide semiconductor (CMOS)) process compatible, have lower supply voltage more easily, so be widely used in the various Analogous Integrated Electronic Circuits.Bandgap voltage reference is a kind of benchmark technology that does not rely on temperature and power supply, all is widely used in a lot of fields.In the middle of many characteristics of band-gap reference; The operating temperature range of low-temperature coefficient and broad is particularly important to radio system and high-resolution modulus, digital to analog converter; Even this temperature stability; Wide operating temperature range, and the noise robustness of the benchmark precision performance very that can influence total system.
But in recent years, along with the continuous minimizing of integrated circuit characteristic dimension, the continuous reduction of supply voltage, system has proposed more and more urgent demand to high integration, high performance band-gap reference.Usually adopt the structure of current-mode can obtain output voltage values arbitrarily now; Adopt the exponential curvature technique for temperature compensation to reduce temperature coefficient; Adopt high-gain degree of depth negative feedback loop to reduce the influence of supply voltage, thereby improve PSRR reference voltage; Adopt low pressure difference linear voltage regulator to come regulated output voltage etc.
Summary of the invention
The objective of the invention is to design a kind of low-temperature coefficient CMOS band-gap reference circuit of exporting the band low pressure difference linear voltage regulator, this band-gap reference not only can obtain lower temperature coefficient, can also drive the load of very big capacitive scope.
The objective of the invention is to realize like this:
A kind of low-temperature coefficient CMOS band-gap reference circuit of exporting the band low pressure difference linear voltage regulator; Characteristics are that this circuit comprises start-up circuit modules A, band-gap reference module B, clamper operational amplifier D and based on the output driver module C of low pressure difference linear voltage regulator, wherein: the start-up circuit modules A comprises the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6 and the 7th metal-oxide-semiconductor M7; Band-gap reference module B comprises the first image current pipe M8, the first transistor Q1, the second image current pipe M9, the 3rd image current pipe M10, transistor seconds Q2, first resistance R 1, the 4th image current pipe M11, the 3rd transistor Q3 and second resistance R 2; Clamper operational amplifier D comprises the first tail current pipe N1, the second tail current pipe N2, the 3rd tail current pipe P1, the 4th tail current pipe P2, the 5th tail current pipe P3; The first difference input pipe P4, the second difference input pipe P5, the first load pipe N3, the second load pipe N4, the 3rd load pipe N5, first zero compensating resistance Rz and first zero building-out capacitor Cz; Comprise the 5th image current pipe M12, the 6th image current pipe M13, the 6th tail current pipe M18, the 3rd difference input pipe M16, the 4th difference input pipe M17, the 4th load pipe M14, the 5th load pipe M15, the second zero compensation resistance R 3, the second zero compensation capacitor C 1, adjustment pipe M19, the first divider resistance R4 and the second divider resistance R5 based on the output driver module C of low pressure difference linear voltage regulator;
The source termination power end VDD of the said first metal-oxide-semiconductor M1, grid end ground connection; The drain terminal of the drain terminal of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 links to each other with the grid end of the 3rd metal-oxide-semiconductor M3; The source end ground connection of the second metal-oxide-semiconductor M2; The drain terminal of the grid end of the grid end of the second metal-oxide-semiconductor M2, the 5th metal-oxide-semiconductor M5, drain terminal, the 4th metal-oxide-semiconductor M4 links to each other with the grid end of the 7th metal-oxide-semiconductor M7; The source end ground connection of the 3rd metal-oxide-semiconductor M3; The drain terminal of the output terminal of the grid end of the grid end of the grid end of the grid end of the grid end of the grid end of the grid end of the drain terminal of the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6, the first image current pipe M8, the second image current pipe M9, the 3rd image current pipe M10, the 4th image current pipe M11, the 5th image current pipe M12, clamper operational amplifier D, the drain terminal of the 6th metal-oxide-semiconductor M6 and the 7th metal-oxide-semiconductor M7 links to each other; The source termination power end VDD of the 4th metal-oxide-semiconductor M4; The source end ground connection of the 5th metal-oxide-semiconductor M5; The source termination power end VDD of the 6th metal-oxide-semiconductor M6; The source end ground connection of the 7th metal-oxide-semiconductor M7; The source termination power VDD of the first image current pipe M8; The negative input end VIN of the drain terminal of the first image current pipe M8, clamper operational amplifier D links to each other with the emitter of the first transistor Q1; The base stage of the first transistor Q1, collector and ground link to each other; The source end of the second image current pipe M9 links to each other with power end VDD; The positive input terminal VIP of the drain terminal of the second image current pipe M9, clamper operational amplifier D links to each other with an end of first resistance R 1; The other end of first resistance R 1 links to each other with the emitter of transistor seconds Q2; The base stage of transistor seconds Q2, collector and ground link to each other; The source end of the 3rd image current pipe M10 links to each other with power end VDD; One end of the drain terminal of the 3rd image current pipe M10, second resistance R 2 links to each other with the grid end of the 4th difference input pipe M17; The other end of second resistance R 2 links to each other with the emitter of the 3rd transistor Q3; The base stage of the 3rd transistor Q3, collector and ground link to each other; The source end of the 4th image current pipe M11 links to each other with power end VDD; The drain terminal of the 4th image current pipe M11 links to each other with the current input terminal BIAS of clamper operational amplifier D; The source end of the 5th image current pipe M12 links to each other with power end; The drain terminal of the drain terminal of the 5th image current pipe M12, the 6th image current pipe M13, grid end and the grid end of the 6th tail current pipe M18 link to each other; The source end of the 6th image current pipe M13 links to each other with ground; The source end of the 4th load pipe M14 links to each other with power end VDD; The drain terminal of the 4th load pipe M14, grid end and the drain terminal of the 3rd difference input pipe M16 link to each other; The source end of the 5th load pipe M15 links to each other with power end VDD; One end of the drain terminal of the drain terminal of the 5th load pipe M15, the 4th difference input pipe M17, the second zero compensation resistance R 3 links to each other with the grid end of adjustment pipe M19; The drain terminal of the grid end of the 3rd difference input pipe M16, adjustment pipe M19 and the end of the first divider resistance R4 link to each other; The source end of the source end of the 3rd difference input pipe M16, the 4th difference input pipe M17 links to each other with the drain terminal of the 6th tail current pipe M18; The source end of the 6th tail current pipe M18 links to each other with ground; The source end of adjustment pipe M19 links to each other with power end; The other end of the second zero compensation resistance R 3 links to each other with an end of the second zero compensation capacitor C 1; The other end of the second zero compensation capacitor C 1 links to each other with ground; The other end of the first divider resistance R4 links to each other with the end of the second divider resistance R5; The other end of the second divider resistance R5 links to each other with ground; The grid end of the drain terminal of the first tail current pipe N1 of clamper operational amplifier D, grid end, the second tail current pipe N2 links to each other with the drain terminal of the 4th image current pipe M11; The source end of the first tail current pipe N1 links to each other with ground; The source end of the second tail current pipe N2 links to each other with ground; The grid end of the drain terminal of the drain terminal of the second tail current pipe N2, the 3rd tail current pipe P1, grid end, the 4th tail current pipe P2 links to each other with the grid end of the 5th tail current pipe P3; The source end of the 3rd tail current pipe P1 links to each other with power end VDD; The source end of the 4th tail current pipe P2 links to each other with power end VDD; The source end of the drain terminal of the 4th tail current pipe P2, the first difference input pipe P4 links to each other with the source end of the second difference input pipe P5; The drain terminal of the drain terminal of the first difference input pipe P4, the first load pipe N3, grid end and the grid end of the second load pipe N4 link to each other; The grid end of the drain terminal of the drain terminal of the second difference input pipe P5, the second load pipe N4, the second load pipe N5 links to each other with the end of first zero compensating resistance Rz; The source end of the first load pipe N3 links to each other with ground; The source end of the second load pipe N4 links to each other with ground; The source end of the 5th tail current pipe P3 links to each other with power end VDD; The drain terminal of the drain terminal of the 5th tail current pipe P3, the 3rd load pipe N5 links to each other with the end of first zero building-out capacitor Cz; The other end of first zero building-out capacitor Cz links to each other with the other end end of first zero compensating resistance Rz.
The said first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6, the first image current pipe M8, the second image current pipe M9, the 3rd image current pipe M10, the 4th image current pipe M11, the 5th image current pipe M12, the 4th load pipe M14, the 5th load pipe M15, adjustment pipe M19, the 3rd tail current pipe P1, the 4th tail current pipe P2, the 5th tail current pipe P3, the first difference input pipe P4 and the second difference input pipe P5 are the PMOS pipe; The second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 5th metal-oxide-semiconductor M5, the 7th metal-oxide-semiconductor M7, the 6th image current pipe M13, the 3rd difference input pipe M16, the 4th difference input pipe M17, the 6th tail current pipe M18, the first tail current pipe N1, the second tail current pipe N2, the first load pipe N3, the second load pipe N4 and the 3rd load pipe N5 are the NMOS pipe.
The present invention drives through the output of low pressure difference linear voltage regulator as band-gap reference, can realize the capacitive load of wide region.Equally, through the low pressure linear voltage regulator, can obtain lower output bandgap voltage reference.
Compared with prior art, the present invention has following good effect:
(1), the present invention uses low pressure difference linear voltage regulator as output buffering, obtained lower output bandgap voltage reference, realizes the capacitive load of wide region simultaneously.
(2), low pressure difference linear voltage regulator of the present invention, the one-level amplifier of use need not off chip resistor voltage and carries out frequency compensation, realizes that complete chip integration becomes.
Description of drawings
Fig. 1 is a band-gap reference circuit structural drawing of the present invention;
Fig. 2 is the clamper operation amplifier circuit figure among the present invention.
Embodiment
Below; To do further explanation to the present invention through concrete embodiment; Yet embodiment only is giving an example of alternative embodiment of the present invention, and its disclosed characteristic only is used for explanation and sets forth technical scheme of the present invention, and is not used in qualification protection scope of the present invention.
Consult Fig. 1, groundwork process of the present invention be detailed at present:
The present invention comprises start-up circuit modules A, band-gap reference module B, clamper operational amplifier D and based on output driver module C four parts of low pressure difference linear voltage regulator.Circuit start (modules A) is achieved in that when entire circuit powers on M1 manages unlatching, and the grid voltage of M3 pipe rises, thereby makes the M3 pipe be in state of saturation, and the drain voltage of M3 descends, and makes M4, M6 saturated.Electric current is mirrored in the main circuit through current mirror and distinguishes, thereby makes the entire circuit operate as normal.This moment, the drain voltage of M4 rose, thereby made the M2 conducting, and the drain voltage of M2 descends, and made the grid voltage of M3 descend, and caused M3 to end.The reference voltage of circuit low-temperature coefficient (module B) is achieved in that the value of two opposite temperature coefficients is carried out addition through proper proportion, thereby obtains the magnitude of voltage of a zero-temperature coefficient.The base-emitter voltage of bipolar transistor has negative temperature coefficient, and two bipolar transistors are when being operated in different electric currents, and the difference of two base-emitter voltages is directly proportional with temperature." clamper " of operational amplifier (module D) is achieved in that the negative feedback with operational amplifier terminates at the Q1 branch road, and positive feedback terminates on the Q2 branch road, when positive terminal voltage is higher, and Δ V
InIncrease, the magnitude of voltage of OP output terminal increases, and the grid voltage of M8, M9 increases, and the electric current on Q1, the Q2 branch road reduces, and the ohmically pressure drop of R1 reduces, and the magnitude of voltage of OP positive feedback end descends, and this is a degeneration factor.When gain was very big, the numerical value of two input ends of OP was tending towards equal.Realize like this during the output of low pressure high driving ability (module C): for traditional low pressure difference linear voltage regulator; Because its output impedance is very high, and receives the influence of output load very big, whole loop stable very poor; The most outer electric capacity resistance of sheet that adopt of traditional low pressure difference linear voltage regulator carry out zero compensation; The value of general electric capacity is all bigger, and corresponding chip area is also very big, can't realize that chip integration becomes; The present invention uses follow-on low pressure difference linear voltage regulator to increase the output load capacity; Use the error amplifier of one-level differential operational amplifier as low pressure difference linear voltage regulator; Output terminal at error amplifier; The branch road of the i.e. parallelly connected resistance capacitance series connection of the gate input of adjustment pipe, thus introduce a zero point, satisfy the phase margin requirement of 60 degree; Reduce frequency compensated difficulty, thereby well realize the purpose that chip integration becomes.Simultaneously, low pressure difference linear voltage regulator can also obtain lower output voltage values through electric resistance partial pressure.
Claims (2)
1. export the low-temperature coefficient CMOS band-gap reference circuit of being with low pressure difference linear voltage regulator for one kind; It is characterized in that this circuit comprises start-up circuit module (A), band-gap reference module (B), clamper operational amplifier (D) and based on the output driver module (C) of low pressure difference linear voltage regulator, wherein: start-up circuit module (A) comprises first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6) and the 7th metal-oxide-semiconductor (M7); Band-gap reference module (B) comprises the first image current pipe (M8), the first transistor (Q1), the second image current pipe (M9), the 3rd image current pipe (M10), transistor seconds (Q2), first resistance (R1), the 4th image current pipe (M11), the 3rd transistor (Q3) and second resistance (R2); Clamper operational amplifier (D) comprises the first tail current pipe (N1), the second tail current pipe (N2), the 3rd tail current pipe (P1), the 4th tail current pipe (P2), the 5th tail current pipe (P3); The first difference input pipe (P4), the second difference input pipe (P5), the first load pipe (N3), the second load pipe (N4), the 3rd load pipe (N5), first zero compensating resistance (Rz) and first zero building-out capacitor (Cz); Output driver module (C) based on low pressure difference linear voltage regulator comprises the 5th image current pipe (M12), the 6th image current pipe (M13), the 6th tail current pipe (M18), the 3rd difference input pipe (M16), the 4th difference input pipe (M17), the 4th load pipe (M14), the 5th load pipe (M15), the second zero compensation resistance (R3), the second zero compensation electric capacity (C1), adjustment pipe (M19), first divider resistance (R4) and second divider resistance (R5);
The source termination power end (VDD) of said first metal-oxide-semiconductor (M1), grid end ground connection; The drain terminal of the drain terminal of first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2) links to each other with the grid end of the 3rd metal-oxide-semiconductor (M3); The source end ground connection of second metal-oxide-semiconductor (M2); The drain terminal of the grid end of the grid end of second metal-oxide-semiconductor (M2), the 5th metal-oxide-semiconductor (M5), drain terminal, the 4th metal-oxide-semiconductor (M4) links to each other with the grid end of the 7th metal-oxide-semiconductor (M7); The source end ground connection of the 3rd metal-oxide-semiconductor (M3); The drain terminal of the output terminal of the grid end of the grid end of the grid end of the grid end of the grid end of the grid end of the grid end of the drain terminal of the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 6th metal-oxide-semiconductor (M6), the first image current pipe (M8), the second image current pipe (M9), the 3rd image current pipe (M10), the 4th image current pipe (M11), the 5th image current pipe (M12), clamper operational amplifier (D), the 6th metal-oxide-semiconductor (M6) links to each other with the drain terminal of the 7th metal-oxide-semiconductor (M7); The source termination power end (VDD) of the 4th metal-oxide-semiconductor (M4); The source end ground connection of the 5th metal-oxide-semiconductor (M5); The source termination power end (VDD) of the 6th metal-oxide-semiconductor (M6); The source end ground connection of the 7th metal-oxide-semiconductor (M7); The source termination power (VDD) of the first image current pipe (M8); The negative input end (VIN) of the drain terminal of the first image current pipe (M8), clamper operational amplifier (D) links to each other with the emitter of the first transistor (Q1); Base stage, collector and the ground of the first transistor (Q1) link to each other; The source end of the second image current pipe (M9) links to each other with power end (VDD); The positive input terminal (VIP) of the drain terminal of the second image current pipe (M9), clamper operational amplifier (D) links to each other with an end of first resistance (R1); The other end of first resistance (R1) links to each other with the emitter of transistor seconds (Q2); Base stage, collector and the ground of transistor seconds (Q2) link to each other; The source end of the 3rd image current pipe (M10) links to each other with power end (VDD); One end of the drain terminal of the 3rd image current pipe (M10), second resistance (R2) links to each other with the grid end of the 4th difference input pipe (M17); The other end of second resistance (R2) links to each other with the emitter of the 3rd transistor (Q3); Base stage, collector and the ground of the 3rd transistor (Q3) link to each other; The source end of the 4th image current pipe (M11) links to each other with power end (VDD); The current input terminal (BIAS) of the drain terminal of the 4th image current pipe (M11) and clamper operational amplifier (D) links to each other; The source end of the 5th image current pipe (M12) links to each other with power end; The drain terminal of the drain terminal of the 5th image current pipe (M12), the 6th image current pipe (M13), grid end and the grid end of the 6th tail current pipe (M18) link to each other; The source end of the 6th image current pipe (M13) links to each other with ground; The source end of the 4th load pipe (M14) links to each other with power end (VDD); The drain terminal of the 4th load pipe (M14), grid end and the drain terminal of the 3rd difference input pipe (M16) link to each other; The source end of the 5th load pipe (M15) links to each other with power end (VDD); One end of the drain terminal of the drain terminal of the 5th load pipe (M15), the 4th difference input pipe (M17), the second zero compensation resistance (R3) links to each other with the grid end of adjustment pipe (M19); The drain terminal of the grid end of the 3rd difference input pipe (M16), adjustment pipe (M19) and an end of first divider resistance (R4) link to each other; The source end of the source end of the 3rd difference input pipe (M16), the 4th difference input pipe (M17) links to each other with the drain terminal of the 6th tail current pipe (M18); The source end of the 6th tail current pipe (M18) links to each other with ground; The source end of adjustment pipe (M19) links to each other with power end; The other end of the second zero compensation resistance (R3) links to each other with an end of the second zero compensation electric capacity (C1); The other end of the second zero compensation electric capacity (C1) links to each other with ground; The other end of first divider resistance (R4) links to each other with an end of second divider resistance (R5); The other end of second divider resistance (R5) links to each other with ground; The grid end of the drain terminal of the first tail current pipe (N1) of clamper operational amplifier (D), grid end, the second tail current pipe (N2) links to each other with the drain terminal of the 4th image current pipe (M11); The source end of the first tail current pipe (N1) links to each other with ground; The source end of the second tail current pipe (N2) links to each other with ground; The grid end of the drain terminal of the drain terminal of the second tail current pipe (N2), the 3rd tail current pipe (P1), grid end, the 4th tail current pipe (P2) links to each other with the grid end of the 5th tail current pipe (P3); The source end of the 3rd tail current pipe (P1) links to each other with power end (VDD); The source end of the 4th tail current pipe (P2) links to each other with power end (VDD); The source end of the drain terminal of the 4th tail current pipe (P2), the first difference input pipe (P4) links to each other with the source end of the second difference input pipe (P5); The drain terminal of the drain terminal of the first difference input pipe (P4), the first load pipe (N3), grid end and the grid end of the second load pipe (N4) link to each other; The grid end of the drain terminal of the drain terminal of the second difference input pipe (P5), the second load pipe (N4), the second load pipe (N5) links to each other with an end of first zero compensating resistance (Rz); The source end of the first load pipe (N3) links to each other with ground; The source end of the second load pipe (N4) links to each other with ground; The source end of the 5th tail current pipe (P3) links to each other with power end (VDD); The drain terminal of the drain terminal of the 5th tail current pipe (P3), the 3rd load pipe (N5) links to each other with an end of first zero building-out capacitor (Cz); The other end of first zero building-out capacitor (Cz) links to each other with the other end end of first zero compensating resistance (Rz).
2. the low-temperature coefficient CMOS band-gap reference circuit of output band low pressure difference linear voltage regulator according to claim 1 is characterized in that first metal-oxide-semiconductor (M1), the 4th metal-oxide-semiconductor (M4), the 6th metal-oxide-semiconductor (M6), the first image current pipe (M8), the second image current pipe (M9), the 3rd image current pipe (M10), the 4th image current pipe (M11), the 5th image current pipe (M12), the 4th load pipe (M14), the 5th load pipe (M15), adjustment pipe (M19), the 3rd tail current pipe (P1), the 4th tail current pipe (P2), the 5th tail current pipe (P3), the first difference input pipe (P4) and the second difference input pipe (P5) are the PMOS pipe; Second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 5th metal-oxide-semiconductor (M5), the 7th metal-oxide-semiconductor (M7), the 6th image current pipe (M13), the 3rd difference input pipe (M16), the 4th difference input pipe (M17), the 6th tail current pipe (M18), the first tail current pipe (N1), the second tail current pipe (N2), the first load pipe (N3), the second load pipe (N4) and the 3rd load pipe (N5) are the NMOS pipe.
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| CN2010106094860A CN102073332B (en) | 2010-12-28 | 2010-12-28 | Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100492244C (en) * | 2007-03-21 | 2009-05-27 | 北京中星微电子有限公司 | Voltage regulator with low voltage difference |
| CN101183270B (en) * | 2007-11-21 | 2010-06-02 | 北京中星微电子有限公司 | Low pressure difference voltage stabilizer |
| CN101271344B (en) * | 2008-05-15 | 2010-06-02 | 北京中星微电子有限公司 | High-power supply noise restraint low-voltage difference voltage regulator |
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