CN107483044B - Baseline drift voltage correction circuit for network port chip - Google Patents
Baseline drift voltage correction circuit for network port chip Download PDFInfo
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- CN107483044B CN107483044B CN201710547130.0A CN201710547130A CN107483044B CN 107483044 B CN107483044 B CN 107483044B CN 201710547130 A CN201710547130 A CN 201710547130A CN 107483044 B CN107483044 B CN 107483044B
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- H03—ELECTRONIC CIRCUITRY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
A baseline drift voltage correction circuit for a network interface chip comprises a common mode adjustment module, a comparator module, a digital processing module, a charge pump module, a voltage-controlled current source module and a baseline drift correction module. The input differential signal is adjusted to the input range of the comparator after passing through the common mode adjusting module, the comparator outputs square waves by comparing the height of the positive end and the height of the negative end of the differential signal, the digital processing module controls the charge pump module to output different control voltages according to the duty ratio of the square waves output by the comparator, and the voltages control the magnitude of the compensation current in the baseline wandering module to finish the correction of the baseline wandering of the input signal. The circuit judges and compensates signal direct current and low-frequency attenuation caused by the high-pass characteristic of the isolation transformer, corrects baseline drift in signal transmission and improves the noise tolerance of the circuit. Meanwhile, the design difficulty of the analog circuit is reduced, the dynamic input range of the ADC is not sacrificed any more, and the baseline drift voltage correction range of the circuit is expanded.
Description
Technical Field
The invention relates to a baseline drift voltage correction circuit for an internet access chip, and belongs to the field of Ethernet baseband communication.
Background
In order to increase the signal transmission distance and improve the signal anti-interference capability and be compatible with the network ports with different interface levels, an isolation transformer is required to be added to the output of the electric port when the network port chip is applied. However, the high-pass characteristic of the isolation transformer causes signal direct current and low-frequency attenuation, which causes baseline drift in signal transmission, and as the length of a transmission line increases, the baseline drift phenomenon in signal transmission is also aggravated, which causes the system error rate to increase as the length of the transmission line increases, so that the noise margin is seriously affected, and the input of a subsequent ADC may exceed an allowable range.
The baseline wander voltage correction circuit consists of a control circuit and a compensation circuit, the control circuit and the compensation circuit are generally realized by a digital algorithm in the existing design, and because the baseline wander increases the input level range of the ADC, the baseband excursion compensation of a digital domain can lose the input dynamic range of the ADC, the ADC with higher performance needs to be selected for compensation, and the design difficulty of an analog circuit is increased invisibly.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the base line drift voltage correction circuit for the network port chip is used for overcoming the defects of the prior art, reducing the design difficulty of an analog circuit, not sacrificing the dynamic input range of an ADC (analog to digital converter), and expanding the base line drift voltage correction range of the circuit.
The technical solution of the invention is as follows: a baseline drift voltage correction circuit for a network port chip comprises a common mode adjustment module, a comparator module, a digital processing module, a charge pump module, a voltage-controlled current source module and a baseline drift correction module;
a common mode adjustment module: receiving a differential signal input on a twisted pair wire, adjusting the differential signal to the input range of a comparator through common mode adjustment, and outputting the adjusted differential signal to a comparator module;
a comparator module: the height of the positive end and the height of the negative end of the differential signal are compared to obtain a square wave with a certain duty ratio, and the square wave is output to a digital processing module;
a digital processing module: according to the duty ratio of the square wave signal output by the comparator, judging the baseline voltage drift condition of the input differential signal on the twisted pair, obtaining a charge pump control signal according to the baseline voltage drift condition, and outputting the charge pump control signal to the charge pump module;
a charge pump module: the charge pump capacitor is charged or discharged according to a charge pump control signal output by the digital processing module, and the voltage on the charge pump capacitor is output to the voltage-controlled current source module;
a voltage-controlled current source module: adjusting the output current by comparing the output voltage of the charge pump module with the reference voltage value, and sending the adjusted output current to the baseline drift correction module;
a baseline drift correction module: the current sent by the voltage-controlled current source module is utilized to carry out current mirroring, compensation current is generated according to the mirrored current, and the common-mode voltage of the input differential signal on the twisted pair is adjusted according to the compensation current, so that the correction of the voltage drift of the input differential signal baseline on the twisted pair is realized.
The implementation method for obtaining the charge pump control signal by the digital processing module is as follows:
when the duty ratio of the square wave signal output by the comparator is more than 50%, the base line voltage of the input differential signal on the twisted pair wire drifts to the positive end, and the charge pump control signal is a discharge signal;
when the duty ratio of the square wave signal output by the comparator is less than 50%, the baseline voltage of the input differential signal on the twisted pair wire drifts to the negative end, and the charge pump control signal is a charging signal.
The charge pump module comprises a current source IUPA current source IDNMOS transistor M1, MOS transistor M2 and capacitor C1;
the gate terminal of the MOS transistor M1 is connected with the charging signal output by the digital processing module, and the source terminal of the MOS transistor M1 is connected with the current source IUPThe drain terminal of the MOS transistor M1 is connected with the drain terminal of the MOS transistor M2 and one end of the capacitor C1, the gate terminal of the MOS transistor M2 is connected with the discharge signal output by the digital processing module, the source terminal of the MOS transistor M2 is connected with the current source IDNIs connected to a current source IDNIs connected to the other end of the capacitor C1, a current source IUPInput terminal of MOS transistor M1 and drain terminal of MOS transistor M1 and current source IDNThe output terminals of the charge pump module are used as three output terminals of the charge pump module and used for outputting voltage to the voltage-controlled current source module.
The voltage-controlled current source module comprises an MOS tube M3, an MOS tube M4 and a current source I0A current source I1A current source I2A current source I3And a resistance RS；
Current source I1And a current source I2The input end of the charge pump module is simultaneously connected with the current source I of the charge pump moduleUPInput terminal connected to a current source I1The output end of the MOS tube M3 is connected with the drain end of the MOS tube M3, the gate end of the MOS tube M3 is connected with the drain end of the MOS tube M1 of the charge pump module, and the source end of the MOS tube M3 is connected with the current source I0Is connected to a current source I2The output end of the MOS tube M4 is connected with the drain end of the MOS tube M4, the gate end of the MOS tube M4 is connected with the reference voltage, and the source end of the MOS tube M4 is connected with the current source I3Is connected to a current source I0Output terminal and current source I3The output end of the charge pump module is simultaneously connected with the current source I of the charge pump moduleDNThe output end is connected; resistance RSIs connected between the source terminal of the MOS transistor M3 and the source terminal of the MOS transistor M4.
The current source I0A current source I1A current source I2And a current source I3Current I in0、I1、I2、I3Satisfy I1+I2＝I0+I3，I0＝I3。
The baseline drift correction module comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M912, a MOS tube M13, a MOS tube M14, a capacitor C2, a current source I11A current source I21A current source I12A current source I22A current source Ibl1And a current source Ib12；
The non-inverting input terminal of the operational amplifier U1 is connected with one terminal of the resistor R1 and the current source Ibl1Is connected with one end of a resistor R3, the other end of a resistor R1 is connected with a positive differential signal input on a twisted pair, and a current source Ib11The output end of the resistor R3 is connected with the non-inverting input end of the operational amplifier U2, and the other end of the resistor R3 is connected with the positive output end of the operational amplifier U1; the inverting input terminal of the operational amplifier U1 is connected to one terminal of the resistor R2 and the current source Ibl2Is connected to one end of a resistor R4The other end of the resistor R2 is connected with a negative differential signal input on the twisted pair, and the current source Ibl2The output end of the resistor R4 is connected with the non-inverting input end of the operational amplifier U3, and the other end of the resistor R4 is connected with the negative output end of the operational amplifier U1; the positive and negative output ends of the operational amplifier U1 are used for outputting a differential signal after baseline drift correction;
current source I11And a current source I12For current source I in voltage-controlled current source module1Mirror image of, current source I21And a current source I22For current source I in voltage-controlled current source module2Mirror image of, current source I11A current source I21A current source I12And a current source I22Are interconnected by a current source I11The output end of the operational amplifier is simultaneously connected with the non-inverting input end of the operational amplifier U2, the drain end of the MOS tube M5 and the drain end of the MOS tube M6, and the current source I21The output end of the current source I is simultaneously connected with the drain end of the MOS tube M7 and the gate end of the MOS tube M1012The output end of the current source I is simultaneously connected with the drain end of the MOS tube M8 and the gate end of the MOS tube M1222The output end of the operational amplifier U2 and the inverting input end of the operational amplifier U3 are connected to the drain end of the MOS tube M9, the drain end of the MOS tube M14 and the non-inverting input end of the operational amplifier U3, the inverting input end of the operational amplifier U2 and the inverting input end of the operational amplifier U3 are connected to the reference voltage VCM, the output end of the operational amplifier U2 is connected to the gate end of the MOS tube M5, one end of the capacitor C2, the gate end of the MOS tube M14 and the output end of the operational amplifier U3, the gate end of the MOS tube M6, the gate end of the MOS tube M7, the gate end of the MOS tube M8 and the gate end of the MOS tube M9, the source end of the MOS tube M5, the source end of the MOS tube M10, the source end of the MOS tube M11, the source end of the MOS tube M912, the source end of the MOS tube M13, the source end of the MOS tube M14 and the other end of the capacitor C2 are connected together, the drain end of the MOS tube M6 is connected to the drain end of the MOS tube M10, the drain end of, the source end of the MOS transistor M9 is connected with the drain end of the MOS transistor M13, the gate end of the MOS transistor M10 is connected with the gate end of the MOS transistor M11, and the gate end of the MOS transistor M12 is connected with the gate end of the MOS transistor M13.
Compared with the prior art, the invention has the following advantages:
(1) the invention judges the baseline voltage drift condition through the digital processing module, controls the charge pump module to output different control voltages according to the baseline voltage drift condition, controls the size of the compensation current in the baseline drift correction module by the control voltage, finishes the correction of the baseline drift of the input signal, realizes the judgment and the compensation of the signal direct current and low frequency attenuation caused by the high-pass characteristic of the isolation transformer, corrects the baseline drift in the signal transmission and improves the noise tolerance of the circuit.
(2) The controller (digital processing module) is realized in a digital domain, and the compensator (baseline wander correction module) is realized in an analog circuit, so that the design difficulty of the analog circuit is reduced, a signal subjected to baseline wander correction does not exceed the input range of an ADC (analog-to-digital converter), and the baseline wander voltage correction range of the circuit is expanded.
(3) The invention realizes the conversion from a digital control signal to an analog compensation signal through the charge pump module circuit and the voltage-controlled current source module circuit, has simple circuit and clear principle, and lays a foundation for realizing the baseline drift correction in the analog circuit.
Drawings
FIG. 1 is a block diagram of the general structure of a baseline wander voltage correction circuit of the present invention;
FIG. 2 is a schematic diagram of a charge pump and a voltage controlled current source in the present invention;
FIG. 3 is a schematic diagram of a baseline wander correction circuit of the present invention;
Detailed Description
The high-pass characteristic of the isolation transformer can attenuate direct current and low-frequency components of signals to cause baseline drift of signal common-mode voltage. As shown in fig. 1, the baseline wander voltage correction circuit of the present invention includes a common mode adjustment module, a comparator module, a digital processing module, a charge pump module, a voltage controlled current source module, and a baseline wander correction module.
A common mode adjustment module: receiving the differential signal input on the twisted pair, carrying out common mode adjustment on the differential signal, namely adjusting the voltage of the differential signal from 2.5V to 1.25V, so that the differential signal is adjusted to the input range of the comparator, and outputting the adjusted differential signal to the comparator module.
A comparator module: and square waves with certain duty ratio are obtained by comparing the positive end and the negative end of the differential signal, and are output to the digital processing module.
A digital processing module: and judging the baseline voltage drift condition of the input differential signal on the twisted pair according to the duty ratio of the square wave signal output by the comparator, obtaining a charge pump control signal according to the baseline voltage drift condition, and outputting the charge pump control signal to the charge pump module.
When the duty ratio of the square wave signal output by the comparator is more than 50%, the base line voltage of the input differential signal on the twisted pair wire drifts to the positive end, and the charge pump control signal is a discharge signal;
when the duty ratio of the square wave signal output by the comparator is less than 50%, the baseline voltage of the input differential signal on the twisted pair wire drifts to the negative end, and the charge pump control signal is a charging signal.
A charge pump module: and charging or discharging the charge pump capacitor according to the charge pump control signal output by the digital processing module, and outputting the voltage on the charge pump capacitor to the voltage-controlled current source module.
A voltage-controlled current source module: the current is adjusted by comparing the output voltage of the charge pump module with the reference voltage value, and the adjusted current is output to the baseline drift correction module.
A baseline drift correction module: the current mirror is carried out by utilizing the adjusting current output by the voltage-controlled current source module, the compensating current is generated according to the mirrored current, and the common-mode voltage of the input differential signal on the twisted pair is adjusted according to the compensating current, so that the correction of the voltage drift of the input differential signal baseline on the twisted pair is realized.
Fig. 2 is a circuit diagram of the charge pump module and the voltage-controlled current source module. The charge pump module comprises a current source IUPA current source IDNMOS pipe M1, MOS pipe M2 and capacitor C1, the voltage-controlled current source module includes MOS pipe M3, MOS pipe M4, current source I0A current source I1A current source I2A current source I3And a resistance RS。
The gate terminal of the MOS transistor M1 is connected with the charging signal AN output by the digital processing module, and the source terminal of the MOS transistor M1 is connected with the current source IUPThe drain terminal of the MOS transistor M1 is connected to the drain terminal of the MOS transistor M2 and one terminal of the capacitor C1, the gate terminal of the MOS transistor M2 is connected to the discharge signal BN output by the digital processing module, and the source terminal of the MOS transistor M2 is connected to the current source IDNIs connected to the input terminal of the controller.
Current source I1And a current source I2Is simultaneously connected with a current source IUPInput terminal connected to a current source I1The output end of the MOS tube M3 is connected with the drain end of the MOS tube M3, the gate end of the MOS tube M3 is connected with the drain end of the MOS tube M1, and the source end of the MOS tube M3 is connected with the current source I0Is connected to a current source I2The output end of the MOS tube M4 is connected with the drain end of the MOS tube M4, the gate end of the MOS tube M4 is connected with the reference voltage, and the source end of the MOS tube M4 is connected with the current source I3Is connected to a current source I0Output terminal and current source I3Is simultaneously connected with the current source IDNThe output end is connected; resistance RSIs connected between the source terminal of the MOS transistor M3 and the source terminal of the MOS transistor M4.
Provided with a current source I0A current source I1A current source I2A current source I3Respectively is I0、I1、I2、I3Then, the working principle of the charge pump module and the voltage-controlled current source module is as follows: when AN is low and BN is low, the current source IUPThe capacitor C1 is charged, and the voltage on the C1 rises; when AN is high and BN is high, current IDNDischarging the capacitor C1 and the voltage on C1 decreases. Voltage at C1 and reference voltage VrefComparing to adjust the current I1、I2The size of (2). If the voltage at C1 is greater than VrefThen, I1Increase of I2Decrease; if the voltage at C1 is less than VrefThen, I1Decrease of I2And is increased. In addition, I1+I2＝I0+I3，I0＝I3. Current I1And I2Will be used to generate the complement in the baseline wander correction moduleThe current is compensated.
As shown in fig. 3, the baseline wander correcting module includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, a MOS transistor M912, a MOS transistor M13, a MOS transistor M14, a capacitor C2, a current source I11A current source I21A current source I12A current source I22A current source Ibl1And a current source Ib12. The operational amplifier U1 is a folded cascode operational amplifier, and the operational amplifiers U2 and U3 are symmetric operational amplifiers.
The non-inverting input terminal of the operational amplifier U1 is connected with one terminal of the resistor R1 and the current source Ib11Is connected with one end of a resistor R3, the other end of a resistor R1 is connected with a positive differential signal input on a twisted pair, and a current source Ib11The output end of the resistor R3 is connected with the non-inverting input end of the operational amplifier U2, and the other end of the resistor R3 is connected with the positive output end of the operational amplifier U1; the inverting input terminal of the operational amplifier U1 is connected to one terminal of the resistor R2 and the current source Ib12Is connected with one end of a resistor R4, the other end of a resistor R2 is connected with a negative differential signal input on a twisted pair, and a current source Ib12The output end of the resistor R4 is connected with the non-inverting input end of the operational amplifier U3, and the other end of the resistor R4 is connected with the negative output end of the operational amplifier U1; the positive and negative output ends of the operational amplifier U1 output differential signals after baseline drift correction;
current source I11And a current source I12For current source I in voltage-controlled current source module1Mirror image of, current source I21And a current source I12For current source I in voltage-controlled current source module2Mirror image of, current source I11A current source I21A current source I12And a current source I22Are interconnected by a current source I11The output end of the operational amplifier is simultaneously connected with the non-inverting input end of the operational amplifier U2, the drain end of the MOS tube M5 and the drain end of the MOS tube M6, and the current source I21The output end of the current source I is simultaneously connected with the drain end of the MOS tube M7 and the gate end of the MOS tube M1012The output end of the current source I is simultaneously connected with the drain end of the MOS tube M8 and the gate end of the MOS tube M1222The output end of the operational amplifier U2 is connected with the gate end of the MOS transistor M5, one end of the capacitor C2, the gate end of the MOS transistor M14 and the output end of the operational amplifier U3, the gate end of the MOS transistor M6, the gate end of the MOS transistor M7, the gate end of the MOS transistor M8 and the gate end of the MOS transistor M9, the source end of the MOS transistor M5, the source end of the MOS transistor M56, the source end of the MOS transistor M11, the source end 912 of the MOS transistor M, the drain end of the MOS transistor M14 and the other end of the capacitor C2, the drain end of the MOS transistor M6 is connected with the drain end of the MOS transistor M10, the drain end of the MOS transistor M10 is connected with the drain end of the MOS transistor M10, the source end of the MOS transistor M9 is connected with the drain end of the MOS transistor M13, the gate end of the MOS transistor M10 is connected with the gate end of the MOS transistor M11, and the gate end of the MOS transistor M12 is connected with the gate end of the MOS transistor M13.
The current I generated by the voltage-controlled current source module in FIG. 21，I2Mirror image to baseline drift correction module, I, through current mirror circuit1Mirrored as a current source I11A current source I21，I2Mirrored as a current source I21A current source I22As shown in FIG. 3, a current source I is provided11A current source I21A current source I12A current source I22A current source Ib11And a current source Ibl2The current in (A) is I11、I21、I12、I22、Ibl1And Ibl2The current flowing through MOS transistors M5 and M14 is I31And I32According to the current conservation law:
at point X:
Ib11＝I31+I21-I11
at point Y there are:
Ibl2＝I32+I12-I22
I31and I32Is a constant current, and I31＝I32By regulating the current I11、I12And I21、I22Can adjust the baseline wander correction current Ibl1And Ibl2，Ibl1And Ibl2Currents are respectively extracted from the positive input end and the negative input end of the operational amplifier, so that the common-mode voltage of the input ends of the operational amplifier is adjusted downwards, and correction of the baseline drift voltage is achieved.
The digital processing module controls the charge pump module to output different control voltages, and the voltages control the magnitude of the compensation current in the baseline wandering module to finish the correction of the baseline wandering of the input signals. The circuit judges and compensates signal direct current and low-frequency attenuation caused by the high-pass characteristic of the isolation transformer, corrects baseline drift in signal transmission and improves the noise tolerance of the circuit.
The digital processing module sends a control signal to the charge pump module, the charge pump module is controlled by digital logic to output different control voltages, and the voltages control the magnitude of compensation current in the baseline drift correction module; the baseline drift correction module is realized in the analog circuit, so that the design difficulty of the analog circuit is reduced, the dynamic input range of the ADC is not sacrificed, and the baseline drift correction range of the circuit is improved.
Those skilled in the art will appreciate that those matters not described in detail in this specification are well known in the art.
Claims (6)
1. A baseline wander voltage correction circuit for a portal chip, comprising: the device comprises a common-mode adjustment module, a comparator module, a digital processing module, a charge pump module, a voltage-controlled current source module and a baseline drift correction module;
a common mode adjustment module: receiving a differential signal input on a twisted pair wire, adjusting the differential signal to the input range of a comparator through common mode adjustment, and outputting the adjusted differential signal to a comparator module;
a comparator module: the height of the positive end and the height of the negative end of the differential signal are compared to obtain a square wave with a certain duty ratio, and the square wave is output to a digital processing module;
a digital processing module: according to the duty ratio of the square wave signal output by the comparator, judging the baseline voltage drift condition of the input differential signal on the twisted pair, obtaining a charge pump control signal according to the baseline voltage drift condition, and outputting the charge pump control signal to the charge pump module;
a charge pump module: the charge pump capacitor is charged or discharged according to a charge pump control signal output by the digital processing module, and the voltage on the charge pump capacitor is output to the voltage-controlled current source module;
a voltage-controlled current source module: adjusting the output current by comparing the output voltage of the charge pump module with the reference voltage value, and sending the adjusted output current to the baseline drift correction module;
a baseline drift correction module: the current sent by the voltage-controlled current source module is utilized to carry out current mirroring, compensation current is generated according to the mirrored current, and the common-mode voltage of the input differential signal on the twisted pair is adjusted according to the compensation current, so that the correction of the voltage drift of the input differential signal baseline on the twisted pair is realized.
2. The baseline wander voltage correction circuit of claim 1, wherein: the implementation method for obtaining the charge pump control signal by the digital processing module is as follows:
when the duty ratio of the square wave signal output by the comparator is more than 50%, the base line voltage of the input differential signal on the twisted pair wire drifts to the positive end, and the charge pump control signal is a discharge signal;
when the duty ratio of the square wave signal output by the comparator is less than 50%, the baseline voltage of the input differential signal on the twisted pair wire drifts to the negative end, and the charge pump control signal is a charging signal.
3. The baseline wander voltage correction circuit of claim 2, wherein: the charge pump module comprises a current source IUPA current source IDNMOS transistor M1, MOS transistor M2 and capacitor C1;
grid end of MOS transistor M1 and digital processing module inputThe output charging signal is connected, and the source end of the MOS transistor M1 is connected with the current source IUPThe drain terminal of the MOS transistor M1 is connected with the drain terminal of the MOS transistor M2 and one end of the capacitor C1, the gate terminal of the MOS transistor M2 is connected with the discharge signal output by the digital processing module, the source terminal of the MOS transistor M2 is connected with the current source IDNIs connected to a current source IDNIs connected to the other end of the capacitor C1, a current source IUPInput terminal of MOS transistor M1 and drain terminal of MOS transistor M1 and current source IDNThe output terminals of the charge pump module are used as three output terminals of the charge pump module and used for outputting voltage to the voltage-controlled current source module.
4. The baseline wander voltage correction circuit of claim 3, wherein: the voltage-controlled current source module comprises an MOS tube M3, an MOS tube M4 and a current source I0A current source I1A current source I2A current source I3And a resistance RS；
Current source I1And a current source I2The input end of the charge pump module is simultaneously connected with the current source I of the charge pump moduleUPInput terminal connected to a current source I1The output end of the MOS tube M3 is connected with the drain end of the MOS tube M3, the gate end of the MOS tube M3 is connected with the drain end of the MOS tube M1 of the charge pump module, and the source end of the MOS tube M3 is connected with the current source I0Is connected to a current source I2The output end of the MOS tube M4 is connected with the drain end of the MOS tube M4, the gate end of the MOS tube M4 is connected with the reference voltage, and the source end of the MOS tube M4 is connected with the current source I3Is connected to a current source I0Output terminal and current source I3The output end of the charge pump module is simultaneously connected with the current source I of the charge pump moduleDNThe output end is connected; resistance RSIs connected between the source terminal of the MOS transistor M3 and the source terminal of the MOS transistor M4.
5. The baseline wander voltage correction circuit of claim 4, wherein: the current source I0A current source I1A current source I2And a current source I3Current I in0、I1、I2、I3Satisfy I1+I2＝I0+I3，I0＝I3。
6. The baseline wander voltage correction circuit of claim 5, wherein: the baseline drift correction module comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a capacitor C2 and a current source I11A current source I21A current source I12A current source I22A current source Ib11And a current source Ib12；
The non-inverting input terminal of the operational amplifier U1 is connected with one terminal of the resistor R1 and the current source Ib11Is connected with one end of a resistor R3, the other end of a resistor R1 is connected with a positive differential signal input on a twisted pair, and a current source Ib11The output end of the resistor R3 is connected with the non-inverting input end of the operational amplifier U2, and the other end of the resistor R3 is connected with the positive output end of the operational amplifier U1; the inverting input terminal of the operational amplifier U1 is connected to one terminal of the resistor R2 and the current source Ib12Is connected with one end of a resistor R4, the other end of a resistor R2 is connected with a negative differential signal input on a twisted pair, and a current source Ib12The output end of the resistor R4 is connected with the non-inverting input end of the operational amplifier U3, and the other end of the resistor R4 is connected with the negative output end of the operational amplifier U1; the positive and negative output ends of the operational amplifier U1 are used for outputting a differential signal after baseline drift correction;
current source I11And a current source I12For current source I in voltage-controlled current source module1Mirror image of, current source I21And a current source I22For current source I in voltage-controlled current source module2Mirror image of, current source I11A current source I21A current source I12And a current source I22Are interconnected by a current source I11The output end of the operational amplifier is simultaneously connected with the non-inverting input end of the operational amplifier U2, the drain end of the MOS tube M5 and the drain end of the MOS tube M6, and the current source I21The output end of is the same asIs connected with the drain terminal of the MOS transistor M7 and the gate terminal of the MOS transistor M10, and a current source I12The output end of the current source I is simultaneously connected with the drain end of the MOS tube M8 and the gate end of the MOS tube M1222The output end of the operational amplifier U2 and the inverting input end of the operational amplifier U3 are connected to the drain end of the MOS tube M9, the drain end of the MOS tube M14 and the non-inverting input end of the operational amplifier U3, the inverting input end of the operational amplifier U2 and the inverting input end of the operational amplifier U3 are connected to the reference voltage VCM, the output end of the operational amplifier U2 is connected to the gate end of the MOS tube M5, one end of the capacitor C2, the gate end of the MOS tube M14 and the output end of the operational amplifier U3, the gate end of the MOS tube M6, the gate end of the MOS tube M7, the gate end of the MOS tube M8 and the gate end of the MOS tube M9, the source end of the MOS tube M5, the source end of the MOS tube M10, the source end of the MOS tube M11, the source end of the MOS tube M912, the source end of the MOS tube M13, the source end of the MOS tube M14 and the other end of the capacitor C2 are connected together, the drain end of the MOS tube M6 is connected to the drain end of the MOS tube M10, the drain end of, the source end of the MOS transistor M9 is connected with the drain end of the MOS transistor M13, the gate end of the MOS transistor M10 is connected with the gate end of the MOS transistor M11, and the gate end of the MOS transistor M12 is connected with the gate end of the MOS transistor M13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710547130.0A CN107483044B (en) | 2017-07-06 | 2017-07-06 | Baseline drift voltage correction circuit for network port chip |
Applications Claiming Priority (1)
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| CN201710547130.0A CN107483044B (en) | 2017-07-06 | 2017-07-06 | Baseline drift voltage correction circuit for network port chip |
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| CN107483044B true CN107483044B (en) | 2020-08-04 |
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| TWI725327B (en) * | 2018-07-19 | 2021-04-21 | 智原科技股份有限公司 | Apparatus for performing baseline wander correction |
| CN113497603B (en) * | 2020-04-01 | 2023-09-19 | 智原微电子(苏州)有限公司 | Device for baseline wander correction by means of differential wander current sensing |
| CN113590515B (en) * | 2021-07-23 | 2022-09-27 | 上海锐星微电子科技有限公司 | Signal transmission loss compensation circuit, integrated circuit and transmission system |
| CN113836071B (en) * | 2021-11-26 | 2022-02-22 | 苏州浪潮智能科技有限公司 | Self-correcting circuit and signal self-correcting method |
| CN115328247B (en) * | 2022-08-16 | 2023-11-24 | 骏盈半导体(上海)有限公司 | Power supply module and voltage stabilizing circuit |
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| CN102073332A (en) * | 2010-12-28 | 2011-05-25 | 华东师范大学 | Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator |
| CN202711106U (en) * | 2012-05-30 | 2013-01-30 | 西安航天民芯科技有限公司 | Linear voltage regulator with internally-installed compensation capacitor |
| CN104656732A (en) * | 2014-12-31 | 2015-05-27 | 格科微电子（上海）有限公司 | Voltage reference circuit |
| CN106411269A (en) * | 2016-12-07 | 2017-02-15 | 桂林电子科技大学 | Current feedback type instrument amplifier with low power consumption and low noise |
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| CN102073332A (en) * | 2010-12-28 | 2011-05-25 | 华东师范大学 | Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator |
| CN202711106U (en) * | 2012-05-30 | 2013-01-30 | 西安航天民芯科技有限公司 | Linear voltage regulator with internally-installed compensation capacitor |
| CN104656732A (en) * | 2014-12-31 | 2015-05-27 | 格科微电子（上海）有限公司 | Voltage reference circuit |
| CN106411269A (en) * | 2016-12-07 | 2017-02-15 | 桂林电子科技大学 | Current feedback type instrument amplifier with low power consumption and low noise |
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