CN111969964B - Semiconductor operational amplifier and semiconductor sensing device - Google Patents
Semiconductor operational amplifier and semiconductor sensing device Download PDFInfo
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- CN111969964B CN111969964B CN202011142199.3A CN202011142199A CN111969964B CN 111969964 B CN111969964 B CN 111969964B CN 202011142199 A CN202011142199 A CN 202011142199A CN 111969964 B CN111969964 B CN 111969964B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
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Abstract
Semiconductor operational amplification devices and semiconductor sensing devices are described herein. The semiconductor operational amplifier device includes: a main operational amplification circuit comprising a first bipolar junction transistor and a second bipolar junction transistor configured to receive a differential input signal; and an input current compensation circuit comprising a third bipolar junction transistor, a clamping operational amplifier and a current mirror. The clamping operational amplifier is configured to operate the third bipolar junction transistor at the same bias as the first bipolar junction transistor and the second bipolar junction transistor. A current mirror is coupled between the first node and the bases of the first, second, and third bipolar junction transistors, and the current mirror is configured to provide bias currents proportional to one another to the bases of the first, second, and third bipolar junction transistors, respectively. The semiconductor operational amplifier device realizes low-noise amplification of a weak input signal with high precision.
Description
Technical Field
Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly, to a low-noise operational amplification apparatus with low input current under a BiCMOS process and a sensing apparatus.
Background
High precision sensors typically require processing of weak current signals. High-precision sensors include, for example, optical observation sensors, which require the use of a current-to-voltage converter to amplify the weak current signal of the photodiode into a voltage signal that can be subsequently processed. The current-to-voltage converter is generally composed of a low noise operational amplifier having a low input leakage current or input bias current and a resistor.
In CMOS processes, low noise operational amplifiers are typically implemented using Chopper technology (Chopper) or self-zeroing technology (AZ). However, both techniques produce output ripple and introduce input leakage current at the input terminals of the operational amplifier. The input leakage current brings about a performance deterioration effect for the processing of the weak current signal. In a BiCMOS process, the low noise operational amplifier includes a low noise Bipolar Junction Transistor (BJT). However, due to the limited current amplification factor β of the bipolar junction transistor, there is an input leakage current or bias current at the input terminal of the operational amplifier.
In the conventional scheme disclosed in CN206671935U, current copy mirror compensation is performed on the input leakage current of an operational amplifier of a bipolar junction transistor architecture. In this scheme, the matching degree of the image compensation current is easily changed along with the change of the input common mode of the operational amplifier and the power supply voltage, so that the input residual leakage current is changed. In addition, this scheme employs a CMOS current mirror to compensate for the input leakage current of the operational amplifier, which deteriorates the noise figure of the operational amplifier.
It is desirable to provide an operational amplifier of an improved bipolar junction transistor architecture with improved input leakage current compensation accuracy.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor operational amplification apparatus and a semiconductor sensing apparatus having improved input leakage current compensation accuracy and capable of realizing low-noise amplification of a weak input signal with high accuracy.
In a first aspect, there is provided a semiconductor operational amplification apparatus comprising: a primary operational amplification circuit comprising a first bipolar junction transistor and a second bipolar junction transistor configured to receive a differential input signal, and configured to amplify the differential input signal to generate an amplified signal; and an input current compensation circuit comprising: a third bipolar junction transistor; a clamping operational amplifier having a non-inverting input terminal coupled to the emitters of the first and second bipolar junction transistors, an inverting input terminal coupled to the emitter of the third bipolar junction transistor, and an output terminal coupled to a first node, and configured to operate the third bipolar junction transistor at the same bias as the first and second bipolar junction transistors; a current mirror coupled between the first node and the bases of the first, second, and third bipolar junction transistors, and configured to provide bias currents proportional to one another to the bases of the first, second, and third bipolar junction transistors, respectively.
In some embodiments, the current mirror comprises: a fourth bipolar junction transistor comprising an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the third bipolar junction transistor; a fifth bipolar junction transistor comprising an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the first bipolar junction transistor; and a sixth bipolar junction transistor comprising an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the second bipolar junction transistor.
In some embodiments, the current mirror further comprises a buffer comprising an input terminal coupled to the collector of the fourth bipolar junction transistor and an output terminal coupled to the second node, and the buffer is configured to drive the bases of the fourth, fifth, and sixth bipolar junction transistors.
In some embodiments, a current flowing through the third bipolar junction transistor is in a first proportion to a current flowing through each of the first and second bipolar junction transistors, and a current flowing through the fourth bipolar junction transistor is in a second proportion to a current flowing through each of the fifth and sixth bipolar junction transistors, the first proportion being equal to the second proportion.
In some embodiments, the main operational amplification circuit further comprises: a first transistor comprising a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to a collector of the first bipolar junction transistor, and a control terminal coupled to the second conduction terminal of the first transistor; a second transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a collector of the second bipolar junction transistor, and a control terminal coupled to a control terminal of the first transistor; and a first current source coupled between the emitters of the first and second bjts and a ground terminal.
In some embodiments, the input current compensation circuit further comprises: a third transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a collector of the third bipolar junction transistor, and a control terminal coupled to the second conduction terminal of the third transistor; and a second current source coupled between the emitter of the third bipolar junction transistor and the ground terminal.
In some embodiments, a current flowing through the third transistor is in a third proportion to a current flowing through each of the first transistor and the second transistor, the third proportion being equal to the first proportion, and a proportion of a current of the second current source to a current of the first current source is equal to a fourth proportion, the fourth proportion being equal to half of the first proportion.
In some embodiments, the buffer comprises: a fourth transistor comprising a control terminal coupled to a collector of the fourth bipolar junction transistor; a fifth transistor comprising a control terminal coupled to the second node, and a second conduction terminal coupled to the second node; a sixth transistor comprising a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to a second conduction terminal of the fourth transistor, and a control terminal coupled to the second conduction terminal of the sixth transistor; a seventh transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a second conduction terminal of the fifth transistor, and a control terminal coupled to a control terminal of the sixth transistor; and a third current source coupled between the first conduction terminals of the fourth and fifth transistors and the ground terminal.
In some embodiments, the clamp operational amplifier comprises a cascode amplifier.
In some embodiments, the semiconductor operational amplification apparatus further comprises: an output stage configured to receive the amplified signal from the main operational amplification circuit and output the amplified signal as an output signal of the semiconductor operational amplification apparatus.
In a second aspect, there is provided a semiconductor sensing device comprising: the semiconductor operational amplifier device as described above; a sense element coupled between a non-inverting input terminal and an inverting input terminal of the semiconductor operational amplification device; and a resistor coupled between an output terminal of the semiconductor operational amplification device and the inverting input terminal.
In some embodiments, the sensing element comprises a photodiode, an anode of the photodiode is coupled to the inverting input terminal, and a cathode of the photodiode is coupled to a system common mode terminal.
According to the embodiment of the present disclosure, the operating point of the bipolar junction transistor as the mirror device in the input current compensation circuit and the operating point of the bipolar junction transistor as the differential pair device in the main operational amplification circuit are kept at the same bias. In this way, ideal replication of the operating current can be achieved, accurate input current compensation is achieved, and low-noise amplification of weak input signals can be achieved with high accuracy.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings. In exemplary embodiments of the present disclosure, like reference numerals generally represent like parts.
Fig. 1 is a block diagram illustrating a semiconductor operational amplification apparatus according to an embodiment of the present disclosure.
Fig. 2 is a circuit schematic diagram illustrating a semiconductor operational amplification apparatus according to an embodiment of the present disclosure.
Fig. 3 is a circuit schematic illustrating a buffer according to an embodiment of the present disclosure.
Fig. 4 is a circuit schematic illustrating a clamped operational amplifier according to an embodiment of the present disclosure.
Fig. 5 is a circuit schematic diagram illustrating a semiconductor sensing device according to an embodiment of the present disclosure.
Detailed Description
Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned above, the conventional scheme of the operational amplifier of the bipolar junction transistor architecture has the problems of the variation of the input residual leakage current and the noise degradation of the operational amplifier.
At least to address the above issues, embodiments of the present disclosure provide improvements to operational amplifiers of bipolar junction transistor architecture. The semiconductor operational amplification apparatus according to the embodiment tracks an input common mode voltage of a main operational amplifier by a clamp operational amplifier, makes an operating point of three terminals of a transistor in an input current compensation circuit follow an operating point of three terminals of a pair of differential input transistors in the main operational amplifier, and makes the transistor mirror each transistor of the pair of differential input transistors to achieve accurate input current compensation. In addition, the semiconductor operational amplifier device according to the embodiment drives the transistor in the leakage current mirror through the 1-time input buffer, thereby avoiding the influence of the limited current amplification factor of the transistor in the current mirror on the leakage current mirror accuracy. In this way, the input current compensation precision of the semiconductor operational amplifier device is improved, the influence of process voltage temperature deviation (PVT) on leakage current compensation is overcome, meanwhile, the deterioration of the input current compensation circuit on operational amplifier noise is reduced, and the low-noise amplification of weak input signals is realized with high precision.
Example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a block diagram illustrating a semiconductor operational amplification apparatus 100 according to an embodiment of the present disclosure. As shown in fig. 1, the semiconductor operational amplifier device 100 includes a main operational amplifier circuit 102 and an input current compensation circuit 104.
The main operational amplification circuit 102 is configured to receive a differential input signal and amplify the received differential input signal to generate an amplified signal. The semiconductor operational amplification apparatus 100 includes an inverting input terminal V-and a non-inverting input terminal V + as differential input terminals. The main operational amplification circuit 102 receives signals supplied from the outside via differential input terminals V-and V +. In some embodiments, the main operational amplification circuit 102 receives current signals via differential input terminals V + and V-.
The main operational amplification circuit 102 includes a differential input pair of Bipolar Junction Transistors (BJTs) configured to receive a differential input signal, including a first bipolar junction transistor and a second bipolar junction transistor. The bases of the first and second bipolar junction transistors are coupled to differential input terminals V-and V +, respectively. The main operational amplifier circuit 102 uses bipolar junction transistors as a differential input pair to achieve low noise amplification. Due to the finite amplification factor β of the bipolar junction transistor, there is an input leakage current or input bias current at the base of the bipolar junction transistor. In application, it is undesirable to draw leakage current from the differential input terminals V-and V + of the main operational amplification circuit 102.
The input current compensation circuit 104 is configured to compensate for input leakage currents at the bases of the first and second bjts. Input current compensation circuit 104 provides input leakage to the bases of the first and second bjts such that the first and second bjts do not draw input leakage from differential input terminals V-and V +. In this way, even if the semiconductor operational amplification apparatus 100 receives a weak current signal, the semiconductor operational amplification apparatus 100 can process the weak current signal with high accuracy.
The input current compensation circuit 104 includes a third bipolar junction transistor. The input current compensation circuit 104 is configured to keep the operating point of the third bjt the same as the operating points of the first bjt and the second bjt. The input current compensation circuit 104 mirrors the operating current of the first and second bjts to the third bjt. The input current compensation circuit 104 is configured to operate the third bjt at the same bias as the first bjt and the second bjt. In this way, the input current compensation circuit 104 achieves accurate current compensation for the input leakage currents of the first and second bjts.
In some embodiments, the semiconductor operational amplification apparatus 100 may further include an output stage circuit 106. The output stage circuit 106 is configured to receive the amplified signal from the main operational amplification circuit 102 and output the amplified signal as an output signal of the semiconductor operational amplification apparatus. The output stage circuit 106 can output the amplified signal received from the main operational amplifier circuit 102 from the semiconductor operational amplifier device 100 via the output terminal Vout.
Fig. 2 is a circuit schematic diagram illustrating the semiconductor operational amplification apparatus 100 according to an embodiment of the present disclosure. The circuit diagram shown in fig. 2 is only one example of the semiconductor operational amplification apparatus 100, and the semiconductor operational amplification apparatus 100 is not limited to the circuit diagram of fig. 2, in which some components may be equivalently replaced by other components.
Referring to fig. 2, the main operational amplification circuit 102 includes a first bjt T1 and a second bjt 2 configured to receive differential inputs. The bases of first and second bipolar junction transistors T1 and T2 are coupled to differential input terminals V-and V +, respectively.
The input current compensation circuit 104 includes a third bipolar junction transistor T3, a clamping operational amplifier a1, and a current mirror.
The clamping operational amplifier a1 has a non-inverting input terminal coupled to the emitters of the first and second bjts T1 and T2, an inverting input terminal coupled to the emitter of the third bjt T3, and an output terminal coupled to the first node VE.
Node VX is coupled to the emitters of the first and second BJT T1, T2, and node VY is coupled to the emitter of the third BJT T3. The clamping operational amplifier a1 is configured such that the voltage of node VX and the voltage of node VY remain the same. In this way, the clamping operational amplifier a1 is configured such that the voltage of the emitter of the third bjt T3 remains the same as the voltage of the emitters of the first bjt T1 and the second bjt 2.
A current mirror is coupled between the first node VE and the bases of the first, second, and third bjts T1, T2, and T3. The current mirror includes a first leg coupled between the first node VE and the base of the first bjt T1, a second leg coupled between the first node VE and the base of the second bjt T2, and a third leg coupled between the first node VE and the base of the third bjt T3.
In some embodiments, the current mirror includes a fourth bipolar junction transistor T4, a fifth bipolar junction transistor T5, and a sixth bipolar junction transistor T6. In the third branch, a fourth bjt T4 includes an emitter coupled to the first node VE, a base coupled to the second node VB, and a collector coupled to the base of the third bjt T3. In the first branch, the fifth bjt T5 includes an emitter coupled to the first node VE, a base coupled to the second node VB, and a collector coupled to the base of the first bjt T1. Further, in the second branch, the sixth bjt T6 includes an emitter coupled to the first node VE, a base coupled to the second node VB, and a collector coupled to the base of the second bjt T2.
The current mirror is configured to provide an input bias current or an input leakage current to the bases of the first, second, and third bjts T1, T2, and T3, respectively. The current flowing through the fourth, fifth and sixth bjts T4, T5 and T6 in the current mirror is input to the bases of the third, first and second bjts T3, T1 and T2, respectively. These currents in the current mirror are proportional to each other.
The first node VE, which is coupled to the output terminal of the clamping operational amplifier a1, provides the required input current. The current flowing from the first node VE to the bases of the first and second bjts T1 and T2 via the fifth and sixth bjts T5 and T6 compensates for the input leakage current or the input bias current. The input leakage currents of the first bjt T1 and the second bjt 2 are mirrored to the base of the third bjt T3 by a mirroring method via the fourth bjt T4 in the current mirror.
In other words, the clamping operational amplifier a1 is configured to operate the third bjt T3 at the same bias as the first bjt T1 and the second bjt 2. The clamping operational amplifier a1 is configured to keep the operating point of the third bjt T3 the same as the operating points of the first bjt 1 and the second bjt 2. The clamp operational amplifier a1 achieves good replication. The operation state of the third bjt T3 is consistent with the operation states of the first bjt 1 and the second bjt 2 through node voltage replication. Good uniformity can be maintained regardless of supply voltage, input common mode, and even process variations. The input leakage current is sunk from the fifth and sixth bjts T5 and T6 without additional sinking from the differential input terminals V-and V +, thereby compensating for the input leakage current.
Since the common mode currents at terminals V-and V + are unknown, it is difficult to ensure that the operating point of the third BJT T3 coincides with the operating points of the first BJT T1 and the second BJT T2 without clamping the operational amplifier A1. The node VY, the clamping operational amplifier a1, the first node VE, the fourth bjt T4, and the third bjt T3 form a negative feedback loop. If the voltage of the node VY is reduced, the voltage of the first node VE is pulled up, the voltage of the node VC is pulled up, and the voltage of the node VY is pulled up, so that negative feedback automatic regulation is realized. In this way, it can be ensured that the input current at the base of the third bjt T3 follows the input current at the bases of the first bjt T1 and the second bjt 2. In some embodiments, the input current at the base of the third bjt T3 is the same as the input current at the bases of the first bjt T1 and the second bjt 2. In this way, the input leakage current at the bases of the first and second bjts T1 and T2 can be compensated.
In some embodiments, the current mirror may also include a buffer B1. The buffer B1 includes an input terminal coupled to the collector of the fourth bjt T4, and an output terminal coupled to the second node VB. The buffer B1 is configured to drive the bases of the fourth, fifth, and sixth bipolar junction transistors T4, T5, and T6.
Since buffer B1 is coupled between node VC and second node VB, the input current at the base of third bjt T3 is sourced entirely from the current flowing through fourth bjt 4. In some embodiments, the collector currents of the fourth bjt T4, the fifth bjt T5, and the sixth bjt T6 are identical, and the collector current of the fourth bjt T4 is equal to the input current at the base of the third bjt T3, thereby completely compensating for the input currents at the bases of the first bjt T1 and the second bjt T2.
If the current mirror uses a metal oxide field effect transistor (MOS), noise still exists therein and is fed back to the input terminal of the operational amplifier. If the current mirror employs a bipolar junction transistor, a set buffer B1 is added. Without buffer B1, it is equivalent to node VC and second node VB being shorted, and the current at the base of third bjt T3 is split into two paths, one being the collector current of fourth bjt T4 and the other being the sum of the base currents of fourth bjt T4, fifth bjt 5 and sixth bjt T6. Therefore, the collector currents of the fourth bjt T4, the fifth bjt T5 and the sixth bjt T6 in the current mirror are not equal to the base current of the third bjt T3, that is, not equal to the base currents of the first bjt T1 and the second bjt T2, so that there is a compensation residue.
By providing the buffer B1, since the buffer B1 has no input current, the input current at the base of the third bjt T3 completely flows through the fourth bjt T4, which is mirrored and then equal to the input current at the bases of the first bjt T1 and the second bjt T2, thereby achieving accurate current compensation. Buffer B1 provides the drive source for fourth, fifth, and sixth BJT's T4, T5, T6, thereby avoiding drawing current from node VC to the bases of fourth, fifth, and sixth BJT's T4, T5, T6. In this way, by providing the buffer B1, an error in leakage current compensation is avoided.
In some embodiments, the current flowing through the third bjt T3 is in a first proportion to the current flowing through each of the first bjt T1 and the second bjt 2. In some embodiments, the first ratio is equal to 1. In addition, the current flowing through the fourth bjt T4 is in a second proportion to the current flowing through each of the fifth bjt T5 and the sixth bjt T6, the second proportion being equal to the first proportion. In this way, by scaling, the bias of the three terminals of the third bjt T3 follows the bias of the three terminals of the first bjt T1 and the second bjt 2 to achieve accurate input current compensation.
In some embodiments, the main operational amplification circuit 102 may further include a first transistor M1, a second transistor M2, and a first current source I1. The first transistor M1 includes a first conduction terminal coupled to the power supply node VDD, a second conduction terminal coupled to the collector of the first bjt T1, and a control terminal coupled to the second conduction terminal of the first transistor M1. The second transistor M2 includes a first conduction terminal coupled to the power supply node VDD, a second conduction terminal coupled to the collector of the second bjt 2, and a control terminal coupled to the control terminal of the first transistor T1. A first current source I1 is coupled between the emitters of the first and second BJT T1, T2 and the ground terminal VSS. In some embodiments, the first transistor M1 and the second transistor M2 may be metal oxide field effect transistors. In other embodiments, the first transistor M1 and the second transistor M2 may be bipolar junction transistors. The first transistor M1 and the second transistor M2 constitute a low-noise operational amplification means together with the first bjt T1 and the second bjt 2.
In some embodiments, the input current compensation circuit 104 may further include a third transistor M3 and a second current source I2. The third transistor M3 includes a first conduction terminal coupled to the power supply node VDD, a second conduction terminal coupled to the collector of the third bipolar junction transistor T3, and a control terminal coupled to the second conduction terminal of the third transistor M3. A second current source I2 is coupled between the emitter of the third bjt T3 and the ground terminal VSS. The first current source I1 and the second current source I2 may be two equal-ratio current sources generated by the same current mirror. The current flowing through the third transistor M3 is in a third proportion to the current flowing through each of the first transistor M1 and the second transistor M2, the third proportion being equal to the first proportion, and the proportion of the current of the second current source I2 to the current of the first current source I1 is equal to a fourth proportion, the fourth proportion being equal to half the first proportion. In this way, by providing the third transistor M3, the same bias voltage as the voltage of the collectors of the first and second bjts T1 and T2 can be supplied to the collector of the third bjt T3, thereby achieving good replication of the operating points of the first and second bjts T1 and T2 by the third bjt T3.
In some embodiments, the output stage 106 includes a transistor M0, a capacitor C0, and a current source I0 configured to receive the amplified signal from the collector of the second bjt 2 and output the amplified signal as an output signal of the semiconductor operational amplification device via an output terminal Vout.
According to the embodiment of the present disclosure, the input common mode voltage of the main operational amplification circuit is tracked by the clamping operational amplifier a1, so that the operating point of the third bjt T3 as a mirror device in the input current compensation circuit and the operating points of the first bjt T1 and the second bjt 2 as a differential pair device in the main operational amplification circuit are kept at the same bias, so as to achieve ideal replication of the operating current and accurate input current compensation. In addition, the 1-time input buffer B1 is adopted to drive the fourth bjt T4, the fifth bjt T5 and the sixth bjt T6 which form the leakage current mirror, so that the influence of the limited current amplification factor β on the leakage current mirror accuracy is avoided, and the high-accuracy operational amplifier input current compensation effect is realized. The noise of the buffer B1 in the input current compensation circuit is attenuated by the clamp operational amplifier a1, and does not have a degrading effect on the noise of the main operational amplifier circuit. In this way, an improved scheme of a low-noise semiconductor operational amplification device can be provided according to an embodiment of the present disclosure.
It should be understood that, although fig. 2 illustrates that the first, second, and third bjts T1, T2, and T3 are NPN-type transistors and the fourth, fifth, and sixth bjts T4, T5, and T6 are PNP-type transistors, embodiments according to the present disclosure are not limited thereto. In other embodiments, the first, second, and third bjts T1, T2, and T3 may be PNP type transistors and the fourth, fifth, and sixth bjts T4, T5, and T6 are NPN type transistors by changing the conductivity types of the first, second, and third transistors M1, M2, and M3.
Fig. 3 is a circuit schematic diagram illustrating a buffer B1 according to an embodiment of the present disclosure. Referring to fig. 3, the buffer B1 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a current source. In some embodiments, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be metal oxide field effect transistors.
The fourth transistor M4 includes a control terminal coupled to the collector of the fourth bipolar junction transistor T4 depicted in fig. 2. The fifth transistor M5 includes a control terminal coupled to the second node VB, and a second conduction terminal coupled to the second node VB. The sixth transistor M6 includes a first conduction terminal coupled to the power supply node VDD, a second conduction terminal coupled to the second conduction terminal of the fourth transistor M4, and a control terminal coupled to the second conduction terminal of the sixth transistor M6. The seventh transistor M7 includes a first conduction terminal coupled to the power supply node VDD, a second conduction terminal coupled to the second conduction terminal of the fifth transistor M5, and a control terminal coupled to the control terminal of the sixth transistor M6. The current source is coupled between the first conductive terminals of the fourth transistor M4 and the fifth transistor M5 and the ground terminal VSS.
A control terminal of the fourth transistor M4 serves as an input terminal of the buffer B1, and a control terminal of the fifth transistor M5 serves as an output terminal of the buffer B1. The voltage at the control terminal of the fourth transistor M4 remains the same as the voltage at the control terminal of the fifth transistor M5. In this way, the voltage at the collector and the voltage at the base of fourth bjt T4 are kept the same, so that fourth bjt T4 is turned on.
Fig. 4 is a circuit schematic illustrating a clamp operational amplifier a1 according to an embodiment of the present disclosure. As shown in fig. 4, the clamp operational amplifier a1 comprises a cascode amplifier. The clamp operational amplifier a1 may comprise any type of cascode amplifier known in the art.
Referring to fig. 4, the clamping operational amplifier a1 includes eighth to seventeenth transistors M8 to M17. The eighth transistor M8, the ninth transistor M9, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 have the same conductivity type. The tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 have the same conductivity type.
A control terminal of the eighth transistor M8 is coupled to the terminal VX in fig. 2, and a control terminal of the ninth transistor M9 is coupled to the terminal VY in fig. 2. The current source I3 is coupled between the first conduction terminals of the eighth transistor M8 and the ninth transistor M9 and the power supply node VDD. The tenth transistor M10, the twelfth transistor M12, the fourteenth transistor M14, and the sixteenth transistor M16 are coupled in series between the ground node VSS and the power supply node VDD. The eleventh transistor M11, the thirteenth transistor M13, the fifteenth transistor M15, and the seventeenth transistor M17 are coupled in series between the ground node VSS and the power supply node VDD. Control terminals of the tenth, twelfth, fourteenth and sixteenth transistors M10, M12, M14 and M16 are coupled to control terminals of the eleventh, thirteenth, fifteenth and seventeenth transistors M11, M13, M15 and M17, respectively. A first conduction terminal of the sixteenth transistor M16 is coupled to the power supply node VDD, and a control terminal of the sixth transistor M16 is coupled to a second conduction terminal of the fourteenth transistor M14. First conductive terminals of the tenth transistor M10 and the eleventh transistor M11 are coupled to the ground terminal VSS. Second conduction terminals of the eighth transistor M8 and the ninth transistor M9 are coupled to second conduction terminals of the tenth transistor M10 and the eleventh transistor M11, respectively.
Control terminals of the eighth transistor M8 and the ninth transistor M9 serve as differential inputs to the clamp operational amplifier a 1. In this way, the voltage at the collector of the third bjt T3 and the voltages at the collectors of the first bjt T1 and the second bjt T2 are clamped to the same level to achieve the operating point duplication.
Fig. 5 is a circuit schematic diagram illustrating a semiconductor sensing device 500 according to an embodiment of the present disclosure.
The semiconductor sensing device 500 includes a current-to-voltage converter and a sensing element. The current-voltage converter includes a low-noise semiconductor operational amplification device 100 and a resistor R1. The sensing element is coupled between the non-inverting input terminal V + and the inverting input terminal V-of the semiconductor operational amplification apparatus 100. The resistor R1 is coupled between the output terminal Vout and the inverting input terminal V-of the semiconductor operational amplification device 100.
In some embodiments, the sensing element comprises a photodiode D1. The anode of photodiode D1 is coupled to the inverting input terminal V-, and the cathode of photodiode D1 is coupled to the non-inverting input terminal V +. The non-inverting input terminal V + is coupled to the system common mode terminal.
The current-voltage converter amplifies the weak current signal of the photodiode D1 into a voltage signal that can be processed subsequently. The voltage signal is transmitted to an external device via the output terminal Vs of the semiconductor sensing device 500.
In the semiconductor operational amplification apparatus 100, the input leakage current has been compensated. In this way, the input leak current Is not supplied from the current Is flowing through the photodiode D1, so that the weak current signal Is can be processed with high accuracy.
According to the embodiment of the present disclosure, the operating point of the bipolar junction transistor as the mirror device in the input current compensation circuit and the operating point of the bipolar junction transistor as the differential pair device in the main operational amplification circuit are kept at the same bias. In this way, ideal replication of the operating current can be achieved, accurate input current compensation is achieved, and low-noise amplification of weak input signals can be achieved with high accuracy.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A semiconductor operational amplification apparatus comprising:
a primary operational amplification circuit comprising a first bipolar junction transistor and a second bipolar junction transistor configured to receive a differential input signal, and configured to amplify the differential input signal to generate an amplified signal; and
an input current compensation circuit comprising:
a third bipolar junction transistor;
a clamping operational amplifier having a non-inverting input terminal coupled to the emitters of the first and second bipolar junction transistors, an inverting input terminal coupled to the emitter of the third bipolar junction transistor, and an output terminal coupled to a first node, and configured to operate the third bipolar junction transistor at the same bias as the first and second bipolar junction transistors;
a current mirror, comprising:
a fourth bipolar junction transistor having an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the third bipolar junction transistor;
a fifth bipolar junction transistor having an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the first bipolar junction transistor; and
a sixth bipolar junction transistor having an emitter coupled to the first node, a base coupled to the second node, and a collector coupled to the base of the second bipolar junction transistor, and
the current mirror is configured to provide bias currents proportional to each other to the bases of the first, second, and third bipolar junction transistors, respectively;
a buffer having an input terminal coupled to the collector of the fourth bipolar junction transistor and an output terminal coupled to the second node, and the buffer configured to drive the bases of the fourth, fifth, and sixth bipolar junction transistors; and
a third transistor comprising a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to a collector of the third bipolar junction transistor, and a control terminal coupled to the second conduction terminal of the third transistor.
2. The semiconductor operational amplification device of claim 1, wherein a current flowing through the third bipolar junction transistor is in a first proportion to a current flowing through each of the first and second bipolar junction transistors, and a current flowing through the fourth bipolar junction transistor is in a second proportion to a current flowing through each of the fifth and sixth bipolar junction transistors, the first proportion being equal to the second proportion.
3. The semiconductor operational amplification apparatus according to claim 2, wherein the main operational amplification circuit further comprises:
a first transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a collector of the first bipolar junction transistor, and a control terminal coupled to the second conduction terminal of the first transistor;
a second transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a collector of the second bipolar junction transistor, and a control terminal coupled to a control terminal of the first transistor; and
a first current source coupled between the emitters of the first and second bipolar junction transistors and a ground terminal.
4. The semiconductor operational amplification apparatus according to claim 3, wherein the input current compensation circuit further comprises:
a second current source coupled between the emitter of the third bipolar junction transistor and the ground terminal.
5. The semiconductor operational amplification apparatus according to claim 4, wherein a current flowing through the third transistor is in a third proportion to a current flowing through each of the first transistor and the second transistor, the third proportion being equal to the first proportion, and a proportion of a current of the second current source to a current of the first current source is equal to a fourth proportion, the fourth proportion being equal to half of the first proportion.
6. The semiconductor operational amplification apparatus according to any one of claims 1 to 5, wherein the buffer comprises:
a fourth transistor comprising a control terminal coupled to a collector of the fourth bipolar junction transistor;
a fifth transistor comprising a control terminal coupled to the second node, and a second conduction terminal coupled to the second node;
a sixth transistor comprising a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to a second conduction terminal of the fourth transistor, and a control terminal coupled to the second conduction terminal of the sixth transistor;
a seventh transistor comprising a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to a second conduction terminal of the fifth transistor, and a control terminal coupled to a control terminal of the sixth transistor; and
a third current source coupled between the first conduction terminals of the fourth and fifth transistors and a ground terminal.
7. The semiconductor operational amplification device of any one of claims 1 to 5, wherein the clamp operational amplifier comprises a cascode amplifier.
8. The semiconductor operational amplification apparatus according to any one of claims 1 to 5, further comprising:
an output stage configured to receive the amplified signal from the main operational amplification circuit and output the amplified signal as an output signal of the semiconductor operational amplification apparatus.
9. A semiconductor sensing device, comprising:
the semiconductor operational amplification apparatus according to any one of claims 1 to 8;
a sense element coupled between a non-inverting input terminal and an inverting input terminal of the semiconductor operational amplification device; and
a resistor coupled between an output terminal of the semiconductor operational amplification device and the inverting input terminal.
10. The semiconductor sensing device of claim 9, wherein the sensing element comprises a photodiode, an anode of the photodiode is coupled to the inverting input terminal, and a cathode of the photodiode is coupled to a system common mode terminal.
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Address after: Room 501, 5 / F, building 4, No. 351, Changhe Road, Changhe street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Jinghua Microelectronics Co.,Ltd. Address before: Room 501, 5 / F, building 4, No. 351, Changhe Road, Changhe street, Binjiang District, Hangzhou City, Zhejiang Province Patentee before: HANGZHOU SDIC MICROELECTRONICS Co.,Ltd. |
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