CN217037143U

CN217037143U - Open-loop high-gain precision current amplification circuit based on BCD (binary coded decimal) process

Info

Publication number: CN217037143U
Application number: CN202123245830.5U
Authority: CN
Inventors: 唐毓尚; 王俊生; 刘俊; 朱正永; 李政; 彭俊; 周文质; 杨菲菲
Original assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Current assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2022-07-22
Anticipated expiration: 2031-12-22

Abstract

The utility model provides an open-loop high-gain precision current amplifier circuit based on BCD technology, relates to semiconductor integrated circuit, includes multistage current mirror image circuit, biasing circuit and amplifier circuit, still includes base current compensation circuit, base current compensation circuit comprises current sampling circuit and current mirror image circuit. The method adopts a base current compensation technology, constructs a proper bias circuit to ensure that the sampling current accurately compensates the base current of the triode, and reduces the influence of the base current on the gain precision. The problem of current gain low precision caused by the dependence of the existing current detection amplifier on the process and the poor performance of the triode in the BCD process is solved. The technical scheme of the utility model is widely applied to the current detection amplifier with current detection precision.

Description

Open-loop high-gain precision current amplification circuit based on BCD (binary coded decimal) process

Technical Field

The present invention relates to a semiconductor integrated circuit, particularly to a current amplification circuit, and more particularly to a current sense amplifier circuit.

Background

As shown in fig. 1, the current detection amplifier mainly comprises two parts, wherein the front stage is a current detection circuit, the rear stage is a current amplification circuit, the current amplification circuit is an important part of the current detection amplifier, and Qn is a single-tube amplification. The current detection circuit I R can be derived from FIG. 1₁＝I_LOAD*R_senseCurrent amplifying circuit I_OUTIn the current detection amplifier, the current accuracy determines the accuracy of the current detection amplifier, and the current amplification circuit configuration determines the current accuracy and thus the accuracy of the current detection amplifier. In the current detection amplifier, the accuracy of the current detection amplifier is difficult to improve by opening a loop current amplifying circuit. The utility model is provided for solving the problem that the current precision directly affects the gain precision of a current detection amplifier, and the influence of errors on the current precision needs to be reduced in order to improve the gain precision.

In the Chinese patent database, patents relating to the current amplifying circuit include a module power supply high-end current detection amplifying circuit with publication number of CN113740589A, a high-precision large-range current measuring system with publication number of CN113514690A, a weak current detection circuit of a nitrogen oxygen sensor with publication number of CN109239432A, and a micro current detection circuit with publication number of CN 106018926B. A weak current detection circuit and method is disclosed in the publication number CN 105548654A. However, no application for current amplification using the technical solution of the present invention has been available so far.

Disclosure of Invention

The utility model aims to solve the technical problems that: the problems that the existing current detection amplifier is low in current gain precision due to process dependence and poor performance of a triode in a BCD (bipolar transistor-coupled device) process are solved.

Therefore, the utility model provides an open-loop high-gain precision current detection amplifying circuit based on a BCD process, as shown in figures 2 and 3.

In the current amplifier circuit with a current mirror shown in fig. 2, K is first performed for the current I obtained at the previous stage₁The current is multiplied, the area ratio of the Q6 to the Q4 emitter is S_Q6∶S_Q4＝1∶K₁(K₁As a variable, the proportion can be adjusted according to the circuit requirements), the influence of the base currents of the Q6 and the Q4 on the current mirror can be reduced by adding the Q2; mirrored I_Q4＝K₁I, P2 as Q4 active load for realizing current K again₂Magnification, the ratio of P1 to P2 is NUM_P1∶NUM_P2＝K₂∶1(K₂The proportion can be adjusted according to circuit requirements), the influence of base voltage on current mirror images of P2 and P1 can be reduced by increasing P3, Q1 is increased, the base is connected to the collector of Q3, the potential clamping of the collector of Q3 is realized, Q3 and Q5 are used as voltage-withstanding tubes and are also used as a cascode circuit to improve circuit output impedance, and a branch of Q7 is a bias circuit of Q3 and Q5.

The current amplifying circuit shown in FIG. 2 can realize K₁*K₂The current amplification is multiplied, but the Q1 base current affects the current mirror accuracy. Therefore, on the basis of the current amplification circuit shown in fig. 2, a current sampling circuit and a base compensation circuit are added to form the current amplification circuit with base current compensation shown in fig. 3, so that the current is accurately amplified.

As for the current amplifying circuit with base current compensation shown in fig. 3, bias partial circuits Q8, Q10, Q13 and R4 are added, and Q7 is removed; q8 copies Q9 current, and Q10 reduces the influence of base current on mirror current; q13 and R4 are constant current source loads, P7 and P6 provide compensation current, and N1 and N2 realize compensation of Q1 base current.

Compared with the prior art, the utility model has the advantages that:

the BCD process is adopted, so that the area of a chip is reduced;

under the condition of poor performance of the triode, the performance equivalent to that of a bipolar process is realized;

the technical scheme of the utility model is widely applied to the current detection amplifier for current detection.

Drawings

Fig. 1 is a schematic diagram of a current sense amplifier.

Fig. 2 is a schematic diagram of a current amplifying circuit with a current mirror.

Fig. 3 is a schematic diagram of a current amplifying circuit with base current compensation.

In the figure: p1, P2, P3, P6 and P7 are PMOS tubes of the same type, N1 and N2 are NMOS tubes of the same type, Q1, Q3, Q5, Q8, Q9, Q10 and Q12 are PNP tubes of the same type, Q2, Q4, Q6, Q7, Q11 and Q13 are NPN tubes of the same type, and R1, R2, R3 and R4 are resistors of the same type.

Detailed Description

The specific embodiment is as follows:

1. the current amplifying circuit shown in fig. 2:

assuming that the current supplied by the front stage is I and the amplification factor of the PNP tube is beta, the area ratio of the emitters Q6 and Q4 is S_Q6∶S_Q4＝1∶K₁Then, I_Q4C＝K₁I and I_Q3C＝I_Q4C+I_Q1B，I_Q3C＝I_Q3BBeta, then I_Q3E＝I_Q3C+I_Q3BAnd the ratio of P2 to P1 is 1: K₂The ratio of Q3 to Q5 is also 1: K₂Then, I_Q5C＝K₂I_Q3CI.e. I_OUT＝K₂I_Q3C＝K₂(I_Q4C+I_Q1B)＝K₂(K₁I+I_Q1B)＝K₁K₂I+K₂I_Q1BRealizing a current of about K₁K₂And (4) magnification.

2. The current amplifying circuit shown in fig. 3:

because the current amplifying circuit shown in fig. 2 has an error caused by the base current of Q1, in order to eliminate the base current of Q1, current sampling needs to be accurately performed, the current amplifying circuit with base current compensation as shown in fig. 3 is added with a bias circuit Q8 branch, the emitter area ratio of constant current source loads Q11 and Q13 is S_Q11∶S_Q13＝K₃∶1(K₃As a variable, the ratio can be adjusted according to the circuit requirements), the emitter area ratio of Q9 and Q8 is S_Q9∶S_Q8＝K₃1, then I_Q11C＝K₃I_Q13C，I_Q9C＝K₃I_Q8CAnd is I_Q11C＝I_Q9C+(K₂+1)I_Q3B(due to I)_Q12E＝I_Q3BThen the base current is I_Q12B＝I_Q3BBeta, negligible), I_Q13C＝I_Q8C+I_P7Then, I_P7＝(K₂+1)I_Q3B/K₃The number ratios of P7 and P6 are NUM_P7∶NUM_P6＝(K₂+1)∶K₃Then the current P6 is I_Q3BAnd the ratio of the numbers N1 to N2 is NUM_N1∶NUM_N2At 3: 1, the current of N2 is I_Q3B(iii)/3, since the number ratio of P3 to P2 is NUM_P3∶NUM_P21: 3, the base current of Q1 is 1/3 (assuming β is unity) of the base current of Q3, i.e., I_Q3B/3. The current flowing through N2 is equal to the base current of Q1, and the compensation of the base current of Q1, namely I_OUT＝K₁K₂I。

The symbols involved in the formula illustrate:

I_XXXthe current of a certain port of a certain device is represented, wherein I represents a current symbol, the first X in subscript XXX represents a transistor symbol which is respectively Q (triode), N (NMOS tube) and P (PMOS tube), the second X represents a device number which is numbered as Arabic numerals 1, 2, 3 and the like, and the third X represents a device numberThe ports of (1) are respectively a collector (C), a base (B) and an emitter (E). I is_RXRepresents the current flowing through a certain resistor, wherein I represents the symbol of the current, R in subscript RX represents the symbol of the resistor, X represents the device number, the number is Arabic numerals 1, 2, 3, etc., wherein S represents the symbol of the emitter area, Q in subscript QX represents the symbol of the bipolar transistor, X represents the device number, the number is Arabic numerals 1, 2, 3, etc.; NUM represents the number of MOS tubes, N, P in subscripts NX and PX represents MOS tube symbols, X represents device numbers, and the numbers are Arabic numerals such as 1, 2, 3 and the like.

Finally, the above embodiments are merely illustrative of the technical solutions of the present invention and not restrictive, and although the present invention has been described in detail, it will be understood by those skilled in the art that various changes in structure and details may be made therein without departing from the scope of the utility model as defined by the appended claims.

Claims

1. An open-loop high-gain precision current amplification circuit based on a BCD (binary coded decimal) process is characterized by comprising a multi-stage current mirror circuit, a bias circuit and an amplification circuit, wherein the multi-stage current mirror circuit firstly carries out K on an input current I₁Amplifying the image current, and performing K₂And amplifying the mirror image current, inputting the amplified current into the amplifying circuit to improve the output impedance of the current output end, and providing voltage bias for the amplifying circuit by the bias circuit.

2. The open-loop high-gain precision current amplifying circuit based on the BCD process as claimed in claim 1, comprising PMOS tubes P1, P2 and P3 of the same type, NMOS tubes N1 and N2 of the same type, PNP tubes Q1, Q3 and Q5 of the same type, NPN tubes Q2, Q4, Q6, Q7 and Q11 of the same type, a resistor R3;

the collector of the NPN tube Q11 is connected with the emitter of the NPN tube Q7, the base of the PNP tube Q3 and the base of the PNP tube Q5; the collector of the NPN tube Q7 is connected to a positive power supply; the base electrodes of the NPN tube Q7 and the NPN tube Q11 are bias voltage ends; an emitter of the NPN tube Q11 is connected with a resistor R3, and the other end of the resistor R3 is connected to a negative power supply; the source ends of the PMOS tubes P3, P2 and P1 are connected to a positive power supply; the grid end of the PMOS tube P1 is connected with the grid end of the PMOS tube P2, the grid end and the drain end of the PMOS tube P3 and the emitting electrode of the PNP tube Q1; the collector electrode of the PNP tube Q1 is connected to a negative power supply; the base electrode of the PNP tube Q1 is connected with the collector electrode of the PNP tube Q3 and the collector electrode of the NPN tube Q4; the drain end of the PMOS tube P2 is connected with a PNP tube Q3 emitter stage; the drain end of the PMOS tube P1 is connected with the emitting stage of a PNP tube Q5; the base electrode of the NPN tube Q4 is connected with the emitter electrode of the NPN tube Q2 and the base electrode of the NPN tube Q6; the emitting stage of the NPN tube Q4 is connected with a negative power supply; the collector of the PNP tube Q5 is connected with the output end OUT; the emitter of the NPN tube Q6 is connected to a negative power supply; the collector of the NPN transistor Q6 and the base of the NPN transistor Q2 are connected to the previous stage; the collector of the NPN transistor Q2 is connected to the positive power supply.

3. The open-loop high-gain precision current amplification circuit based on BCD (binary-coded decimal) process as claimed in claim 2, wherein the area ratio of the Q6 to the Q4 emitters is S_Q6∶S_Q4=1∶K₁。

4. The BCD process-based open-loop high-gain precision current amplification circuit as claimed in claim 2, wherein the ratio of P2 to P1 is 1: K₂。

5. The BCD process-based open-loop high-gain precision current amplification circuit as claimed in claim 2, wherein the ratio of Q3 to Q5 is also 1: K₂。

6. The open-loop high-gain precision current amplification circuit based on the BCD process as claimed in claim 1, further comprising a base current compensation circuit, wherein the base current compensation circuit is composed of a current sampling circuit and a current mirror circuit.

7. The open-loop high-gain precision current amplification circuit based on the BCD process as claimed in claim 6, comprising PMOS tubes P1, P2, P3, P6 and P7 of the same type, NMOS tubes N1 and N2 of the same type, PNP tubes Q1, Q3, Q5, Q8, Q9, Q10 and Q12 of the same type, NPN tubes Q2, Q4, Q6, Q11 and Q13 of the same type, resistors R3 and R4 of the same type;

the collector of the PNP tube Q9 is connected with the collector of the NPN tube Q11, the base of the PNP tube Q10, the base of the PNP tube Q12, the base of the PNP tube Q3 and the base of the PNP tube Q5; the base electrode of the PNP tube Q9 is connected with the emitter electrode of the PNP tube Q10 and the base electrode of the PNP tube Q8; the emitter of the PNP pipe Q9 is connected to a positive power supply; the collector of the PNP tube Q10 is connected to a negative power supply; the base electrode of the NPN tube Q11 is connected with the base electrode of the NPN tube Q13 and is a bias voltage end, meanwhile, the emitter electrode of the NPN tube Q11 is connected with the resistor R3, the emitter electrode of the NPN tube Q13 is connected with the resistor R4, and the other ends of the resistors R3 and R4 are connected to a negative power supply; an emitter of the PNP tube Q8 is connected to a positive power supply, a collector of the Q8 is connected with a collector of the NPN tube Q13, a drain end and a gate end of the PMOS tube P7 and a gate end of the PMOS tube P6; the PMOS tubes P7 and P6 are connected to the positive power supply at the source ends; the drain end of the PMOS tube P6 is connected with the emitter of the PNP tube Q12; the collector end of the PNP tube Q12 is connected with the grid end of the NMOS tube N2, the drain end of the NMOS tube N1 and the grid end; the source ends of the NMOS tubes N1 and N2 are connected to a negative power supply; the PMOS tubes P3, P2 and P1 are connected to a positive power supply at the source ends; the grid end of the PMOS tube P1 is connected with the grid end of the PMOS tube P2, the grid end and the drain end of the PMOS tube P3 and the emitting electrode of the PNP tube Q1; the collector electrode of the PNP tube Q1 is connected to a negative power supply; the base electrode of the PNP tube Q1 is connected with the drain end of the NMOS tube N2, the collector electrode of the PNP tube Q3 and the collector electrode of the NPN tube Q4; the drain end of the PMOS tube P2 is connected with the emitting stage of a PNP tube Q3; the drain end of the PMOS tube P1 is connected with a PNP tube Q5 emitter stage; the base electrode of the NPN tube Q4 is connected with the emitter electrode of the NPN tube Q2 and the base electrode of the NPN tube Q6; the emitting stage of the NPN tube Q4 is connected with a negative power supply; the collector of the PNP tube Q5 is connected with the output end OUT; the emitter of the NPN tube Q6 is connected to a negative power supply; the collector of the NPN transistor Q6 and the base of the NPN transistor Q2 are connected to the previous stage; the collector of the NPN transistor Q2 is connected to the positive power supply.

8. The open-loop high-gain precision current amplifying circuit based on BCD process as claimed in claim 7, wherein the area ratio of the Q11 emitter to the Q13 emitter is S_Q11∶S_Q13=K₃∶1。

9. The method of claim 7The open-loop high-gain precision current amplification circuit based on the BCD process is characterized in that the area ratio of the emitting electrodes of Q9 and Q8 is S_Q9∶S_Q8=K₃∶1。

10. The open-loop high-gain precision current amplification circuit based on the BCD process of claim 7, wherein the number ratio of P3, P2 and P1 is NUM_P3∶NUM_P2∶NUM_P1=1∶3∶3K₂The number ratio of P7 to P6 is NUM_P7∶NUM_P6=(K₂+1 to 2, and the number ratio of N1 to N2 is NUM_N1∶NUM_N2=3∶1。