CN114513177B - Ultra-low bias current design method based on bipolar amplifier and circuit thereof - Google Patents
Ultra-low bias current design method based on bipolar amplifier and circuit thereof Download PDFInfo
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- CN114513177B CN114513177B CN202111654980.3A CN202111654980A CN114513177B CN 114513177 B CN114513177 B CN 114513177B CN 202111654980 A CN202111654980 A CN 202111654980A CN 114513177 B CN114513177 B CN 114513177B
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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Abstract
A bipolar amplifier-based ultra-low bias current design method and a circuit thereof relate to a semiconductor integrated circuit. The real-time sampling current elimination design method is adopted, and the amplifier circuit comprises a starting bias circuit, a common-emitter common-base differential input circuit and a base current compensation core circuit; the starting bias circuit enables the system to get rid of the constraint of a degeneracy point to normally work after the power supply is powered on, and provides a stable direct current bias point for the system after the starting is finished; the common-emitter common-base differential input circuit comprises the same type of ultra-beta NPN transistor differential pair, and realizes the functions of input signal amplification and double-rotation single-function; the base current compensation core circuit comprises a bias current monitoring circuit and a compensation circuit, and realizes input geminate transistor base current copying through a precise current mirror and negative feedback to realize base current synchronous compensation. The problems of overlarge input bias current and low weak signal processing precision of the conventional current operational amplifier are solved. The method is widely applied to the technical field of low-bias current operational amplifiers.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a bipolar semiconductor integrated circuit, and more particularly, to a method for designing an ultra-low bias current based on a bipolar amplifier and a circuit thereof.
Background
The bipolar operational amplifier is an important part of an analog integrated circuit, has excellent characteristics such as high transconductance current ratio, high gain, low noise, high linearity and the like, is widely applied to a weak signal processing circuit, and realizes operations such as addition, subtraction, multiplication, division and the like of signals. With the development of high-precision intelligent instruments and meters, the processing and operation of weak signals become necessary, and the operational amplifier is used as a core element of a signal processing circuit, plays a crucial role in the amplification of the weak signals, and the market demand is increasing. Therefore, the input bias current and the offset current of the amplifier have a greater and greater influence on the amplifier to process a weak signal, and therefore, the design technology of the ultra-low bias current operational amplifier becomes necessary to be developed.
In the ultra-low bias current operational amplifier, devices such as a CMOS and a JFET are generally used as input stages in the prior art, but compared with a bipolar device, the transconductance current ratio of a field effect transistor is significantly lower than that of the bipolar device, so that under the condition of the same power consumption, the circuit gain is significantly reduced, the linearity is also reduced, and the precision is insufficient when weak signals are processed. In addition, the base current cancellation technology is also adopted in the industry to reduce the bias current, but the base current after cancellation also stays at the nA level (namely, nanoAmp level) and cannot be reduced to the pA level (namely, picoAmp level).
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The purpose of the invention is: the problems that the input bias current of the existing low-bias current operational amplifier is overlarge and the processing precision of weak signals is low are solved.
The invention has the following inventive concept: a real-time sampling current elimination design method is adopted, a super beta NPN tube is used as an input tube of the common-emitter common-base differential input circuit, the input impedance is improved, and the input bias current is physically reduced; meanwhile, a base current compensation core circuit consisting of a bias circuit, a precise current mirror and a base current elimination circuit is adopted, on one hand, tail currents of the input differential pair are monitored and sampled in real time, on the other hand, the input bias current is compensated in real time through the precise current mirror, and the input bias current is eliminated through real-time sampling monitoring and real-time compensation of the input bias current, so that PA-level current input of the common-emitter common-base differential pair input tube is realized, and the common-emitter common-base differential input circuit has the excellent input characteristics of a bipolar device and the ultralow bias current characteristics of a CMOS device. Meanwhile, the temperature drift coefficient of the bias current is reduced, the bias current is kept almost unchanged in the range of the full temperature region, and the input characteristic of the device is close to idealization.
The schematic diagram of the ultra-low bias current bipolar amplifier circuit adopting the real-time sampling current elimination design method is shown in fig. 1. The circuit comprises a direct current power supply, a starting bias circuit, a base current compensation core circuit and a common-emitter common-base differential input circuit.
The direct-current power supply is connected with a starting bias circuit and a common-emitter common-base differential input circuit, the starting bias circuit is connected with the common-emitter common-base differential input circuit and a base current compensation core circuit, the base current compensation core circuit is in forward connection and reverse connection with the common-emitter common-base differential input circuit, and the common-emitter common-base differential input circuit is connected with an output end.
The starting bias circuit enables a system to get rid of the constraint of a degenerate point after a power supply is powered on to normally work, and provides a stable direct current bias point for the system after the starting is finished;
the common-emitter common-base differential input circuit comprises a same type of super beta NPN transistor differential pair which is used as a core input circuit with an input stage being an operational amplifier, and mainly realizes the amplification of input signals and a double-conversion single-ended function (namely a double-end input to single-end output function);
the base current compensation core circuit comprises a bias current monitoring circuit and a compensation circuit, input geminate transistor base current copying is achieved through a precise current mirror and negative feedback, the input geminate transistor base current copying is used for collecting input bias current and achieving base current synchronous compensation, and the input bias current of the bipolar operational amplifier is reduced to pA level.
As shown in fig. 2-5:
the starting bias circuit comprises a PJFET tube PJ1, PNP tubes P1, P2, P3, P4, P5, P6, P7, P19 and P20, NPN tubes N1, N2, N3, N4 and N8, and resistors R1, R2, R3, R4, R5, R6, R8 and R9.
The drain end of the PJFET tube PJ1 is connected with the ground GND, the source end of the PJ1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the grid electrode of the PJ1 and is connected with the collector electrode and the base electrode of a PNP tube P1, the emitter electrode of the P1 is connected with the collector electrode of the PNP tube P3 and the base electrode of a PNP tube P4, and the emitter electrode of the P3 is connected to a power supply VCC; an emitter of the P4 is connected with one end of the resistor R2, the other end of the R2 is connected to a power supply VCC, a collector of the P4 is connected with a base of the P3 and an emitter of the PNP tube P2, a base of the P2 is connected with a base of the P1, a collector of the P2 is connected with a collector of the NPN tube N1 and a base of the NPN tube N2, a base of the N1 is connected with an emitter of the N2, an emitter of the N1 is connected with one end of the resistor R3, and the other end of the R3 is connected to the ground GND; the base electrode of an NPN tube N3 is connected with the base electrode of the N1, the emitting electrode of the N3 is connected with one end of a resistor R4, the other end of the resistor R4 is connected to the ground, the collector electrode of the N3 is connected with the collector electrode of a PNP tube P5, the base electrode of the P5 is connected with the base electrode of a PNP tube P6, and the emitting electrode of the P5 is connected to a power supply VCC; an emitter of the PNP tube P6 is connected to a power supply VCC, a collector of the PNP tube P6 is connected with one end of the resistor R6 and an emitter of the PNP tube P7, the other end of the resistor R6 is connected with a base electrode of the PNP tube P7, a base electrode of the PNP tube P7 is connected with a collector of the P5, and a collector of the P7 is connected to the ground GND; bases of PNP tubes P19 and P20 are connected with a base of P6, a collector of P19 is connected with a collector of an NPN tube N7, and a collector of P20 is connected with a collector of an NPN tube N13; one end of the resistor R5 is connected with the base electrode of the N3 tube, the other end of the resistor R5 is connected with the base electrode of the NPN tube N4, the collector electrode of the N4 tube is connected with the emitter electrode of the transistor N5, the emitter electrode of the N4 tube is connected with one end of the resistor R8, and the other end of the resistor R8 is connected to the ground GND; the base electrode of an NPN tube N8 is connected with the base electrode of the N4, the collector electrode of the N8 is connected with the emitting electrodes of the NPN tubes N9 and N10 and the base electrode of the PNP tube P22, the emitting electrode of the N8 tube is connected with one end of a resistor R9, and the other end of the resistor R9 is connected to the ground GND.
The common-emitter common-base differential input circuit comprises the same type of super beta NPN transistors N9 and N10, the same type of NPN transistors N11 and N12, the same type of PNP tubes P23 and P24 and the same type of resistors R10 and R11.
The base electrode of the super beta NPN tube N9 is connected with an IP signal input port and a PNP tube P13 collector electrode, an N9 emitter electrode is connected with a transistor N8 collector electrode, an N9 collector electrode is connected with an NPN tube N12 emitter electrode, an NPN tube N12 base electrode is connected with a transistor N11 base electrode, an N12 collector electrode is connected with a PNP tube P23 base electrode and a PNP collector electrode, a P23 emitter electrode is connected with one end of a resistor R10, and the other end of the resistor R10 is connected to a power supply VCC; one end of a resistor R11 is connected with a power supply VCC, the other end of the resistor R11 is connected with an emitter of a transistor P24, a base of the P24 is connected with a base of a transistor P23, a collector of the P24 is connected with an output port OUT and a collector of an NPN tube N11, a base of the N11 is connected with a base of an N12, an emitter of the N11 is connected with a collector of a super beta transistor N10, a base of the N10 is connected with a signal input end IN and a collector of a PNP tube P4, and an emitter of the N10 is connected with an emitter of an N9.
The common-emitter common-base differential input circuit is provided with an input tube VCE clamping circuit; the clamping circuit consists of an NPN transistor N13 and a PNP transistor P22.
The base electrode of the N13 is connected with the collector electrode of the N13, the collector electrode of the P20, the base electrode of the N11 and the base electrode of the N12; the collector of the N13 is connected with the collector of the P20; the emitter of the N13 is connected with the emitter of the P22; the base of the P22 is connected with the emitter of the N9, the emitter of the N10 and the collector of the N8, and the collector of the P22 is grounded.
The base current compensation core circuit comprises PNP transistors P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18 and P21 of the same type, NPN transistors N6 and N7 of the same type, resistors R7, R8 and R12 of the same type and an ultra-beta transistor N5.
The PNP transistor P8 collector is connected with the ground, the P8 base is connected with the NPN transistor N6 base, the P8 emitter is connected with one end of the resistor R7, one end of the resistor R7 is connected with the PNP transistor P9 base and the collector, the P9 emitter is connected with one end of the resistor R8, and the other end of the resistor R8 is connected to the power supply VCC; the emitter of the PNP transistor P10 is connected with the emitter of the P9, the base of the P10 is connected with the base of the P9, the collector of the P10 is connected with the emitter of the PNP transistor P13, the base of the P13 is connected with the base of the transistor P14, and the collector of the P13 is connected with the base of the super beta NPN transistor N9 and the IP port; an emitter of the PNP transistor P11 is connected with an emitter of the PNP transistor P10, a base of the PNP transistor P11 is connected with a base of the PNP transistor P10, a collector of the PNP transistor P11 is connected with an emitter of the PNP transistor P14, a base of the PNP transistor P14 is connected with a base of the PNP transistor P15, and a collector of the PNP transistor P14 is connected with a base of the super beta NPN transistor N10 and a signal input IN port; the emitter of the PNP transistor P12 is connected with the emitter of the P11, the base of the P12 is connected with the base of the P11, the collector of the P12 is connected with the emitter of the PNP transistor P15, the base of the P15 is connected with the base of the PNP transistor P18 and the collector, the collector of the P15 is connected with the base of the super beta NPN transistor N5, the emitter of the N5 is connected with the collector of the NPN transistor N4 and the base of the PNP transistor P21, the collector of the N5 is connected with the emitter of the NPN transistor N6, the base of the N6 is connected with the base of the P8, the collector of the N6 is connected with the base and the collector of the PNP 18, the emitter of the PNP transistor P18 is connected with the base and the collector of the PNP transistor P17, the base of the P17 is connected with the base of the P16, and the emitter of the P17 is connected with the positive power VCC; the collector of the PNP transistor P21 is connected with the ground GND, the base of the P21 is connected with the collector of the N4, the emitter of the P21 is connected with one end of a resistor R12, the other end of the R12 is connected with the emitter of an NPN transistor N7, the base and the collector of the N7 are connected with the base of the N6, the collector of the N7 is connected with the collector of the PNP transistor P19, the base of the P19 is connected with the base of the P6, and the emitter of the P19 is connected with a power supply VCC; the emitter of the PNP transistor P20 is connected with a power supply VCC, the base of the P20 is connected with the base of the P19, the collector of the P20 is connected with the base and the collector of the NPN transistor N13, the emitter of the N13 is connected with the emitter of the transistor P22, the base of the P22 is connected with the collector of the N8, and the collector of the P22 is connected with the ground GND.
The invention has the beneficial effects that:
1. base current real-time sampling compensation technology: the invention adopts a base current sampling compensation technology, realizes input geminate transistor base current copy through a precise current mirror and negative feedback, and further reduces input bias current and increases input impedance by adopting the same type of super beta NPN transistor differential pair as an input stage.
2. The performance is excellent: the invention adopts a super beta device as an operational amplifier input stage, the gain beta value of the input geminate transistors can reach 10000, under the condition of not adopting a current elimination technology, the input bias current is nA level, and the current elimination technology is further introduced, thereby realizing the input current capability of PA level. The ultra beta technology and the base current elimination technology are fused, so that the bipolar input stage has excellent input characteristics of ultra-low bias current, high input impedance and the like of an input stage of a MOSFET (metal oxide semiconductor field effect transistor) or a field effect transistor, and meanwhile, the characteristics of high transconductance current ratio, low noise and high gain of a bipolar device are kept, and the input characteristic of the operational amplifier becomes more ideal.
3. The temperature drift coefficient of the bias current is reduced, the bias current is kept almost unchanged in the range of the full temperature zone, and the input characteristic of the device is close to idealization.
The technical scheme provided by the invention is widely applied to the technical field of low-bias current operational amplifiers.
Drawings
FIG. 1 is a schematic diagram of the overall schematic of an ultra low bias current circuit of the present invention.
FIG. 2 is a schematic diagram of a start-up bias circuit of the ultra-low bias current circuit of the present invention.
FIG. 3 is a schematic diagram of a cascode differential input circuit of an ultra-low bias current circuit according to the present invention.
FIG. 4 is a schematic diagram of a basic current compensation core circuit of an ultra-low bias current circuit according to the present invention.
FIG. 5 is a schematic diagram of the overall circuit schematic of the ultra low bias current circuit of the present invention.
Detailed Description
As shown in fig. 1 to 5, the embodiment of the ultra-low bias current circuit based on the bipolar amplifier according to the present invention is as follows:
as shown in fig. 1, the ultra-low bias current circuit based on the bipolar amplifier comprises a start bias circuit, a cascode differential input circuit, and a base current compensation core circuit. The starting bias circuit provides a static working point for the whole circuit and gets rid of a power-on starting degenerate working point; the common-emitter common-base differential input circuit adopts an ultra-beta NPN tube as an input tube, an input bias circuit is reduced for the first time, and input impedance is improved; the base current compensation core circuit comprises a bias current monitoring and compensating circuit consisting of a bias circuit and a base current eliminating circuit, on one hand, tail currents of input differential pairs can be monitored and sampled in real time, on the other hand, input bias currents are eliminated according to real-time compensation of the input bias currents through a precise current mirror, PA-level current input of the device is achieved, meanwhile, the temperature drift coefficient of the bias currents is reduced, the bias currents are kept almost unchanged in the range of a full temperature zone, and input characteristics of the device become more ideal.
The start-up bias circuit is shown in fig. 2. The starting circuit and the reference current generating circuit are formed by PJ1, R2, P1, P2, P3 and P4, when the power supply is powered on, because the grid-source voltage of PJ1 is a negative value, PJ1 is approximate to a constant current source, the device can generate a current I1 flowing through a branch formed by P3, P1, R1 and PJ1, and the current is about the reverse saturation current I of PJ1 DSS After the bias circuit enters the steady-state operation, the collector of the P2 is pulled up to 2 VBE voltage drops, so that the whole bias circuit works normally and is separated from a degenerate point. A loop formed by R2, P1, P2, P3, and P4 forms a self-biased reference current generating circuit to provide a reference current for the whole circuit, where P1, P2, P3, and P4 are transistors of the same type, and an emitter junction area ratio is P1: P2: P3: P4=2: i2 is approximately equal to V T * ln (8)/R2, the current flows through N1, N2 and R3, wherein N1, N2, N3, N4, N8 and R3, R4, R8, R9 together form a beta-help multi-path current mirror, wherein the proportional current mirror composed of N1, N2, R3, N8, R9 generates a current I5 ≈ I2 ≈ R3/R9, the current acts on the cascode differential pair circuit, providing bias for the module; similarly, a proportional current mirror composed of N1, N2, N4, R3 and R8 generates a current I4 ≈ I2 × R3/R8, and the current flows through N5 to provide bias for the base current cancellation circuit; the branches N3, R4, P5 will generate currents I3 ≈ I2 × R3/R4, P19, P20, P5, P7, forming a beta-hellp multi-way proportional current mirror, so that P19, P20 copies the current I3 proportionally, forming currents I6, I7, I6: i7 is 1.
The cascode circuit is shown in fig. 3: n9 and N10 are ultra-beta NPN tubes, the current amplification capacity is about 10000, the ultra-beta NPN tubes and the conventional NPN tubes form a cascode amplification circuit, R10 and R11, P23 and P24 form an active load, on one hand, the voltage gain of an input stage is improved, on the other hand, the differential input single-ended output function of input signals is realized, an I4 current source provided by a starting bias circuit is used as a tail current source of an input differential pair to provide static bias for the differential input pair, and the base of the input differential pair tubes N9 and N10 can be known by combining circuit analysisThe pole bias current is about:
wherein beta is p Is the current amplification factor, beta, of the P-type transistor P22 S Is the current amplification factor of an ultra beta NPN tube N9/N10, beta N The current amplification factor of a conventional NPN tube N11/N12 is obtained. I2 and I4 are static currents provided by the starting bias circuit.
The base current sampling/cancellation core circuit is shown in fig. 4. As shown, conventional transistors P9, P10, P11, P12 constitute a proportional current mirror, and the current ratio is 1
Wherein I3 and I1 are static bias currents beta provided by the start-up bias circuit p Is the current amplification factor, beta, of the P-type transistor P21 S Is the current amplification factor of an ultra beta NPN tube N5, beta N The current amplification factor of a conventional NPN tube N7/N6 is obtained. By strictly controlling the current distribution proportion of I3 and I1, and I2 and I4, IP = IN = IB, when the currents of the three are equal, the input bias current of the cascode differential pair is completely cancelled, so that the zero bias current design is realized, and the input bias current range of the design is 1 pA-8 pA through the current slice verification.
Fig. 5 is an integrated circuit of fig. 2-4.
The foregoing is a further detailed description of the invention in connection with preferred embodiments and is not intended to limit the invention to the precise form disclosed. It will be understood by those skilled in the art that various changes in detail may be effected therein without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A method for designing ultralow bias current based on a bipolar amplifier is characterized by comprising the following steps: the method adopts a real-time sampling current elimination design method, and the real-time sampling current elimination design method comprises the following steps:
a super beta NPN tube is used as an input tube of the cascode differential input circuit, so that the input impedance is improved, and the input bias current is physically reduced;
the super beta NPN tube is provided with an input tube VCE clamping circuit;
the method comprises the steps of adopting a base current real-time sampling monitoring and real-time compensation method consisting of a bias circuit, a precise current mirror and a base current elimination circuit to monitor and sample tail currents of an input differential pair in real time, compensating the input bias current in real time through the precise current mirror, and eliminating the input bias current through real-time sampling monitoring and real-time compensation of the input bias current to realize the input of the co-emitting common-base differential pair input tube PA-level current.
2. An ultra-low bias current bipolar amplifier circuit according to the design method of claim 1, comprising a dc power supply, a start-up bias circuit, a base current compensation core circuit, a cascode differential input circuit, and an output terminal;
the direct-current power supply is connected with a starting bias circuit and a common-emitter common-base differential input circuit, the starting bias circuit is connected with the common-emitter common-base differential input circuit and a base current compensation core circuit, the base current compensation core circuit is in forward connection and reverse connection with the common-emitter common-base differential input circuit, and the common-emitter common-base differential input circuit is connected with an output end;
the starting bias circuit enables a system to get rid of the constraint of a degeneracy point to normally work after a power supply is powered on, and provides a stable direct current bias point for the whole circuit after the starting is finished;
the common-emitter common-base differential input circuit comprises a same type of super beta NPN transistor differential pair, and the amplification and double-rotation single function of an input signal are realized;
the base current compensation core circuit comprises a bias current monitoring circuit and a compensation circuit, input geminate transistor base current copying is achieved through a precise current mirror and negative feedback, the input geminate transistor base current copying is used for collecting input bias current and achieving base current synchronous compensation, and the input bias current of the bipolar operational amplifier is reduced to pA level.
3. An ultra-low bias current bipolar amplifier circuit as recited in claim 2, wherein:
the starting bias circuit comprises a PJFET tube PJ1, PNP tubes P1, P2, P3, P4, P5, P6, P7, P19 and P20, NPN tubes N1, N2, N3, N4 and N8, resistors R1, R2, R3, R4, R5, R6, R8 and R9;
the drain end of the PJFET tube PJ1 is connected with the ground GND, the source end of the PJ1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the grid electrode of the PJ1 and is connected with the collector electrode and the base electrode of a PNP tube P1, the emitter electrode of the P1 is connected with the collector electrode of the PNP tube P3 and the base electrode of a PNP tube P4, and the emitter electrode of the P3 is connected to a power supply VCC; an emitter of the P4 is connected with one end of the resistor R2, the other end of the R2 is connected to a power supply VCC, a collector of the P4 is connected with a base of the P3 and an emitter of the PNP tube P2, a base of the P2 is connected with a base of the P1, a collector of the P2 is connected with a collector of the NPN tube N1 and a base of the NPN tube N2, a base of the N1 is connected with an emitter of the N2, an emitter of the N1 is connected with one end of the resistor R3, and the other end of the R3 is connected to the ground GND; the base electrode of an NPN tube N3 is connected with the base electrode of the N1, the emitting electrode of the N3 is connected with one end of a resistor R4, the other end of the resistor R4 is connected to the ground, the collector electrode of the N3 is connected with the collector electrode of a PNP tube P5, the base electrode of the P5 is connected with the base electrode of a PNP tube P6, and the emitting electrode of the P5 is connected to a power supply VCC; an emitter of a PNP tube P6 is connected to a power supply VCC, a collector of the PNP tube P6 is connected with one end of a resistor R6 and an emitter of a PNP tube P7, the other end of the resistor R6 is connected with a base of the PNP tube P7, a base of the PNP tube P7 is connected with a collector of the PNP 5, and a collector of the PNP tube P7 is connected to a ground GND; bases of PNP tubes P19 and P20 are connected with a base of P6, a collector of P19 is connected with a collector of an NPN tube N7, and a collector of P20 is connected with a collector of an NPN tube N13; one end of a resistor R5 is connected with the base electrode of the N3 tube, the other end of the resistor R5 is connected with the base electrode of the NPN tube N4, the collector electrode of the N4 tube is connected with the emitter electrode of the transistor N5, the emitter electrode of the N4 tube is connected with one end of a resistor R8, and the other end of the resistor R8 is connected to the ground GND; the base electrode of an NPN tube N8 is connected with the base electrode of the N4, the collector electrode of the N8 is connected with the emitting electrodes of the NPN tubes N9 and N10 and the base electrode of the PNP tube P22, the emitting electrode of the N8 tube is connected with one end of a resistor R9, and the other end of the resistor R9 is connected to the ground GND.
4. An ultra-low bias current bipolar amplifier circuit as in claim 3, wherein:
the emitter junction area ratio of P1, P2, P3, P4 is P1: P2: P3: P4= 2.
5. An ultra-low bias current bipolar amplifier circuit as in claim 3, wherein:
p19, P20, P5, P7 form a beta-hellp multi-way proportional current mirror, so that P19, P20 copies the current I3 of the N3, R4, P5 branch proportionally, the current I6 is formed at the P19 collector, the current I7 is formed at the P20 collector, and the ratio of I6 to I7 is 1.
6. An ultra-low bias current bipolar amplifier circuit as recited in claim 2, wherein:
the common-emitter common-base differential input circuit comprises same type super beta NPN transistors N9 and N10, same type NPN transistors N11 and N12, same type PNP transistors P23 and P24 and same type resistors R10 and R11;
the N9 base electrode is connected with the IP signal input port and the PNP transistor P13 collector electrode, the N9 emitter electrode is connected with the transistor N8 collector electrode, the N9 collector electrode is connected with the NPN transistor N12 emitter electrode, the NPN transistor N12 base electrode is connected with the transistor N11 base electrode, the N12 collector electrode is connected with the PNP transistor P23 base electrode and the PNP transistor P23 collector electrode, the P23 emitter electrode is connected with one end of a resistor R10, and the other end of the resistor R10 is connected to a power supply VCC; one end of a resistor R11 is connected with a power supply VCC, the other end of the resistor R11 is connected with an emitter of a transistor P24, a base of the P24 is connected with a base of a P23, a collector of the P24 is connected with an output port OUT and a collector of an NPN tube N11, a base of the N11 is connected with a base of an N12, an emitter of the N11 is connected with a collector of an N10, a base of the N10 is connected with a signal input end IN and a collector of a PNP tube P4, and an emitter of the N10 is connected with an emitter of an N9.
7. An ultra-low bias current bipolar amplifier circuit as in claim 6, wherein: the common-emitter common-base differential input circuit is provided with an input tube VCE clamping circuit; the clamping circuit consists of an NPN transistor N13 and a PNP transistor P22;
the base electrode of the N13 is connected with the collector electrode of the N13, the collector electrode of the P20, the base electrode of the N11 and the base electrode of the N12;
the collector of the N13 is connected with the collector of the P20;
the emitter of the N13 is connected with the emitter of the P22;
the base of the P22 is connected with the emitter of the N9, the emitter of the N10 and the collector of the N8, and the collector of the P22 is grounded.
8. An ultra-low bias current bipolar amplifier circuit as in claim 6, wherein: IP = IN = IB, IP being the base input current of N9, IN being the base input current of N10, IB being the base bias current of N9, N10.
9. An ultra-low bias current bipolar amplifier circuit as in claim 2, wherein:
the base current compensation core circuit comprises PNP transistors P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18 and P21 of the same type, NPN transistors N6 and N7 of the same type, resistors R7, R8 and R12 of the same type and an ultra-beta transistor N5;
the collector of the PNP transistor P8 is connected with the ground, the base of the P8 is connected with the base of the NPN transistor N6, the emitter of the P8 is connected with one end of the resistor R7, the other end of the R7 is connected with the base and the collector of the PNP transistor P9, the emitter of the P9 is connected with one end of the resistor R8, and the other end of the R8 is connected to a power supply VCC; the emitter of the PNP transistor P10 is connected with the emitter of the P9, the base of the P10 is connected with the base of the P9, the collector of the P10 is connected with the emitter of the PNP transistor P13, the base of the P13 is connected with the base of the transistor P14, and the collector of the P13 is connected with the base of the super beta NPN transistor N9 and the IP port; an emitter of the PNP transistor P11 is connected with an emitter of the PNP transistor P10, a base of the PNP transistor P11 is connected with a base of the PNP transistor P10, a collector of the PNP transistor P11 is connected with an emitter of the PNP transistor P14, a base of the PNP transistor P14 is connected with a base of the PNP transistor P15, and a collector of the PNP transistor P14 is connected with a base of the super beta NPN transistor N10 and a signal input IN port; the emitter of the PNP transistor P12 is connected with the emitter of the P11, the base of the P12 is connected with the base of the P11, the collector of the P12 is connected with the emitter of the PNP transistor P15, the base of the P15 is connected with the base of the PNP transistor P18 and the collector, the collector of the P15 is connected with the base of the super beta NPN transistor N5, the emitter of the N5 is connected with the collector of the NPN transistor N4 and the base of the PNP transistor P21, the collector of the N5 is connected with the emitter of the NPN transistor N6, the base of the N6 is connected with the base of the P8, the collector of the N6 is connected with the base and the collector of the PNP 18, the emitter of the PNP transistor P18 is connected with the base and the collector of the PNP transistor P17, the base of the P17 is connected with the base of the P16, and the emitter of the P17 is connected with the positive power VCC; the collector of the PNP transistor P21 is connected with the ground GND, the base of the P21 is connected with the collector of the N4, the emitter of the P21 is connected with one end of the resistor R12, the other end of the R12 is connected with the emitter of the NPN transistor N7, the base and the collector of the N7 are connected with the base of the N6, the collector of the N7 is connected with the collector of the PNP transistor P19, the base of the P19 is connected with the base of the P6, and the emitter of the P19 is connected with the power supply VCC; the emitter of the PNP transistor P20 is connected with a power supply VCC, the base of the P20 is connected with the base of the P19, the collector of the P20 is connected with the base and the collector of the NPN transistor N13, the emitter of the N13 is connected with the emitter of the transistor P22, the base of the P22 is connected with the collector of the N8, and the collector of the P22 is connected with the ground GND.
10. An ultra-low bias current bipolar amplifier circuit as recited in claim 9, wherein:
current ratios of P9, P10, P11, P12 are 1.
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| CN113630096A (en) * | 2021-08-17 | 2021-11-09 | 中国电子科技集团公司第二十四研究所 | Rail-to-rail output circuit of high-speed fully differential amplifier and high-speed fully differential amplifier |
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| US4855684A (en) * | 1988-10-14 | 1989-08-08 | Analog Devices, Inc. | Bias current compensation for bipolar input stages |
| US4959622A (en) * | 1989-08-31 | 1990-09-25 | Delco Electronics Corporation | Operational amplifier with precise bias current control |
| GB2378068B (en) * | 2001-07-27 | 2005-05-04 | Motorola Inc | Bipolar differential amplifier |
| US6414553B1 (en) * | 2001-08-30 | 2002-07-02 | Koninklijke Philips Electronics N.V. | Power amplifier having a cascode current-mirror self-bias boosting circuit |
| US6965267B2 (en) * | 2004-02-27 | 2005-11-15 | Analog Devices, Inc. | Bipolar differential input stage with input bias current cancellation circuit |
| US8970301B2 (en) * | 2013-05-20 | 2015-03-03 | Analog Devices, Inc. | Method for low power low noise input bias current compensation |
| CN104506144B (en) * | 2014-11-18 | 2017-08-01 | 华中科技大学 | A kind of low noise difference pre-amplification circuit and amplifier |
| CN110048675B (en) * | 2019-05-06 | 2023-03-21 | 西安微电子技术研究所 | Circuit for improving input bias current performance of bipolar rail-to-rail operational amplifier |
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