CN211603985U - Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process - Google Patents
Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process Download PDFInfo
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Abstract
The utility model discloses a negative pressure reference circuit based on CMOS technology belongs to integrated circuit technical field. The utility model comprises a reference source core circuit and a reference level conversion circuit, wherein the reference source core circuit generates a reference voltage relative to a negative voltage power supply; the reference level conversion circuit is used for generating a negative voltage reference output which is referenced to the ground; the output end of the reference source core circuit is connected with the positive input end of an operational amplifier of the reference level conversion circuit, the reference source core circuit and the reference level conversion circuit are both connected with the same ground and the same negative voltage power supply, and the resistors are the same type of resistors. The utility model discloses the reference voltage for negative voltage power supply who will produce by traditional reference source core circuit converts required negative pressure benchmark into, solves the problem that realizes that the high accuracy negative pressure benchmark degree of difficulty is big on traditional CMOS technology.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, concretely relates to negative pressure reference circuit based on CMOS technology.
Background
With the great improvement of the integration level of the radar antenna array surface, the chip integration requirement of the radio frequency front-end system is more and more strong. The radio frequency front-end chip based on the CMOS process has the characteristics of high integration level, low cost and low power consumption, and is a necessary way for improving the integration level of an antenna array surface. The power amplifier gate driver chip is one of the important elements in the radio frequency front end, and needs a driving capability capable of providing nF-level capacitance and tens of milliamperes of current. The negative voltage reference circuit is an important component of the power amplifier grid driving chip, and the realization of the negative voltage reference circuit based on the CMOS process is the basis of meeting the requirements of the power amplifier grid driving chip with high integration level and low cost.
The NPN triode in the BiCMOS process or the BCD process can be used for designing a high-precision negative-pressure reference circuit, compared with the CMOS process, the BiCMOS/BCD process is higher in price, and the application cost of the radio frequency front end is improved. The traditional CMOS process only has parasitic PNP triodes, and the positive voltage reference circuit based on the ground level can be realized by adopting the traditional design method, but the difficulty of realizing the high-precision negative voltage reference circuit based on the traditional CMOS process is higher.
Disclosure of Invention
The utility model aims at providing a negative pressure reference circuit based on CMOS technology that realization mode is simple, high accuracy.
In particular, the utility model provides a negative voltage reference circuit based on CMOS process, which comprises a reference source core circuit and a reference level conversion circuit,
the reference source core circuit generates a reference voltage relative to a negative voltage power supply, and comprises parasitic PNP triodes Q1, Q2 and Q3 in a CMOS process, a first resistor and a second resistor of the same type; the reference source core circuit output voltage Vref _ pre is expressed as:
wherein, Vbe1Is the voltage between the base and emitter of Q1, VbeIs the voltage between the base and emitter of Q2, Vbe3The voltage between the base stage and the emitter stage of the Q3 is shown as R1, R2 and VEE, wherein R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and VEE is the voltage of the negative power supply;
the reference level conversion circuit is used for generating a negative voltage reference output which is referenced to the ground; the power supply circuit comprises an operational amplifier A, NMOS tube MN, a third resistor and a fourth resistor, wherein the positive input end of the operational amplifier A is used as the input end of a reference level conversion circuit, the reverse input end of the operational amplifier A and the source end of the NMOS tube MN are connected with the third resistor, the positive power supply end of the operational amplifier A is connected with the ground, and the negative power supply end of the operational amplifier A is connected with a power supply VEE; the output end of the operational amplifier A is connected with the gate end of the NMOS transistor MN; the other end of the third resistor is connected with VEE; the drain terminal of the NMOS tube MN is connected with one end of the fourth resistor and is used as the output terminal of the reference level conversion circuit; the other end of the fourth resistor is grounded;
the output end of the reference source core circuit is connected with the positive input end of an operational amplifier of the reference level conversion circuit, the reference source core circuit and the reference level conversion circuit are both connected with the same ground and the same negative voltage power supply, and the first resistor, the second resistor, the third resistor and the fourth resistor are resistors of the same type.
Further, the operational amplifier a is a PMOS input two-stage operational amplifier or a high-gain single-stage operational amplifier.
Further, the reference source core circuit further includes: an operational amplifier A1 and PMOS tubes MP 1-MP 3; the sources of the MP 1-MP 3 are simultaneously connected with the ground; the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A1; the drain electrode of the MP1 is connected with the inverted input end of the operational amplifier A1 and is also connected with the emitter electrode of the Q1; the drain electrode of the MP2 is connected with the positive input end of the operational amplifier A1 and is also connected with one end of the first resistor; the drain electrode of the MP3 is connected with one end of the second resistor and is used as the output of the reference source core circuit; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of the first resistor is connected with an emitting electrode of the Q2; the other end of the second resistor is connected to the emitter of Q3.
Further, the reference source core circuit further includes: an operational amplifier A2 and PMOS tubes MP 1-MP 6; the sources of the MP 1-MP 3 are simultaneously connected with the ground, and the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A2; the drain electrode of the MP1 is connected with the source electrode of the MP 4; the drain electrode of the MP2 is connected with the source electrode of the MP 5; the drain electrode of the MP3 is connected with the source electrode of the MP 6; the drain electrode of the MP4 is connected with the inverted input end of the operational amplifier A2 and is also connected with the emitter electrode of the Q1; the drain electrode of the MP5 is connected with the positive input end of the operational amplifier A2 and is also connected with one end of the first resistor; the drain of the MP6 is connected with one end of a second resistor R2 and is used as the output of the reference source core circuit; the gates of the MP 4-MP 6 are connected with the output end of the bias circuit at the same time; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of the first resistor is connected with an emitting electrode of the Q2; the other end of the second resistor is connected to the emitter of Q3.
The utility model discloses a negative pressure reference circuit based on CMOS technology's beneficial effect is as follows:
the utility model discloses a negative pressure reference circuit based on CMOS technology utilizes traditional reference source core circuit to produce the reference voltage for negative pressure power supply, produces required negative pressure benchmark through simple reference level converting circuit again. The negative voltage reference circuit of the utility model can provide a stable level relative to the ground under the CMOS process, and the reference voltage has a low temperature coefficient and does not change along with the change of the negative voltage power supply; the utility model discloses can realize under the CMOS technology of standard, only increase simple level shift circuit on traditional reference source circuit basis, the implementation is simple.
Drawings
Fig. 1 is a schematic diagram of a reference source core circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of another reference source core circuit according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a reference level shift circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings in conjunction with embodiments.
Example 1:
an embodiment of the utility model, be a negative pressure reference circuit based on CMOS technology for power amplifier's grid negative pressure drive module.
As shown in fig. 1 and 3, the negative voltage reference circuit based on the CMOS process includes a reference source core circuit having an output terminal Vref _ pre, and a reference level shifter circuit having an input terminal Vref _ pre ', the output terminal Vref _ pre being connected to the input terminal Vref _ pre'. The reference source core circuit and the reference level conversion circuit are both connected to ground and a power supply VEE.
The reference source core circuit adopts a traditional reference source core circuit, as shown in fig. 1, A1 is an operational amplifier, Q1, Q2 and Q3 are parasitic PNP triodes in a CMOS process, R1 and R2 are resistors of the same type, and MP 1-MP 3 are PMOS tubes. The sources of the MP 1-MP 3 are simultaneously connected with the ground; the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A1; the drain electrode of the MP1 is connected with the inverted input end of the operational amplifier A1 and is also connected with the emitter electrode of the Q1; the drain of the MP2 is connected with the positive input end of the operational amplifier A1 and is also connected with one end of the R1; the drain of the MP3 is connected with one end of the R2 and is used as the output of the reference source core circuit; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of R1 is connected with the emitter of Q2; the other end of R2 is connected to the emitter of Q3.
The reference source core circuit shown in fig. 2 can also be adopted, a2 is an operational amplifier, Q1, Q2 and Q3 are parasitic PNP triodes in a CMOS process, R1 and R2 are resistors of the same type, and MP 1-MP 6 are PMOS transistors. The sources of the MP 1-MP 3 are simultaneously connected with the ground, and the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A2; the drain electrode of the MP1 is connected with the source electrode of the MP 4; the drain electrode of the MP2 is connected with the source electrode of the MP 5; the drain electrode of the MP3 is connected with the source electrode of the MP 6; the drain electrode of the MP4 is connected with the inverted input end of the operational amplifier A2 and is also connected with the emitter electrode of the Q1; the drain of the MP5 is connected with the positive input end of the operational amplifier A2 and is also connected with one end of the R1; the drain of the MP6 is connected with one end of the R2 and is used as the output of the reference source core circuit; the gates of the MP 4-MP 6 are connected with the output end of the bias circuit at the same time; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of R1 is connected with the emitter of Q2; the other end of R2 is connected to the emitter of Q3.
The reference level conversion circuit comprises an operational amplifier A, NMOS tube MN, a resistor R3 and a resistor R4 and is used for generating negative voltage reference output which is referenced to the ground. The input end Vref _ pre' is connected with the positive input end of the operational amplifier A, the reverse input end of the operational amplifier A is connected with one end of a resistor R3, the positive power end is connected with the ground, the negative power end is connected with the power VEE, and the output end is connected with the gate end of the NMOS transistor MN; one end of the resistor R3 is connected with VEE, and the other end of the resistor R3 is connected with the source end of the NMOS tube MN; the drain terminal of the NMOS transistor MN is connected with one end of a resistor R4 and is also connected with an output terminal Vref; the other end of the resistor R4 is connected to ground.
The operational amplifier A is a PMOS input two-stage operational amplifier or a high-gain single-stage operational amplifier.
The working principle is as follows:
in the conventional reference source core circuit shown in fig. 1, the reference source core circuit output voltage Vref _ pre can be expressed as:
wherein, Vbr1Is the voltage between the base and emitter of Q1, Vbe2Is the voltage between the base and emitter of Q2, Vbe3The voltage between the base and emitter of Q3, R1 is the resistance of the first resistor, R2 is the resistance of the second resistor, and VEE is the negative supply voltage.
By selecting proper device parameters and types for parasitic PNP triodes Q1, Q2 and Q3 and resistors R1 and R2, the first term and the second term in the formula (1) are optimized, and the voltage value with a low temperature coefficient can be easily realized.
It is understood that the reference source core circuit including the parasitic PNP transistors Q1, Q2, Q3 in the CMOS process, the resistors R1 and R2 of the same type, and the NMOS transistor may have different circuit structures as long as the reference source core circuit output voltage Vref _ pre can also be expressed as formula (1).
However, the negative voltage supply VEE term exists in the formula (1), and the change of the supply VEE is directly reflected in the reference source output voltage Vref _ pre. In practical application, the power supply VEE is easily subjected to radio frequency interference from the environment, so that the conventional reference source core circuit is not suitable for practical application any more.
The input terminal Vref _ pre 'of the reference level shifter shown in FIG. 3 is the output terminal Vref _ pre of the reference source core circuit shown in FIG. 1, i.e. the input terminal Vref _ pre' of the reference level shifter is the output terminal Vref _ pre
Vref_pre’＝Vref_pre (2)
According to the negative feedback mechanism of the operational amplifier, the levels of the reverse input end and the forward input end of the operational amplifier A are equal under the stable condition, and the current I flowing through the resistor R4 on the output branch circuit is
By substituting the equations (1) and (2) into the equation (3), the negative reference voltage Vref outputted by the reference level converting circuit can be expressed as
According to the formula (4), the formula (4) is optimized by selecting the resistors R1 and R2 of the same type and the resistors R3 and R4 of the same type, and the negative voltage reference voltage Vref output by the optimized reference level conversion circuit is a negative voltage reference voltage value with a lower temperature coefficient regardless of the power supply voltage VEE.
The technical effects are as follows:
through the emulation test, the utility model discloses a negative pressure reference circuit based on CMOS technology, output reference voltage is greater than 80dB at the power supply rejection ratio of low frequency department, changes at-55 ~ 125 ℃ full temperature within range and is less than 1mV, changes to reduce at least 50% for traditional negative pressure reference circuit full temperature.
The utility model discloses a negative pressure reference circuit based on CMOS technology for the negative pressure reference circuit based on the realization of BiCMOS BCD technology, the utility model discloses the cost is lower, and circuit structure is simple, realizes more easily.
Although the present invention has been described with reference to the preferred embodiments, the embodiments are not intended to limit the present invention. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention also belong to the protection scope of the present invention. The scope of protection of the invention should therefore be determined with reference to the claims that follow.
Claims (4)
1. A negative voltage reference circuit based on CMOS process is characterized in that the negative voltage reference circuit comprises a reference source core circuit and a reference level conversion circuit,
the reference source core circuit generates a reference voltage relative to a negative voltage power supply, and comprises parasitic PNP triodes Q1, Q2 and Q3 in a CMOS process, a first resistor and a second resistor of the same type; the reference source core circuit output voltage Vref _ pre is expressed as:
wherein, Vbe1Is the voltage between the base and emitter of Q1, Vbe2Is the voltage between the base and emitter of Q2, Vbe3The voltage between the base stage and the emitter stage of the Q3 is shown as R1, R2 and VEE, wherein R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and VEE is the voltage of the negative power supply;
the reference level conversion circuit is used for generating a negative voltage reference output which is referenced to the ground; the power supply circuit comprises an operational amplifier A, NMOS tube MN, a third resistor and a fourth resistor, wherein the positive input end of the operational amplifier A is used as the input end of a reference level conversion circuit, the reverse input end of the operational amplifier A and the source end of the NMOS tube MN are connected with the third resistor, the positive power supply end of the operational amplifier A is connected with the ground, and the negative power supply end of the operational amplifier A is connected with a power supply VEE; the output end of the operational amplifier A is connected with the gate end of the NMOS transistor MN; the other end of the third resistor is connected with VEE; the drain terminal of the NMOS tube MN is connected with one end of the fourth resistor and is used as the output terminal of the reference level conversion circuit; the other end of the fourth resistor is grounded;
the output end of the reference source core circuit is connected with the positive input end of an operational amplifier of the reference level conversion circuit, the reference source core circuit and the reference level conversion circuit are both connected with the same ground and the same negative voltage power supply, and the first resistor, the second resistor, the third resistor and the fourth resistor are resistors of the same type.
2. The negative voltage reference circuit based on the CMOS process as claimed in claim 1, wherein the operational amplifier A is a PMOS input two-stage operational amplifier or a high-gain single-stage operational amplifier.
3. The CMOS process based negative voltage reference circuit of claim 1, wherein the reference source core circuit further comprises: an operational amplifier A1 and PMOS tubes MP 1-MP 3; the sources of the MP 1-MP 3 are simultaneously connected with the ground; the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A1; the drain electrode of the MP1 is connected with the inverted input end of the operational amplifier A1 and is also connected with the emitter electrode of the Q1; the drain electrode of the MP2 is connected with the positive input end of the operational amplifier A1 and is also connected with one end of the first resistor; the drain electrode of the MP3 is connected with one end of the second resistor and is used as the output of the reference source core circuit; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of the first resistor is connected with an emitting electrode of the Q2; the other end of the second resistor is connected to the emitter of Q3.
4. The CMOS process based negative voltage reference circuit of claim 1, wherein the reference source core circuit further comprises: an operational amplifier A2 and PMOS tubes MP 1-MP 6; the sources of the MP 1-MP 3 are simultaneously connected with the ground, and the gates of the MP 1-MP 3 are connected with the output end of the operational amplifier A2; the drain electrode of the MP1 is connected with the source electrode of the MP 4; the drain electrode of the MP2 is connected with the source electrode of the MP 5; the drain electrode of the MP3 is connected with the source electrode of the MP 6; the drain electrode of the MP4 is connected with the inverted input end of the operational amplifier A2 and is also connected with the emitter electrode of the Q1; the drain electrode of the MP5 is connected with the positive input end of the operational amplifier A2 and is also connected with one end of the first resistor; the drain of the MP6 is connected with one end of a second resistor R2 and is used as the output of the reference source core circuit; the gates of the MP 4-MP 6 are connected with the output end of the bias circuit at the same time; bases and collectors of Q1-Q3 are connected with a negative voltage power supply VEE at the same time; the other end of the first resistor is connected with an emitting electrode of the Q2; the other end of the second resistor is connected to the emitter of Q3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020600314.6U CN211603985U (en) | 2020-04-21 | 2020-04-21 | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process |
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| CN202020600314.6U CN211603985U (en) | 2020-04-21 | 2020-04-21 | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111352461A (en) * | 2020-04-21 | 2020-06-30 | 中国电子科技集团公司第十四研究所 | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process |
| CN112306143A (en) * | 2020-11-16 | 2021-02-02 | 江苏万邦微电子有限公司 | Simple negative voltage reference circuit |
-
2020
- 2020-04-21 CN CN202020600314.6U patent/CN211603985U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111352461A (en) * | 2020-04-21 | 2020-06-30 | 中国电子科技集团公司第十四研究所 | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process |
| CN111352461B (en) * | 2020-04-21 | 2024-04-19 | 中国电子科技集团公司第十四研究所 | Negative pressure reference circuit based on CMOS technology |
| CN112306143A (en) * | 2020-11-16 | 2021-02-02 | 江苏万邦微电子有限公司 | Simple negative voltage reference circuit |
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