CN111158422A - Reference voltage source with zero temperature coefficient bias point - Google Patents
Reference voltage source with zero temperature coefficient bias point Download PDFInfo
- Publication number
- CN111158422A CN111158422A CN202010040053.1A CN202010040053A CN111158422A CN 111158422 A CN111158422 A CN 111158422A CN 202010040053 A CN202010040053 A CN 202010040053A CN 111158422 A CN111158422 A CN 111158422A
- Authority
- CN
- China
- Prior art keywords
- electrode
- tube
- drain electrode
- pmos tube
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The invention discloses a reference voltage source with a zero temperature coefficient bias point, which comprises a current source generating circuit, an operational amplifier circuit and a reference generating circuit. The current generation module generates bias current which is needed by the operational amplifier and is irrelevant to the temperature process, the operational amplifier biases the NMOS tube at a zero temperature coefficient point through output voltage, and the NMOS tube generates gate-source voltage which is irrelevant to the temperature and is the final reference voltage. The invention can simplify the circuit structure, improve the working frequency of the circuit, reduce the temperature coefficient of the reference voltage, ensure that the reference voltage keeps stable output in a wide temperature range, and is suitable for most of analog and digital circuits needing a reference voltage source.
Description
Technical Field
The invention belongs to the technical field of electronics, and further relates to a reference voltage source of a zero temperature coefficient bias point ZTC (zero temperature coefficient) in the technical field of analog integrated circuits. The invention can provide reference voltage for a low-voltage low-temperature drift analog circuit and a digital-analog mixed circuit, and particularly can be used for providing stable and reliable reference voltage for modules such as an oscillator, an LDO (low dropout regulator), an ADC (analog-to-digital converter)/DAC (digital-to-analog converter) and the like.
Background
The integrated circuit technology is rapidly developed, and in the integrated circuit design, a reference voltage source is a key module and is widely applied to an analog circuit, a digital circuit and an analog-digital mixed circuit. The traditional reference voltage source generally adopts a band gap technology, a resistor, an operational amplifier and a bipolar transistor with large area cannot be separated structurally, the circuit structure is complex, the power consumption and the temperature drift are high, and the occupied chip area is large. In order to meet the high stability requirement of the reference voltage source, the reference voltage source must have a low temperature coefficient.
The university of electronic technology in its own patent technology "a bandgap reference circuit based on two threshold voltage MOS devices" (patent No. ZL 201710440384.5, publication No. CN 102495661B) discloses a bandgap reference voltage circuit based on two threshold voltage MOS devices. The circuit comprises a starting circuit of a negative temperature coefficient current source circuit, a current source circuit in a negative proportion relation with temperature, a reference voltage output circuit, a starting circuit of a positive temperature coefficient current source circuit, a current source circuit in a positive proportion relation with temperature and a bias circuit, wherein 6 subcircuits are total. The starting circuit of the negative temperature coefficient current source circuit is used for starting the current source circuit which has a negative proportional relation with the temperature; a current source circuit having a negative proportional relationship with temperature for generating a current having a negative proportional relationship with temperature; a reference voltage output circuit for outputting a reference voltage having a zero temperature characteristic; a current source circuit in direct proportion to temperature for generating a current in direct proportion to temperature; the bias circuit is used for providing bias voltage for a cascode transistor of the current mirror circuit; the starting circuit of the positive temperature coefficient current source circuit is used for starting the current source circuit which is in direct proportion to the temperature. Although the reference voltage circuit realizes second-order compensation of the reference voltage, the technology of the patent still has the disadvantage that the power consumption of the circuit is increased because the circuit uses an additional positive and negative temperature current compensation circuit.
Danyang constant core electronics ltd discloses an ultra-low power consumption all-CMOS reference voltage circuit in the patent document "ultra-low power consumption all-CMOS reference circuit system" (patent No. ZL 201711016255.7, application publication No. CN 107943196 a) applied by danyang constant core electronics ltd. The reference voltage circuit comprises a starting circuit, a micro-current generating circuit, an operational amplifying circuit and a core reference voltage circuit. A start-up circuit for driving the reference voltage circuit; the micro-current generating circuit provides working current for the operational amplifying circuit of the reference voltage circuit, and the core of the micro-current generating circuit is that an MOS tube works in a sub-threshold region; the operational amplification circuit works in a subthreshold region, so that the influence on the circuit caused by current change is reduced to the maximum extent; and the core reference voltage circuit generates a reference current and a reference voltage of the core. Although the reference voltage with the low temperature coefficient can be obtained by biasing the MOS tubes in the sub-threshold region, the reference voltage circuit still has the defects that the MOS tubes biased in the sub-threshold region can slow the response speed of the circuit, so that the working frequency of the circuit is reduced, the temperature coefficient of the reference voltage is increased, and the change of the reference voltage is obvious when the temperature changes.
Disclosure of Invention
The present invention is directed to solve the above-mentioned problems and to provide a reference voltage source with zero temperature coefficient bias point.
The specific idea for realizing the purpose of the invention is to apply a biasing circuit to bias an NMOS tube at a zero temperature coefficient point, the NMOS tube works in a saturation region, and the gate-source voltage is independent of the temperature through the compensation of the mobility and the threshold voltage, so as to output the voltage of the zero temperature coefficient point. The circuit is simple in structure, and can generate reference voltage with low temperature drift and low power consumption compared with the traditional band gap reference.
In order to achieve the above object, the present invention includes a current source generating circuit, an operational amplifier circuit, and a reference generating circuit; the output end of the current source generating circuit is connected with the current bias input end of the operational amplifier circuit, and the current bias input end of the operational amplifier circuit is connected with the output end of the current source generating circuit; the positive phase end of the differential input end of the operational amplifier is grounded, the negative phase end of the differential input end of the operational amplifier is connected with the output end of the reference generating circuit, and the output end of the operational amplifier circuit is connected with the input end of the reference generating circuit; the input end of the reference generating circuit is connected with the output end of the operational amplifier circuit, and the output end of the reference generating circuit is connected with the negative phase end of the differential input of the operational amplifier.
Compared with the prior art, the invention has the following advantages:
the invention can provide bias current irrelevant to process and temperature by connecting the output end of the current source generating circuit with the current bias input end of the operational amplifier circuit, and connecting the current bias input end of the operational amplifier circuit with the output end of the current source generating circuit, thereby overcoming the defect that the power consumption of the circuit is increased by using an additional positive and negative temperature current compensating circuit. The advantages of reducing power consumption and simplifying circuit structure are achieved.
2, the invention uses the positive phase of the differential input end of the operational amplifier to be connected with the ground, the negative phase to be connected with the output end of the reference generating circuit, and the output end of the operational amplifier circuit is connected with the input end of the reference generating circuit; the input end of the reference generating circuit is connected with the output end of the operational amplifier circuit, and the output end of the reference generating circuit is connected with the negative phase end of the differential input of the operational amplifier, so that an NMOS tube in the reference generating circuit can work in a saturation region, and the defects that in the prior art, the response speed of the circuit is slowed down due to the fact that an MOSFET device is biased in a subthreshold region are overcome, the working frequency of the circuit is reduced, the temperature coefficient of reference voltage is increased, the working frequency of the circuit is improved, and the temperature coefficient of the reference voltage is reduced when the temperature changes.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a graph of simulated temperature characteristics according to the present invention;
FIG. 3 is a simulated transient diagram of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
A specific circuit of the present invention is further described with reference to fig. 1.
The dotted line in fig. 1 divides the electrical schematic diagram of the present invention into three parts, namely, a current source generating circuit 1, an operational amplifier circuit 2, and a reference generating circuit 3. The output end of the current source generating circuit 1 is connected with the current bias input end of the operational amplifier circuit 2, and the current bias input end of the operational amplifier circuit 2 is connected with the output end of the current source generating circuit 1; the positive phase end of the differential input end of the operational amplifier 2 is grounded, the negative phase end is connected with the output end of the reference generating circuit 3, and the output end of the operational amplifier circuit 2 is connected with the input end of the reference generating circuit 3; the input terminal of the reference generation circuit 3 is connected to the output terminal of the operational amplifier circuit 2, and the output terminal of the reference generation circuit 3 is connected to the negative phase terminal of the differential input of the operational amplifier circuit 2.
Electrical principle of the invention a current source generating circuit is depicted in dashed line part in fig. 1, an output of the current source generating circuit 1 being connected to a current bias input of an operational amplifier circuit 2.
The source electrodes of a first PMOS tube 4 and a second PMOS tube 5 in the current source generating circuit are respectively connected with a common power supply VDD; the drain electrode of the first PMOS tube 4 is respectively connected with the drain electrode and the grid electrode of the first NMOS tube 6 and the grid electrode of the second NMOS tube 7. The grid electrode of the first PMOS tube 4 is respectively connected with the grid electrode and the drain electrode of the second PMOS tube 5, the grid electrode of the first PMOS tube 8 in the operational amplifier circuit 2, the grid electrode of the second PMOS tube 13 in the operational amplifier circuit 2 and the drain electrode of the second NMOS tube 7; the drain electrode of the second PMOS tube 5 is respectively connected with the grid electrode of the first PMOS tube 4, the grid electrode of the second PMOS tube and the drain electrode of the second NMOS tube 7; the grid electrode of the first NMOS tube 6 is respectively connected with the drain electrode of the first PMOS tube 4, the grid electrode of the first NMOS tube 6 and the grid electrode of the second NMOS tube 7. The drain electrode of the second NMOS transistor 7 is connected to the gate electrode and the drain electrode of the second PMOS transistor 5, the gate electrode of the first PMOS transistor 8 in the operational amplifier circuit 2, the gate electrode of the second PMOS transistor 13 in the operational amplifier circuit 2, and the gate electrode of the first PMOS transistor 4, respectively. The grid electrode of the second NMOS tube 7 is respectively connected with the grid electrode and the drain electrode of the first NMOS tube 6 and the drain electrode of the first PMOS tube 4. The source electrode of the second NMOS tube 7 is connected with one end of a resistor R1; the other end of the resistor is connected with the source of the first NMOS transistor 6 and the common ground GND.
Electrical principle of the invention an operational amplifier circuit is depicted in dashed line part in fig. 1, with a current bias input of the operational amplifier circuit 2 being connected to an output of the current source generating circuit 1. The positive phase of the differential input terminal of the operational amplifier 2 is grounded, the negative phase is connected to the output terminal of the reference generation circuit 3, and the output terminal of the operational amplifier circuit 2 is connected to the input terminal of the reference generation circuit 3.
The source electrode of the first PMOS tube 8 and the source electrode of the second PMOS tube 13 in the operational amplifier circuit are respectively connected with a common power supply VDD. The grid electrode of the first PMOS tube 8 is respectively connected with the grid electrode of the first PMOS tube 4 of the current source generating circuit 1, the grid electrode and the drain electrode of the second PMOS tube 5 of the current source generating circuit 1 and the grid electrode of the second PMOS tube. The drain electrode of the first PMOS tube 8 is respectively connected with the source electrode of the third PMOS tube 9 and the source electrode of the fourth PMOS tube 10, the grid electrode of the third PMOS tube 9 is connected with the common ground GND, and the drain electrode of the third PMOS tube 9 is respectively connected with the drain electrode of the first NMOS tube 11, the third NMOS tube 14 and one end of the capacitor C. The source electrode of the third PMOS tube 9 is respectively connected with the drain electrode of the first PMOS tube 8 and the drain electrode of the fourth PMOS tube 15. The grid electrode of the fourth PMOS transistor 10 is respectively connected with the drain electrode and the grid electrode of the first NMOS transistor 15 of the reference generating circuit 3 and one end of the resistor R2 of the reference generating circuit 3, and the drain electrode of the fourth PMOS transistor 15 is respectively connected with the grid electrode of the first NMOS transistor 11 and the grid electrode and the drain electrode of the second NMOS transistor (NM 4). The drain electrode of the first NMOS tube 11 is respectively connected with the drain electrode of the third PMOS tube 9, the grid electrode of the third NMOS tube 14 and one end of the capacitor C, and the grid electrode of the first NMOS tube 11 is respectively connected with the grid electrode and the drain electrode of the second NMOS tube 12 and the drain electrode of the fourth PMOS tube 10; the grid electrode of the second NMOS tube 12 is respectively connected with the grid electrode of the first NMOS tube 11, the drain electrode of the second NMOS tube 12 and the drain electrode of the fourth PMOS tube 10. The source of the second NMOS transistor 12 and the source of the first NMOS transistor 11 are respectively connected to the common ground GND, the gate of the second PMOS transistor 13 is respectively connected to the gate of the first PMOS transistor 8, the gate of the first PMOS transistor 4 of the current source generating circuit 1, the gate and the drain of the second PMOS transistor 5 of the current source generating circuit 1, and the drain of the second PMOS transistor 13 is respectively connected to the drain of the third NMOS transistor 14, one end of the capacitor C, and one end of the resistor R2 of the reference generating circuit 3. The grid electrode of the fourth NMOS transistor 14 is connected to the drain electrode of the first NMOS transistor 11, the drain electrode of the third PMOS transistor 9, and one end of the capacitor C, the drain electrode of the fourth NMOS transistor 14 is connected to the drain electrode of the second PMOS transistor 13, one end of the capacitor C, and one end of the resistor R2 of the reference generating circuit 3, and the source electrode of the fourth NMOS transistor 14 is connected to the common ground GND. One end of the capacitor C is connected to the drain of the third PMOS transistor 9, the drain of the first NMOS transistor 11, and the gate of the third NMOS transistor 14, and the other end of the capacitor C is connected to the drain of the second PMOS transistor, the drain of the third NMOS transistor, and one end of the resistor R2 in the reference generating module 3.
The electrical principle of the present invention is that in the reference generation circuit described by the dotted line portion in fig. 1, the input terminal of the reference generation circuit 3 is connected to the output terminal of the operational amplifier circuit 2, and the output terminal of the reference generation circuit 3 is connected to the negative phase terminal of the differential input of the operational amplifier circuit 2.
The drain of the first NMOS transistor 15 in the reference generating circuit is connected to one end of the resistor R2, the gate of the first NMOS transistor 15, and the gate of the fourth PMOS transistor 10 in the operational amplifier circuit 2. The source of the first NMOS transistor 15 is connected to the common ground GND, and the other end of the resistor R2 is connected to the drain of the second PMOS transistor 13 in the operational amplifier circuit 2, the drain of the third NMOS transistor 14 in the operational amplifier circuit 2, and one end of the capacitor C in the operational amplifier circuit 2.
The effect of the present invention will be further described with reference to the simulation diagram.
1. Simulation conditions are as follows:
the simulation experiment of the invention is based on an X-FAB XS018 CMOS process, and a Spectre simulation tool of Cadence software is applied. Carrying out temperature characteristic simulation during simulation, wherein the power supply voltage is set to be 1.8V and the simulation temperature is-20-125 ℃; during transient simulation, the simulation time is set to 1ms, the simulation temperature is set to normal temperature (25 ℃), and the power supply voltage is increased to 1.8V.
2. Simulation content:
under the LINUX operating system, temperature characteristic simulation is respectively carried out on the reference voltage source of the invention by applying a spectrum simulation tool of Cadence software based on an X-FAB XS018 CMOS process. When the temperature characteristic is simulated, the power supply voltage is set to be 1.8V, the simulation temperature range is from minus 20 ℃ to 125 ℃, and the device parameters are reasonably set, so that the reference voltage meets the requirement of zero temperature characteristic in the temperature range. During transient simulation, the simulation time is set to 1ms, the simulation temperature is set to normal temperature (25 ℃), the power supply voltage rises to 1.8V, and device parameters are reasonably set, so that the reference voltage can have quick response and can be kept stable all the time in the process.
3. And (3) simulation result analysis:
simulation diagram of the present invention fig. 2 is a simulation diagram of temperature characteristics. The axis of abscissa in fig. 2 represents temperature, and the axis of ordinate represents voltage. As can be seen from the simulation chart of the present invention in FIG. 2, the abscissa of the point A is 49.6 ℃ and the ordinate is 883.05mV, which indicates the magnitude of the reference voltage 883.05mV when the temperature is 49.6 ℃. The abscissa of the point B was-20 ℃ and the ordinate was 879.97mV, indicating that the magnitude of the reference voltage was 879.97mV when the temperature was-20 ℃. The difference between the temperature at the two points of the maximum value and the minimum value of the reference voltage when the temperature is changed within the range of-20 ℃ to 125 ℃ is 3.08mV., the temperature coefficient of the reference voltage is 20 ppm/DEG C, and the requirement of zero-temperature characteristic of the reference voltage is met.
Simulation diagram of the present invention fig. 3 is a simulation diagram of transient simulation. The axis of abscissa in fig. 3 represents time, and the axis of ordinate represents voltage. As can be seen from the simulation chart of the present invention shown in FIG. 3, the abscissa of the point M3 is 14.09. mu.s, and the ordinate is 882.71mV, indicating that the magnitude of the reference voltage is 882.71mV at 14.09. mu.s. The simulation graph of the invention shown in fig. 3 shows that in the process of increasing the power voltage to 1.8V, the reference voltage has quick response, rapidly increases to 882.71mV, and is always stable, thereby meeting the requirements of quick response and stability of the reference voltage. The power consumption of the reference voltage is calculated to be 1 muW when the power supply voltage is 1.8V, and the requirement that the reference voltage is low in power consumption is met.
The simulation result shows that the invention overcomes the defects of complex circuit structure, high power consumption, slow circuit response speed and the like in the prior art, has small reference voltage change, fast response, high stability and low power consumption in a wide temperature range, and meets the requirements of the performance indexes of the reference voltage source.
Claims (4)
1. A reference voltage source with zero temperature coefficient bias point comprises a current source generating circuit (1) and an operational amplifier circuit (2), and is characterized by also comprising a reference generating circuit (3); the output end of the current source generating circuit (1) is connected with the current bias input end of the operational amplifier circuit (2), and the current bias input end of the operational amplifier circuit (2) is connected with the output end of the current source generating circuit (1); the positive phase end of the differential input end of the operational amplifier (2) is grounded, the negative phase end of the differential input end of the operational amplifier is connected with the output end of the reference generating circuit (3), and the output end of the operational amplifier circuit (2) is connected with the input end of the reference generating circuit (3); the input end of the reference generating circuit (3) is connected with the output end of the operational amplifier circuit (2), and the output end of the reference generating circuit (3) is connected with the negative phase end of the differential input of the operational amplifier (2).
2. The zero temperature coefficient bias point reference voltage source of claim 1, wherein: the source electrodes of a first PMOS (P-channel metal oxide semiconductor) tube (4) and a second PMOS tube (5) in the current source generating circuit (1) are respectively connected with a common power supply VDD; the drain electrode of the first PMOS tube (4) is respectively connected with the drain electrode and the grid electrode of the first NMOS tube (6) and the grid electrode of the second NMOS tube (7); the grid electrode of the first PMOS tube (4) is respectively connected with the grid electrode and the drain electrode of the second PMOS tube (5), the grid electrode of a first PMOS tube (8) in the operational amplifier circuit (2), the grid electrode of a second PMOS tube (13) in the operational amplifier circuit (2) and the drain electrode of a second NMOS tube (7); the drain electrode of the second PMOS tube (5) is respectively connected with the grid electrode of the first PMOS tube (4), the grid electrode of the second PMOS tube and the drain electrode of the second NMOS tube (7); the grid electrode of the first NMOS tube (6) is respectively connected with the drain electrode of the first PMOS tube (4), the grid electrode of the first NMOS tube (6) and the grid electrode of the second NMOS tube (7); the drain electrode of the second NMOS tube (7) is respectively connected with the grid electrode and the drain electrode of the second PMOS tube (5), the grid electrode of a first PMOS tube (8) in the operational amplifier circuit (2), the grid electrode of a second PMOS tube (13) in the operational amplifier circuit (2) and the grid electrode of a first PMOS tube (4); the grid electrode of the second NMOS tube (7) is respectively connected with the grid electrode and the drain electrode of the first NMOS tube (6) and the drain electrode of the first PMOS tube (4); the source electrode of the second NMOS tube (7) is connected with one end of a resistor R1; the other end of the resistor is connected with the source electrode of the first NMOS tube (6) and the common ground GND.
3. The zero temperature coefficient bias point reference voltage source of claim 1, wherein: the source electrode of a first PMOS (P-channel metal oxide semiconductor) tube (8) and the source electrode of a second PMOS tube (13) in the operational amplifier circuit (2) are respectively connected with a common power supply VDD; the grid electrode of the first PMOS tube (8) is respectively connected with the grid electrode of the first PMOS tube (4) of the current source generating circuit (1), the grid electrode and the drain electrode of the second PMOS tube (5) of the current source generating circuit (1) and the grid electrode of the second PMOS tube; the drain electrode of the first PMOS tube (8) is respectively connected with the source electrode of a third PMOS tube (9) and the source electrode of a fourth PMOS tube (10); the grid electrode of the third PMOS tube (9) is connected with the common ground GND; the drain electrode of the third PMOS tube (9) is respectively connected with the drain electrode of the first NMOS tube (11), the third NMOS tube (14) and one end of the capacitor C; the source electrode of the third PMOS tube (9) is respectively connected with the drain electrode of the first PMOS tube (8) and the drain electrode of the fourth PMOS tube (15); the grid electrode of the fourth PMOS tube (10) is respectively connected with the drain electrode and the grid electrode of the first NMOS tube (15) of the reference generating circuit (3) and one end of the resistor R2 of the reference generating circuit (3); the drain electrode of the fourth PMOS tube (15) is respectively connected with the grid electrode of the first NMOS tube (11), the grid electrode and the drain electrode of the second NMOS tube (NM 4); the drain electrode of the first NMOS tube (11) is respectively connected with the drain electrode of the third PMOS tube (9), the grid electrode of the third NMOS tube (14) and one end of the capacitor C; the grid electrode of the first NMOS tube (11) is respectively connected with the grid electrode and the drain electrode of the second NMOS tube (12) and the drain electrode of the fourth PMOS tube (10); the grid electrode of the second NMOS tube (12) is respectively connected with the grid electrode of the first NMOS tube (11), the drain electrode of the second NMOS tube (12) and the drain electrode of the fourth PMOS tube (10); the source electrode of the second NMOS tube (12) and the source electrode of the first NMOS tube (11) are respectively connected with a common ground GND; the grid electrode of the second PMOS tube (13) is respectively connected with the grid electrode of the first PMOS tube (8), the grid electrode of the first PMOS tube (4) of the current source generating circuit (1), and the grid electrode and the drain electrode of the second PMOS tube (5) of the current source generating circuit (1); the drain electrode of the second PMOS tube (13) is respectively connected with the drain electrode of the third NMOS tube (14), the other end of the capacitor C and one end of a resistor R2 of the reference generating circuit (3); the grid electrode of the fourth NMOS tube (14) is respectively connected with the drain electrode of the first NMOS tube (11), the drain electrode of the third PMOS tube (9) and one end of the capacitor C; the drain electrode of the fourth NMOS tube (14) is respectively connected with the drain electrode of the second PMOS tube (13), the other end of the capacitor C and one end of the resistor R2 of the reference generating circuit (3), and the source electrode of the fourth NMOS tube (14) is connected with the common ground GND; one end of the capacitor C is respectively connected with the drain electrode of the third PMOS tube (9), the drain electrode of the first NMOS tube (11) and the grid electrode of the third NMOS tube (14); the other end of the capacitor C is respectively connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and one end of the resistor R2 in the reference generation module (3).
4. The zero temperature coefficient bias point reference voltage source of claim 1, wherein: the drain electrode of a first NMOS tube (15) in the reference generating circuit (3) is respectively connected with the other end of the resistor R2, the grid electrode of the first NMOS tube (15) and the grid electrode of a fourth PMOS tube (10) in the operational amplifier circuit (2); the source electrode of the first NMOS tube (15) is connected with a common ground GND; one end of the resistor R2 is connected with the drain electrode of the second PMOS tube (13) in the operational amplifier circuit (2), the drain electrode of the third NMOS tube (14) in the operational amplifier circuit (2) and one end of the capacitor C in the operational amplifier circuit (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010040053.1A CN111158422A (en) | 2020-01-15 | 2020-01-15 | Reference voltage source with zero temperature coefficient bias point |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010040053.1A CN111158422A (en) | 2020-01-15 | 2020-01-15 | Reference voltage source with zero temperature coefficient bias point |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111158422A true CN111158422A (en) | 2020-05-15 |
Family
ID=70562902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010040053.1A Pending CN111158422A (en) | 2020-01-15 | 2020-01-15 | Reference voltage source with zero temperature coefficient bias point |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111158422A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112416044A (en) * | 2020-12-03 | 2021-02-26 | 电子科技大学 | Voltage reference circuit with high power supply rejection ratio |
| CN114690827A (en) * | 2022-04-14 | 2022-07-01 | 无锡力芯微电子股份有限公司 | Bias circuit for inhibiting reference voltage from second stable state |
| CN115220514A (en) * | 2021-04-16 | 2022-10-21 | 中国科学院微电子研究所 | Voltage reference source, chip and electronic equipment |
| WO2023103748A1 (en) * | 2021-12-06 | 2023-06-15 | 深圳飞骧科技股份有限公司 | Low-voltage detection circuit |
| TWI832306B (en) * | 2021-09-14 | 2024-02-11 | 華邦電子股份有限公司 | Temperature compensation circuit and semiconductor integrated circuit using the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4464588A (en) * | 1982-04-01 | 1984-08-07 | National Semiconductor Corporation | Temperature stable CMOS voltage reference |
| US5945821A (en) * | 1997-04-04 | 1999-08-31 | Citizen Watch Co., Ltd. | Reference voltage generating circuit |
| US20050237104A1 (en) * | 2004-04-27 | 2005-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reference voltage generator circuit having temperature and process variation compensation and method of manufacturing same |
| US7122997B1 (en) * | 2005-11-04 | 2006-10-17 | Honeywell International Inc. | Temperature compensated low voltage reference circuit |
| CN110308757A (en) * | 2019-05-22 | 2019-10-08 | 长沙景美集成电路设计有限公司 | A kind of low-power consumption low supply voltage reference circuit |
-
2020
- 2020-01-15 CN CN202010040053.1A patent/CN111158422A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4464588A (en) * | 1982-04-01 | 1984-08-07 | National Semiconductor Corporation | Temperature stable CMOS voltage reference |
| US5945821A (en) * | 1997-04-04 | 1999-08-31 | Citizen Watch Co., Ltd. | Reference voltage generating circuit |
| US20050237104A1 (en) * | 2004-04-27 | 2005-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reference voltage generator circuit having temperature and process variation compensation and method of manufacturing same |
| US7122997B1 (en) * | 2005-11-04 | 2006-10-17 | Honeywell International Inc. | Temperature compensated low voltage reference circuit |
| CN110308757A (en) * | 2019-05-22 | 2019-10-08 | 长沙景美集成电路设计有限公司 | A kind of low-power consumption low supply voltage reference circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112416044A (en) * | 2020-12-03 | 2021-02-26 | 电子科技大学 | Voltage reference circuit with high power supply rejection ratio |
| CN115220514A (en) * | 2021-04-16 | 2022-10-21 | 中国科学院微电子研究所 | Voltage reference source, chip and electronic equipment |
| TWI832306B (en) * | 2021-09-14 | 2024-02-11 | 華邦電子股份有限公司 | Temperature compensation circuit and semiconductor integrated circuit using the same |
| WO2023103748A1 (en) * | 2021-12-06 | 2023-06-15 | 深圳飞骧科技股份有限公司 | Low-voltage detection circuit |
| CN114690827A (en) * | 2022-04-14 | 2022-07-01 | 无锡力芯微电子股份有限公司 | Bias circuit for inhibiting reference voltage from second stable state |
| CN114690827B (en) * | 2022-04-14 | 2024-02-06 | 无锡力芯微电子股份有限公司 | Bias circuit for inhibiting reference voltage second steady state |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111158422A (en) | Reference voltage source with zero temperature coefficient bias point | |
| CN1316619C (en) | Internal power supply for IC with temp. compensating pedestal generator | |
| CN104007777B (en) | A kind of current source generator | |
| CN113760029B (en) | Novel low dropout linear regulator based on full MOS reference source | |
| CN113703510B (en) | Band gap reference circuit with low power consumption | |
| CN108363447B (en) | Low-temperature coefficient full MOS type current source circuit with process compensation | |
| Xu et al. | A 28 ppm/° C, 2.54 ppm/V,− 77 dB@ 100 Hz pico-ampere voltage reference for high-end IoT systems | |
| CN111026221A (en) | Voltage reference circuit working under low power supply voltage | |
| CN112462835B (en) | Low-voltage linear voltage stabilizer | |
| CN111796624B (en) | CMOS voltage reference circuit with ultrahigh power supply ripple rejection ratio | |
| CN211603985U (en) | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process | |
| CN110879625B (en) | CMOS voltage reference circuit with ultralow linear sensitivity | |
| CN111813177A (en) | High-performance CMOS voltage reference source with negative feedback | |
| Liu et al. | A low-quiescent current off-chip capacitor-less LDO regulator with UGCC compensation | |
| CN111796625A (en) | Ultra-low power consumption CMOS voltage reference circuit | |
| CN111352461A (en) | Negative voltage reference circuit based on CMOS (complementary metal oxide semiconductor) process | |
| CN115840486A (en) | Curvature compensation band gap reference circuit | |
| CN110568902B (en) | Reference voltage source circuit | |
| CN212276289U (en) | High-performance CMOS voltage reference source with negative feedback | |
| CN111026219B (en) | Reference source of cascode structure | |
| CN113176802A (en) | Self-feedback multi-loop fully-integrated low-dropout linear regulator circuit | |
| CN113485504B (en) | Voltage reference circuit and circuit board with same | |
| CN115373460B (en) | Voltage reference source and integrated circuit | |
| CN102023670B (en) | Reference current generation circuit | |
| CN104267774A (en) | Simple linear power supply |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200515 |
|
| WD01 | Invention patent application deemed withdrawn after publication |