CN113485504B - Voltage reference circuit and circuit board with same - Google Patents
Voltage reference circuit and circuit board with same Download PDFInfo
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- CN113485504B CN113485504B CN202110754632.7A CN202110754632A CN113485504B CN 113485504 B CN113485504 B CN 113485504B CN 202110754632 A CN202110754632 A CN 202110754632A CN 113485504 B CN113485504 B CN 113485504B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a voltage reference circuit and a circuit board with the same, wherein the voltage reference circuit comprises a first on-off module, a first control end and a second control end, wherein the first on-off module comprises a first input end, a control end and an output end; the first reference module comprises a first power supply input end, a first grounding end and a first voltage output end vref _ lc, wherein the first power supply input end is connected with a power supply, and the first voltage output end vref _ lc is connected with the control end; the second reference module comprises a second power supply input end, a second grounding end and a second voltage output end, wherein the second power supply input end is connected with the output end, and the second grounding end is connected with the first grounding end; the second voltage output end is used for outputting the reference voltage, and the voltage reference circuit provided by the application can obviously reduce the sensitivity of the reference voltage to a power supply.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a voltage reference circuit and a circuit board with the same.
Background
In an integrated circuit chip, an analog circuit module, such as an ADC/DAC (analog-to-digital/digital-to-analog converter), an LDO (low dropout regulator), and the like, requires a voltage reference circuit to provide a reference voltage. The reference voltage is usually required to have very small changes with the process, the power supply voltage and the temperature, so that an analog circuit module in the system can work in a stable power supply environment to ensure the working performance.
In the prior art, a reference voltage vref at zero temperature coefficient (normal temperature) can be realized by adopting a depletion type NMOS transistor and an enhancement type NMOS transistor to carry out circuit design and adjusting the width-length ratio of a transistor channel, but the channel length of the transistor is too long, the design requirements of smaller chip area and short circuit starting time cannot be met, meanwhile, due to the existence of the channel length modulation effect of the transistor, the reference voltage vref has larger change along with the power supply voltage, particularly, under the current advanced process conditions, such as 28nm and 16nm processes, the power supply voltage dependency is worse, in order to improve the power supply rejection ratio and reduce the linear adjustment rate, a negative feedback circuit is introduced in the prior art to reduce the sensitivity of the reference voltage to the power supply, but the negative feedback circuit has the stability problem, the size of a feedback loop device needs to be carefully adjusted, a stability compensation circuit possibly needs to be added, and the circuit complexity is increased.
Disclosure of Invention
The present invention is directed to solve at least one of the problems of the prior art, and provides a voltage reference circuit and a circuit board having the same, which can significantly reduce the sensitivity of a reference voltage to a power supply.
The technical scheme adopted by the invention for solving the problems is as follows:
in a first aspect, an embodiment of the present invention provides a voltage reference circuit, including:
the first on-off module comprises a first input end, a control end and an output end, and the first input end is connected with the power supply;
the first reference module comprises a first power supply input end, a first grounding end and a first voltage output end vref _ lc, wherein the first power supply input end is connected with a power supply, and the first voltage output end vref _ lc is connected with the control end;
the second reference module comprises a second power supply input end, a second grounding end and a second voltage output end, the second power supply input end is connected with the output end of the first on-off module, and the second grounding end is connected with the first grounding end; the second voltage output end is used for outputting reference voltage.
The voltage reference circuit at least has the following beneficial effects: the voltage reference circuit comprises a first on-off module, a first reference module and a second reference module, wherein the first reference module generates a local reference voltage vref _ lc, the local reference voltage vref _ lc is input into the first on-off module, a starting voltage is provided for the first on-off module, the first on-off module is conducted, the output end of the first on-off module is connected with the input end of the second reference module, the output end voltage of the first on-off module is used as the input voltage vcc _ lc of the second reference module, the second reference module is conducted and generates a reference voltage vref, and through the circuit structure connection, the sensitivity of the reference voltage vref of the output end of the second reference module relative to the power voltage vcc can be effectively reduced, the power supply rejection ratio and the linear adjustment ratio of the reference voltage vref are optimized, in addition, the voltage reference circuit is simple in structure and works in a subthreshold region, and the design requirement of smaller chip area and shorter circuit starting time can be met.
According to the voltage reference circuit of the first aspect of the present invention, the first reference module includes a second transistor, a third transistor, a fourth transistor and a fifth transistor connected in series in this order, a drain of the second transistor is connected to the first power input terminal, a gate of the second transistor is connected to a gate of the third transistor, a source of the second transistor is connected to the first voltage output terminal vref _ lc, a source of the third transistor is connected to a source of the second transistor, a drain of the third transistor is connected to a gate of the third transistor, a source of the fourth transistor is connected to a drain of the third transistor, a drain of the fourth transistor is connected to a gate of the fourth transistor, a source of the fifth transistor MP3 is connected to a drain of the fourth transistor, and a drain of the fifth transistor is connected to a gate and to the first ground terminal.
According to the voltage reference circuit of the first aspect of the present invention, the second transistor is a depletion type NMOS transistor.
According to the voltage reference circuit of the first aspect of the present invention, the third transistor, the fourth transistor, and the fifth transistor are enhancement type PMOS transistors.
According to the voltage reference circuit of the first aspect of the present invention, the second reference module 300 includes a sixth transistor and a seventh transistor, a drain of the sixth transistor is connected to the second power input terminal, a gate of the sixth transistor is grounded, a source of the sixth transistor is connected to a drain of the seventh transistor, a drain of the seventh transistor is connected to a gate, and a source of the seventh transistor is connected to the second ground terminal.
According to the voltage reference circuit of the first aspect of the present invention, the sixth transistor is a depletion type NMOS transistor, and the seventh transistor is an enhancement type NMOS transistor.
According to the voltage reference circuit of the first aspect of the present invention, the first on-off module is an enhancement type NMOS transistor or a depletion type NMOS transistor.
In a second aspect, an embodiment of the present invention provides a circuit board, which includes a voltage reference circuit as described above.
The circuit board at least has the following beneficial effects: the circuit board comprises a first on-off module, a first reference module and a second reference module, wherein the first reference module generates a local reference voltage vref _ lc, the local reference voltage vref _ lc is input into the first on-off module, a starting voltage is provided for the first on-off module, the first on-off module is conducted, the output end of the first on-off module is connected with the input end of the second reference module, the output end voltage of the first on-off module is used as the input voltage vcc _ lc of the second reference module, the second reference module is conducted and generates a reference voltage vref, through the connection relation of the circuit structures, the sensitivity of the reference voltage vref of the output end of the second reference module relative to the power voltage vcc can be effectively reduced, the power supply rejection ratio and the linear adjustment ratio of the reference voltage vref are optimized, in addition, the voltage reference circuit is simple in structure and works in a sub-threshold area, and the design requirements of a small chip area and short circuit starting time can be met.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a circuit schematic of a voltage reference circuit provided by one embodiment of the present invention;
FIG. 2 is a circuit schematic of a voltage reference circuit provided by another embodiment of the present invention;
fig. 3 is a graph comparing the linear sensitivity characteristics of the voltage reference circuit provided herein with the corresponding prior art voltage reference circuit.
Reference numerals are as follows: the system comprises a first on-off module 100, a first reference module 200 and a second reference module 300.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. It should be noted that, if not conflicted, the various features of the embodiments of the invention may be combined with each other within the scope of protection of the invention.
In the description of the present invention, the first and second descriptions are only used for distinguishing technical features, and are not understood to indicate or imply relative importance or implicitly indicate the number of indicated technical features or implicitly indicate the precedence of the indicated technical features.
Referring to fig. 1, an embodiment of the present invention provides a voltage reference circuit, including a first on-off module 100, including a first input terminal, a control terminal, and an output terminal, where the first input terminal is connected to a power supply; the first reference module 200 comprises a first power input terminal, a first ground terminal and a first voltage output terminal vref _ lc, wherein the first power input terminal is connected with a power supply, and the first voltage output terminal vref _ lc is connected with the control terminal of the first on-off module 100; the second reference module 300 includes a second power input vcc _ lc, a second ground terminal and a second voltage output terminal, where the second power input vcc _ lc is connected to the output terminal of the first on-off module 100, and the second ground terminal is connected to the first ground terminal; the second voltage output end is used for outputting reference voltage.
In this embodiment, the first on-off module 100 is a MOS transistor, specifically, an enhanced NMOS transistor MN2, the first reference module 200 includes one NMOS transistor and three PMOS transistors, the second reference module 300 includes two NMOS transistors, after the power vcc is powered on, each transistor in the first reference module 200 works in a sub-threshold region, and the width-to-length ratio of each transistor is appropriately adjusted, so that the local reference voltage vref _ lc (the first voltage output terminal vref _ lc) with a zero temperature coefficient (normal temperature) can be provided. Due to the source-follower effect of the transistor MN2 of the first switching module 100, its source (second supply input) vcc _ lc voltage is substantially determined, approximately equal to its gate voltage minus its threshold voltage, when its gate vref _ lc voltage is determined. The source voltage calculation formula of the transistor MN2 of the first switching module 100 is shown in (1):
V(vcc_lc)＝V(vref_lc)-Vthn (1)
wherein Vthn is the threshold voltage of the transistor MN2 of the first switching module 100, and does not vary with the power supply voltage.
Assuming that the power source vcc voltage is V (vcc) 1, the corresponding vref _ lc and vcc _ lc voltages are V (vref _ lc) 1 and V (vcc _ lc) 1,
assuming that the voltage of the power source vcc is reduced to V (vcc) 2, the voltages of vref _ lc and vcc _ lc are reduced to V (vref _ lc) 2 and V (vcc _ lc) 2, respectively,
namely, the method comprises the following steps:
V(vcc_lc)1＝V(vref_lc)1-Vthn……………………(2)
V(vcc_lc)2＝V(vref_lc)2-Vthn……………………(3)
since Vthn does not vary with the power supply voltage, it can be obtained from equations (2) and (3)
V(vcc_lc)1-V(vcc_lc)2＝V(vref_lc)1-V(vref_lc)2 (4)
Namely: Δ vcc _ lc = Δ vref _ lc (5)
As can be seen from equation (5), the value of vcc _ lc as a function of power source vcc is the same as the value of vref _ lc as a function of power source vcc. Since the local reference voltage vref _ lc generated by the first reference module 200 (the first voltage output terminal vref _ lc) has a small variation value with the variation of the power source vcc voltage, process and temperature, and then the vcc _ lc also has a small variation value with the variation of the power source vcc voltage, process and temperature, then the reference voltage vref (the second voltage output terminal) generated by the second reference module 300 with the vcc _ lc as the power input has a smaller variation value with the variation of the power source vcc voltage, process and temperature, and the sensitivity of the reference voltage vref output by the final voltage reference circuit with respect to the power source input voltage vcc of the voltage reference circuit is significantly reduced through two-stage variation.
Assuming that the power vcc varies by Δ vcc, vref _ lc varies by Δ vref _ lc, as can be seen from the above analysis
Then there is
I.e. after the first reference module 200 and the second reference module 300 are connected in series, the rate of change of the generated second voltage output vref with the power supply vcc is the square of the rate of change of the voltage output with the power supply vcc generated by the single-stage reference module, i.e. the sensitivity to the power supply input voltage vcc is significantly reduced.
Fig. 3 is a linear sensitivity characteristic curve corresponding to the voltage reference circuit provided in an embodiment of the present invention, the first curve is a characteristic curve in an embodiment of the present invention, the second curve is a characteristic curve corresponding to the prior art, and as seen from the graph, when the power supply VCC changes from 3.3V to 1.1V (becomes smaller by 66.7%), the reference voltage corresponding to the prior art changes from 0.15479V to 0.14451V, becomes smaller by 6.64%, and the corresponding linear adjustment rate is 3.02%/V, the reference voltage generated by the voltage reference circuit of the present embodiment changes from 0.14805V to 0.14719V, becomes smaller by 0.58% (sensitivity), and the corresponding linear adjustment rate is 0.26%/V, it is known from comparative data that the voltage reference circuit provided in the present application significantly reduces the sensitivity of the reference voltage to the power supply, and reduces the linear adjustment rate of the reference voltage.
The linear adjustment rate is an error of the output reference voltage due to a change in the power supply voltage, and the linear adjustment rates corresponding to the first curve and the second curve in fig. 3 will be described below.
The linear adjustment rate is calculated by the formula:
calculating a first linear adjustment rate according to equation (8) as:
calculating a second linear adjustment rate according to equation (8) as:
referring to fig. 1, in an embodiment, the first reference module 200 includes a second transistor MNA3, a third transistor MP1, a fourth transistor MP2 and a fifth transistor MP3 connected in series in sequence, a drain of the second transistor MNA3 is connected to the first power input terminal VCC, a gate of the second transistor MNA3 is connected to a gate of the third transistor MP1, a source of the second transistor MNA3 is connected to the first voltage output terminal vref _ lc, a source of the third transistor MP1 is connected to a source of the second transistor MNA3, a drain and a gate of the third transistor MP1 are connected, a source of the fourth transistor MP2 is connected to a drain of the third transistor MP1, a drain and a gate of the fourth transistor MP2 are connected, a source of the fifth transistor MP3 is connected to a drain of the fourth transistor MP2, a drain and a gate of the fifth transistor MP3 are connected to the first ground terminal, and the second ground terminal are connected to the ground.
In one embodiment, the second transistor MNA3 is a depletion transistor, the corresponding threshold voltage is usually less than zero volts, the third transistor MP1, the fourth transistor MP2 and the fifth transistor MP3 are enhancement transistors, the threshold voltage is usually several volts, the second transistor MNA3, the third transistor MP1, the fourth transistor MP2 and the fifth transistor MP3 all operate in a sub-threshold region, and the local reference voltage vref _ lc at zero temperature coefficient can be provided by properly adjusting the width-to-length ratio of the MNA3, MP1, MP2 and MP3 transistors.
Referring to fig. 1, in an embodiment, the second reference module 300 includes a sixth transistor MNA1 and a seventh transistor MN1, a drain of the sixth transistor MNA1 is connected to the second power input terminal and connected to the output terminal of the first on-off module 100, a gate of the sixth transistor MNA1 is grounded, a source is connected to a drain of the seventh transistor MN1, a drain of the seventh transistor MN1 is connected to the gate, a source is connected to the second ground terminal and grounded to the first ground terminal, the sixth transistor MNA1 is a depletion type NMOS transistor, and the seventh transistor MN1 is an enhancement type NMOS transistor.
Referring to fig. 2, in another embodiment of the present application, the first switching module 100 may also be a transistor MNA2, and the first power input terminal of the first reference module 200 is connected to the power vcc; the first reference module 200 generates a local reference voltage vref _ lc to bias the gate of the first on/off module transistor MNA 2; the drain electrode of the first on-off module transistor MNA2 is connected with the power source vcc, and the source electrode of the transistor MNA2 is used as the input power source of the second reference module 300; compared with the embodiment in fig. 1, the first on-off module MNA2 is a depletion transistor, and because the threshold voltage is less than zero volts, the power supply voltage value of the whole voltage reference circuit for normal operation can be reduced, and the number of stages of the PMOS transistors stacked in the first reference module 200 can be reduced, thereby reducing the area.
It should be noted that the first switching module 100 may also be formed by combining one or more other transistors, so as to implement the switching control function in the present application.
In addition, another embodiment of the present invention further provides a circuit board, which includes the voltage reference circuit as in any one of the above embodiments. The circuit board has the beneficial effects brought by the voltage reference circuit in any of the above embodiments, that is, the circuit board can effectively reduce the sensitivity of the reference voltage vref at the output end of the second reference module 300 relative to the power supply voltage vcc by arranging the circuit structures of the first on-off module 100, the first reference module 200 and the second reference module 300, and optimize the power supply rejection ratio and the linear adjustment rate of the reference voltage vref.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.
Claims (6)
1. A voltage reference circuit, comprising:
the first on-off module comprises a first input end, a control end and an output end, and the first input end is connected with the power supply;
the first reference module comprises a first power supply input end, a first grounding end and a first voltage output end vref _ lc, wherein the first power supply input end is connected with a power supply, and the first voltage output end vref _ lc is connected with the control end;
the second reference module comprises a second power supply input end vcc _ lc, a second grounding end and a second voltage output end, wherein the second power supply input end vcc _ lc is connected with the output end of the first on-off module, and the second grounding end is connected with the first grounding end; the second voltage output end is used for outputting reference voltage; wherein,
the second reference module comprises a sixth transistor and a seventh transistor, wherein the drain of the sixth transistor is connected with the second power input end, the gate of the sixth transistor is grounded, the source of the sixth transistor is connected with the drain of the seventh transistor, the drain of the seventh transistor is connected with the gate, and the source of the seventh transistor is connected with the second ground end;
the first reference module comprises a second transistor, a third transistor, a fourth transistor and a fifth transistor which are sequentially connected in series, wherein the drain electrode of the second transistor is connected with the first power supply input end, the grid electrode of the second transistor is connected with the grid electrode of the third transistor, the source electrode of the second transistor is connected with the first voltage output end vref _ lc, the source electrode of the third transistor is connected with the source electrode of the second transistor, the drain electrode of the third transistor is connected with the grid electrode of the third transistor, the source electrode of the fourth transistor is connected with the drain electrode of the third transistor, the drain electrode of the fourth transistor is connected with the grid electrode of the fourth transistor, the source electrode of the fifth transistor is connected with the drain electrode of the fourth transistor, and the drain electrode of the fifth transistor is connected with the grid electrode and the first grounding end.
2. A voltage reference circuit according to claim 1, wherein: the second transistor is a depletion type NMOS transistor.
3. A voltage reference circuit according to claim 1, wherein: the third transistor, the fourth transistor, and the fifth transistor are enhancement type PMOS transistors.
4. A voltage reference circuit according to claim 1, wherein: the sixth transistor is a depletion type NMOS transistor, and the seventh transistor is an enhancement type NMOS transistor.
5. A voltage reference circuit according to claim 1, wherein: the first on-off module is an enhancement type NMOS transistor or a depletion type NMOS transistor.
6. A circuit board, characterized by: comprising a voltage reference circuit as claimed in any one of claims 1-5.
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| CN202110754632.7A CN113485504B (en) | 2021-07-05 | 2021-07-05 | Voltage reference circuit and circuit board with same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6285242B1 (en) * | 1999-02-05 | 2001-09-04 | United Microelectronics Corporation | Reference voltage shifter |
| JP5481926B2 (en) * | 2009-05-18 | 2014-04-23 | 富士通セミコンダクター株式会社 | Power supply control device, power supply device, and power supply control method |
| CN102298434B (en) * | 2010-06-23 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | A kind of SOC (system on a chip) |
| US9323263B2 (en) * | 2012-09-25 | 2016-04-26 | Intel Corporation | Low dropout regulator with hysteretic control |
| CN103941792B (en) * | 2013-01-21 | 2016-06-01 | 西安电子科技大学 | Bandgap voltage reference circuit |
| CN104793689A (en) * | 2015-04-10 | 2015-07-22 | 无锡中星微电子有限公司 | Reference voltage source circuit |
| CN206479869U (en) * | 2017-02-28 | 2017-09-08 | 建荣集成电路科技(珠海)有限公司 | Low voltage bandgap reference, chip, portable power source and drive recorder |
| CN107908216B (en) * | 2017-11-28 | 2019-08-30 | 电子科技大学 | A kind of non-bandgap non-resistance a reference source |
| CN110703010A (en) * | 2019-09-25 | 2020-01-17 | 珠海亿智电子科技有限公司 | Test circuit |
| CN111290459B (en) * | 2020-02-11 | 2021-10-22 | 杭州未名信科科技有限公司 | Voltage reference source circuit |
| CN111796624B (en) * | 2020-07-27 | 2022-02-18 | 东南大学 | CMOS voltage reference circuit with ultrahigh power supply ripple rejection ratio |
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