JP3134343B2 - Bandgap reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit, and more particularly to a reference voltage generating circuit which stabilizes an output voltage by using negative feedback.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a constant voltage circuit for stabilizing an output voltage by using negative feedback is often used as a reference voltage source. For example, a bandgap reference voltage circuit described in Japanese Patent Application No. 1-324386 is a typical example, and is frequently used in a bipolar integrated circuit as a reference voltage source having extremely small temperature dependence.

FIG. 7A is a circuit diagram of an example of a conventional bandgap reference voltage generating circuit, and FIG. 7B is a circuit diagram thereof. In the figure, transistors Q _{3 to} Q ₆ and a resistor R
₄ constitute the differential amplifier 10, and the transistors Q ₇ and Q
Is constituted current amplifier Ai ₈ and the resistor R _5, the constant current source 11 supplies the operating current of the entire circuit. Here, negative feedback control is performed so that the inverting input terminal and the non-inverting input terminal of the differential amplifier 10 have the same potential. Capacitor C
Reference numeral ₁ denotes a phase compensation capacitor for reducing a feedback voltage gain (loop gain) in a high frequency band to prevent oscillation.

Here, the resistance R₁, R_TwoCurrent flowing through each
To I₁, I_TwoAnd the transistor Q ₁Base Emi
Voltage between terminals_BE1And Transistor Q₁, Q_TwoNo
Source current and the input bias current of the differential amplifier 10,
Output voltage V_BGIs given by
You.

[0005]

(Equation 1)

(Where k is the Boltzmann constant, T is the absolute temperature, and q is the charge of the electron.) V _{BE1 in} the first term on the right-hand side has a negative temperature coefficient of approximately −2 mV / ° C., while I ₁ > I second term from the _second relation can zero temperature coefficient of the output voltage V _BG by choosing the value of resistor R ₂ since having a positive temperature coefficient appropriately.

[0007]

In the conventional circuit, the transistors Q ₄ and Q _{7 have} a base-emitter voltage drop of 0.7.
Assuming that the output voltage V _BG is 1.2 V, the capacitor C
₁ of the connection point A and the base of the transistor Q ₇ substantially 0.5 by the base-emitter voltage drop of the transistor Q ₇
A V, the connection point B and the base of the transistor Q ₄ of the capacitor C ₁ is substantially 0.8V voltage drop 0.1V resistor and base-emitter voltage drop 0.7V transistors Q ₄ R _4. However, the voltage drop between the base and the emitter of the transistor has a temperature characteristic of about -2 mV / ° C.
At 7V, the connection point B becomes approximately 0.6V. That can not use the junction capacitor that uses a PN junction in reverse bias state as a capacitor C ₁ since the polarity of the capacitor C ₁ across is reversed by a temperature change, without the use of large MOS capacitor chip area compared to The chip area had to be large.

Further, since the constant current source 11 supplies the operating current and the output current of the entire circuit, the current driving capability of the constant current source 11 must be large including the fluctuation of the output current depending on the load, and the chip area is large. Was getting bigger.

The present invention has been made in view of the above points,
By connecting the active load of the differential amplifier to a point having a predetermined potential higher than the reference voltage and outputting the differential amplifier output through the two-stage emitter follower, the output current increases, and the phase compensation capacitor has a small capacity and a small area. It is intended to be.

[0010]

A bandgap reference voltage generating circuit according to the present invention amplifies an output from a bandgap circuit by a differential amplifier provided with a phase compensation capacitor and outputs a bandgap voltage. In the generating circuit, a common emitter of a transistor constituting a current mirror circuit which is an active load of the differential amplifier is connected to a point having a predetermined potential higher than an output terminal potential of a reference voltage, and an output of the differential amplifier is connected to the emitter as a constant current source. Are extracted by the PNP transistor of the emitter follower connected thereto, and the output of the PNP transistor of the emitter follower is extracted and output by the NPN transistor of the emitter follower.

[0011]

According to the present invention, a PNP transistor and an NP
The output current increases due to the two-stage emitter follower with the N-transistor, the frequency characteristics are good, the phase compensation capacitor can be made small, and the active load of the differential amplifier is connected to a point of a predetermined potential higher than the reference voltage. Since the differential amplifier can be normally biased, the polarity of both ends of the phase compensation capacitor does not reverse due to temperature change, and the area can be reduced by using a junction capacitor. Current consumption can be reduced.

[0012]

FIG. 1 is a circuit diagram showing a first embodiment of the circuit of the present invention. In the figure, the same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, a Zener diode D_ZAnd resistance R
_FiveAnd NPN transistor Q₉Constitutes a constant voltage source,
Transistor Q₉Is the potential V of the output terminal 20._BG(Example
For example, a predetermined value V larger than 1.2 V)₁(For example, 5V or less
Above), and a transistor that is a current mirror type active load.
Star Q_Five, Q₆Connected to a common emitter. Emi
PNP transistor Q of ttafollower configuration₇Emitter of
Is the power supply voltage V via the constant current source 21._CCTo the power supply terminal 22
Connected and the collector is grounded. This transis
NPN transformer with emitter follower configuration
Jista Q_TenOf the transistor Q_TenNo
The collector is connected to the power terminal 22 and the emitter is the output terminal
20. This output terminal 20 has a resistor
R₁, R _TwoOne end of each is connected.

Here, the PNP transistor Q₇Emi of
Tafollower and NPN transistor Q ₈Emitter follower
The output circuit is composed of two stages of emitter followers.
As a result, the current amplification is increased, the output current is increased, and
Output voltage is stabilized. In addition, the constant current source 21
Output current I₀Is set to an appropriate value and the current mirror active
Load PNP transistor Q_Five, Q₆Base current and energy
Mitter follower PNP transistor Q₇Base current
Are approximately the same, the input offset of the differential amplifier is
Can be minimized.

Further, since the transistor Q ₇ is the collector is grounded, can use a substrate PNP transistor whose collector is connected to the substrate, the substrate PNP transistor is high current amplification factor than the Terateru PNP transistor Therefore, the chip area can be reduced.

[0016] Since the transistor Q _5, high potential V ₁ than the output voltage V _BG (1.2V) to the emitter of Q ₆ is applied, the transistor Q _5, Q ₆ each base-emitter voltage of 0 .7V and can be normally biased,
The differential amplifier can operate stably.

In the above embodiment, the transistor Q ₃
~Q and conduct only voltage amplification at the portion of the composed the differential amplifiers ₆ and a resistor R _4, the loop gain is lowered at high frequencies by the resistor R ₂ and the phase compensation capacitor C _1. Loop gain _A vLOO _P is expressed by the following equation when the frequency is sufficiently high.

A _vLOOP = α / (ωR ₂ C ₁ ) where α is the transistors Q ₁ , Q ₂ , resistors R ₁ , R ₂ ,
The damping ratio due to R ₃ , ω is the angular frequency.

Therefore, the loop gain is determined by the resistances R ₁ , R ₂ , R
It is determined by ₃ and the capacitor C ₁ to be stable. Further, except for the differential amplifier, the voltage dividing circuit and the emitter follower circuit have good frequency characteristics, and the frequency characteristics of the whole circuit are good. That is, by using the emitter follower circuit, the capacitor C1 can have a smaller capacitance of about 3 pF than the conventional _one . Therefore, even if a MOS capacitor is used, the area can be reduced.

Further, the connection point A of the capacitor C ₁ is transistor Q _7, the base-emitter voltage drop V _BE of Q ₁₀ are offset output voltage V _BG clogging approximately 1.2V, and the connection point B of the capacitor C ₁ is V _BE and resistance R of transistor Q ₄
It becomes about 0.8V when the voltage drop of ₄ is 0.1V. For example, even if the temperature rises by 100 ° C., the voltage at the connection point A does not change to about 1.2 V, and the voltage at the connection point B becomes about 0.6 V. The polarity at both ends of the capacitor C ₁ does not change due to the temperature change. Therefore, a junction capacitor using a PN junction in a reverse bias state can be used as the capacitor C ₁ .
Chip area can be reduced.

Since the transistors Q ₇ and Q ₁₀ and the two-stage emitter follower are used, the output current of the terminal 20 is several m.
A, which is much larger than the conventional value of several tens μA. In addition, fluctuations in the output voltage _VBG due to changes in the output current and the like are significantly reduced. The constant current source 21 is composed of a circuit portion of the transistors Q ₁ and Q ₂ and the resistors R _{1 to} R ₃ , an operating current of each of the differential amplifiers, a bias current of the emitter follower transistor Q ₇ , and a base current of the emitter follower transistor Q ₁₀ . large output current just to supply the transistor Q ₁₀
Is supplying. Conventionally, the current value of the current source is set to be relatively large in anticipation of the output fluctuation. However, the fluctuation also becomes 1 / amplification factor, so that the margin becomes small. Therefore, the current consumption of the entire circuit becomes, for example, 130 μA. In contrast, the current consumption of the conventional circuit is smaller than 170 μA. Transistors Q _9, Q ₁₀ relative to the conventional circuit of FIG. 7 in the above embodiment, the resistor R _5, despite have added Zener diode D _Z, use a junction capacitor to the capacitor C _1, a constant current source Since the size of the chip 21 can be reduced, the chip area of the embodiment of FIG. 1 is smaller.

Furthermore, when a voltage drop across the constant current source 21 and V _CE, the power supply voltage V _CC by the V _BE of the output voltage V _BE and transistor Q ₁₀ is the relation of the following equation.

V _CC ≧ V _BG + V _CE + V _BE Here, for example, V _BG is 1.2 V, V _CE is 0.1 V, V _BE
Is 0.7 V, the circuit operates normally when V _CC is 2 V or more, and the power supply voltage V _CC can be lower than in the prior art.

2 to 5 show circuit diagrams of another embodiment of the circuit of the present invention.

The embodiment of FIG. 2 instead of the constant voltage source and the Zener diode D _Z and the resistor R ₅ and the transistor Q ₉ NP
N transistors Q ₁₁ and Q ₁₂ and a constant current source 23 are provided. Transistor Q ₁₁ is connected to the collector to the power supply terminal 22 is connected to the emitter to the common emitter of the transistors Q _5, Q _6, the base-collector to the constant current source 23
Is connected. The base of the transistor Q ₁₁ is connected to the emitter of the transistor Q _12, the transistor Q ₁₂
Is connected to the base to the emitter of the transistor Q _7, it is grounded collector.

For this reason, the base emitter of each transistor
V_BEThen, the transistor Q_Five, Q₆of
The potential of the common emitter is equal to the potential V of the terminal 20._BGTransi
Star Q_TenAnd Q₁₂V_BEAre added, and the transistor Q₁₁
V_BEIs subtracted from V _BG+ V_BEFixed to

In the embodiment of FIG. 3, PN is used instead of the constant voltage source.
A P-transistor Q ₁₃ is provided with a constant current source 24. Transistor Q ₁₃ is connected to base terminal 20, a grounded collector, emitter is connected to the power supply terminal 22 via the constant current source 24. Also in this embodiment, the transistor Q
_5, the common emitter of Q ₆ by transistors Q _13, V _BE of the transistor Q ₁₃ to a potential V _BG terminal 20 is fixed to V _BG + V _BE to be added.

In the embodiment of FIG. 4, instead of the constant voltage source, N
PN transistor Q ₁₄ and diode D ₁ is provided. The transistor Q ₁₄ has an emitter connected to the transistor Q ₅ ,
It is connected to the common emitter of Q _6, a base constant current source 21
And the anode of the diode D ₁ , and the collector is connected to the power supply terminal 22. The emitter and the transistor Q ₁₀ of the diode D ₁ of the cathode transistor Q ₇
Connected to the base.

Also in this embodiment, the transistors Q ₅ and Q ₆ are set such that the forward voltage drop of the PN junction of the diode D ₁ is V _BE.
Potential of the common emitter of the potential V _BE of the terminal 20 transistors Q ₁₀ and diode D ₁ of the V _BE is added, is fixed to V _BG + V _BE to V _BE of the transistor Q ₁₄ is subtracted.

In the embodiment shown in FIG. 5, the PNP transistor Q
And it provided _15, which further transistor Q ₁₆ is provided downstream of the transistor Q _10. Transistor Q _5, the emitter of Q ₆ is connected to the power supply terminal 22, the transistor Q _5,
The emitter of the transistor Q ₁₅ to Kokureta the base and the transistor Q ₆ of Q ₆ are connected, the transistor Q ₁₅ is connected to the base to the collector of the transistor Q _5, the base and collector of the transistor Q ₄ of the transistor Q ₇ to the collector It is connected to the. The emitter of the transistor Q ₁₀ is connected to an output terminal 20 via a resistor R ₆ is connected to the base of NPN transistor Q _16, the transistor Q ₁₆ is connected to the collector to the power supply terminal 22, output emitter is connected to the terminal 20 has a transistor Q ₁₀ and the Darlington connection configuration.

In this embodiment, the transistors Q ₅ and Q ₆
Thereby improving the accuracy of the current mirror circuit by adding Q ₁₅ in. The FIG 2 that increases the output current of several tens mA by Darlington-connected transistors Q ₁₀ and Q ₁₆
Examples of to 5 can be obtained even large output current, only a small chip area small capacitance of the capacitor C _1,
As in the embodiment of FIG. 1, the current consumption of the circuit is reduced, and the power supply voltage V _CC is reduced. However, in the embodiments of FIGS. 4 and 5, the power supply voltage V _CC needs to be higher than V _BG + 2 · V _BE , for example, higher than 2.7 V.

[0032] In order to improve the accuracy of the current mirror circuit, may be added an emitter resistor to the people transistors Q _5, Q ₆ respectively, may be added to the transistor Q ₁₅ as shown in FIG. 5, also the transistor Q ₅ , Q ₆ may be reduced in area instead of a single multi-collector PNP transistor. The output circuit of the emitter follower may perform output by three or more stages of emitter followers or Darlington connection, or may add or replace a level shift diode with a level shift diode.
Further, a push-pull output may be used, and the present invention is not limited to the above embodiment.

Also, the transistor Q in the preceding stage of the differential amplifier
₁ , Q ₂ and resistors R _{1 to} R ₃ may be modified or added within a range that does not change its purpose, such as by replacing the transistor Q ₂ with the resistor R ₃ as shown in FIG. good. The Figure 1, in the embodiment of FIG. 6 is generating potential V ₁ with a Zener diode D _Z, may generate a potential V ₁ at another constant voltage circuit. Further, each of the transistors Q ₁₂ and Q _{13 in} FIGS. 2 and 3 may be replaced with a diode, and is not limited to the above embodiment.

[0034]

As described above, according to the reference voltage generating circuit of the present invention, the output current increases, and the phase compensation capacitor has a small capacity. Therefore, even if a MOS capacitor is used, the chip area can be reduced. Can be used, and the chip area can be further reduced, which is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the circuit of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the circuit of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the circuit of the present invention.

FIG. 4 is a circuit diagram of another embodiment of the circuit of the present invention.

FIG. 5 is a circuit diagram of another embodiment of the circuit of the present invention.

FIG. 6 is a circuit diagram of another embodiment of the circuit of the present invention.

FIG. 7 is a circuit diagram and a circuit configuration diagram of a conventional circuit.

[Explanation of symbols]

Q _{1 to} Q ₁₆ transistors R _{1 to} R ₆ resistors C ₁ phase compensation capacitor

Claims (1)

(57) [Claims] In a band gap reference voltage generating circuit for amplifying an output from a band gap circuit by a differential amplifier provided with a phase compensation capacitor and outputting a band gap voltage, a current mirror as an active load of the differential amplifier is provided. Connect the common emitter of the transistors constituting the circuit to a point of a predetermined potential higher than the output terminal potential of the reference voltage,
An output of the differential amplifier is taken out by an emitter follower PNP transistor having an emitter connected to a constant current source, and an output of the emitter follower PNP transistor is taken out by an emitter follower NPN transistor and output. Reference voltage generation circuit.