CN106843352B - Band-gap reference circuit - Google Patents

Band-gap reference circuit Download PDF

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Publication number
CN106843352B
CN106843352B CN201710068655.6A CN201710068655A CN106843352B CN 106843352 B CN106843352 B CN 106843352B CN 201710068655 A CN201710068655 A CN 201710068655A CN 106843352 B CN106843352 B CN 106843352B
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resistance
transistor
pmos transistor
nmos pass
band
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CN106843352A (en
Inventor
周宁
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Abstract

The invention discloses a kind of band-gap reference circuit, including：First PMOS transistor (Pmirr), first nmos pass transistor (NMO), first operational amplifier (YF1), first PNP transistor (Q0), second PNP transistor (Q1), first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R0).The present invention can provide certain current driving ability for the reference voltage V BG of output.

Description

Band-gap reference circuit
Technical field
The present invention relates to semiconductor integrated circuit field, more particularly to a kind of band-gap reference circuit.
Background technology
Voltage reference circuit is the basic module in analogue layout, such as digital analog converter (DAC), analog-to-digital conversion It is all indispensable in the circuit designs such as device (ADC), linear voltage regulator (LDO).Traditional band-gap reference circuit uses negative temperature system Several bipolar transistor tube voltage VBE reduces the temperature coefficient of output voltage with mode that positive temperature coefficient voltage VT is added.
Fig. 1 is existing band-gap reference circuit schematic diagram, it includes start-up circuit and band-gap reference main body circuit.In Fig. 1, Band-gap reference main body circuit is by PMOS transistor PM3, PM4, PM5, operational amplifier YF2, resistance R6 and R7, triode Q2, Q3 Formed with Q4, wherein the base stage of triode Q2, Q3 and Q4 and collector link together in diode-connected, triode Q2 and Q3 Transmitting junction area ratio be 1:N, wherein N are the integer more than 1, usually take 8 or 24 etc., such triode Q2 Base-Emitters electricity Press Vbe_Q2More than triode Q3 base-emitter voltages Vbe_Q3, since operational amplifier makes node voltage VN=VP=Vbe_Q2, institute With electric current I5=(Vbe_Q2-Vbe_Q3)/R7, Δ Vbe are (Vbe_Q2-Vbe_Q3) there is positive temperature coefficient, so electric current I5 be with it is absolute The electric current of temperature directly proportional (Proportional To Absolute Temperature, PTAT).PMOS tube PM5 and PM4, PM3 forms current mirror circuit so that the image current that the electric current I6 on PMOS tube PM5 paths is electric current I5, I6=K*I5, its Middle K is the proportionality coefficient of PMOS transistor PM5 and PM4 or PM3, and electric current I6 is by resistance R6 and connects into the three of diode structure Pole pipe Q4 connections, output reference voltage VBG is by I6 × R6+Vbe_Q4Determine,
That is VBG=I6 × R6+Vbe_Q4=Vbe_Q4+ K* (R6/R7) * Δ Vbe, wherein Vbe_Q4Sent out for the base stage of triode Q4 Emitter voltage, I6 have positive temperature coefficient, Vbe_Q4With negative temperature coefficient, the temperature coefficient of such reference voltage V BG can just be adjusted Section.
Start-up circuit includes NMOS tube NCAP, PMOS tube PM6, resistance RST；Since supply voltage passes through resistance during startup RST charges to NMOS tube NCAP, and the voltage of node NST, which can slowly rise, turns on PMOS tube PM6, PMOS tube PM3, PM4 and PM5 Grid voltage be pulled low so as to turning on, thus there is electric current to be injected into band-gap reference main body circuit and make circuit start；Work as section After the voltage of point NST is charged to supply voltage, PMOS tube PM6 cut-offs, start-up circuit is closed.The driving of existing band-gap reference circuit Ability is poor, and when the output terminal of reference voltage V BG, which has, takes out electric current, which can only be provided by the image current of PMOS tube PM5, So flowing through the electric current of R6 and triode Q4 will reduce or not have, so that reference voltage V BG easily declines.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of band-gap reference circuit, can be that the reference voltage V BG of output is carried For certain current driving ability.
In order to solve the above technical problems, the band-gap reference circuit of the present invention, including：
First PMOS transistor Pmirr, the first nmos pass transistor NMO, the first operational amplifier YF1, the first PNP transistor Q0, the second PNP transistor Q1, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, Six resistance R0；
The source electrode of first PMOS transistor Pmirr is connected with power voltage terminal VDD, its grid and current biasing circuit Output terminal PB is connected, it drains and one end of 3rd resistor R3, the drain electrode of the first nmos pass transistor NMO and the 4th resistance R4 One end be connected, the reference voltage V BG output terminals of the node of the connection as band-gap reference circuit；
The other end of the 3rd resistor R3 is connected with one end of one end of first resistor R1 and second resistance R2；
The emitter and the first operational amplifier YF1 of the other end of the first resistor R1 and the first PNP transistor Q0 Reverse input end is connected；The base stage and grounded collector of first PNP transistor Q0；
The one of the positive input of the first operational amplifier YF1 and the other end of second resistance R2 and the 6th resistance R0 End is connected, and the other end of the 6th resistance R0 is connected with the emitter of the second PNP transistor Q1；Second PNP transistor Q1's Base stage and grounded collector；
The output terminal of the first operational amplifier YF1 is connected with the grid of the first nmos pass transistor NMO, the first NMOS The source electrode ground connection of transistor NMO；
The other end of the 4th resistance R4 is connected with one end of the 5th resistance R5, another termination of the 5th resistance R5 Ground.
Band-gap reference circuit using the present invention can provide certain driving without buffer, output reference voltage；Same work( Under consumption, due to having shared the 6th resistance R0 and Q1, twice of electric current has flowed through 3rd resistor R3, can save the area of chip；Can line Property partial pressure output less than VBG any reference voltage；Branch pressure voltage VREF, which can be realized, linearly to be trimmed.
Brief description of the drawings
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is traditional band-gap reference circuit schematic diagram；
The improved one embodiment schematic diagrams of band-gap reference circuit of Fig. 2；
Fig. 3 is driving force emulation schematic diagram.
Embodiment
With reference to shown in Fig. 2, which is improved one embodiment of band-gap reference circuit, further includes one in this embodiment as institute State the current biasing circuit that band-gap reference circuit provides bias current, and the start-up circuit of the current biasing circuit.
The start-up circuit of the current biasing circuit, including：4th PMOS transistor PSTP, the 5th PMOS transistor PST With the 4th nmos pass transistor Ncap.
The source electrode of 4th PMOS transistor PSTP and the source electrode of the 5th PMOS transistor PST are connected with power voltage terminal VDD Connect, its grid is connected with the grid of the second PMOS transistor PM0 in the current biasing circuit, the 3rd PMOS transistor PM1. Drain electrode and the grid of the 5th PMOS transistor PST and the grid phase of the 4th nmos pass transistor Ncap of 4th PMOS transistor PSTP Connection.The source electrode and grounded drain of 4th nmos pass transistor Ncap.
The current biasing circuit, including：Second PMOS transistor PM0, the 3rd PMOS transistor PM1, the 2nd NMOS are brilliant Body pipe NM1 and the 3rd nmos pass transistor NM2, and the 7th resistance Rb.
The source electrode of second PMOS transistor PM0 and the source electrode of the 3rd PMOS transistor PM1 are connected with power voltage terminal VDD Connect.
The grid of second PMOS transistor PM0 and the grid of the 3rd PMOS transistor PM1 and drain electrode and the 3rd NMOS are brilliant Body pipe NM2 is connected with drain electrode.The drain electrode of second PMOS transistor PM0 and the grid of the second nmos pass transistor NM1 and drain electrode, the The drain electrode of three nmos pass transistor NM2 grids and the 5th PMOS transistor PST in the start-up circuit is connected.
The source electrode ground connection of the second nmos pass transistor NM1, the source electrode of the 3rd nmos pass transistor NM2 and the 7th resistance Rb's One end is connected, the other end ground connection of the 7th resistance Rb.
The band-gap reference circuit, including：
First PMOS transistor Pmirr, the first nmos pass transistor NMO, the first operational amplifier YF1, the first PNP transistor Q0, the second PNP transistor Q1, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, Six resistance R0.
The source electrode of first PMOS transistor Pmirr is connected with power voltage terminal VDD, its grid and current biasing circuit Output terminal PB is connected, it drains and one end of 3rd resistor R3, the drain electrode of the first nmos pass transistor NMO and the 4th resistance R4 One end be connected, the reference voltage V BG output terminals of the node of the connection as band-gap reference circuit.
The other end of the 3rd resistor R3 is connected with one end of one end of first resistor R1 and second resistance R2.
The emitter and the first operational amplifier YF1 of the other end of the first resistor R1 and the first PNP transistor Q0 Reverse input end is connected；The base stage and grounded collector of first PNP transistor Q0.
The one of the positive input of the first operational amplifier YF1 and the other end of second resistance R2 and the 6th resistance R0 End is connected, and the other end of the 6th resistance R0 is connected with the emitter of the second PNP transistor Q1；Second PNP transistor Q1's Base stage and grounded collector.
The output terminal of the first operational amplifier YF1 is connected with the grid of the first nmos pass transistor NMO, the first NMOS The source electrode ground connection of transistor NMO.
The other end of the 4th resistance R4 is connected with one end of the 5th resistance R5, another termination of the 5th resistance R5 Ground.
4th resistance R4 and the 5th resistance R5 partial pressures produce branch pressure voltage VREF；After power supply electrifying, current biasing circuit is first Establish, the electric current of the 3rd PMOS transistor PM1 of current biasing circuit is band gap base described in the first PMOS transistor Pmirr mirror images Quasi- circuit provides operating current, wherein electric current I0=I1+I3+I4, and band-gap reference circuit, which is established, produces reference voltage V BG.Due to First PMOS transistor Pmirr mirror images produce electric current I0, can provide certain electric current driving energy for the reference voltage V BG of output Power.When having sourcing current on reference voltage V BG, which is provided by I0, has no effect on the electric current I1 for producing reference voltage V BG, So that reference voltage V BG has certain driving force.In Fig. 2,
R1=R2
12=(Vbe_Q0-Vbe_Q1)/R0
I1=2*I2
1 and N is proportionate relationship in Fig. 1,2, is usually 1：8 or 1：24.
Driving force emulation is shown in Figure 3.Wherein, the ordinate of Fig. 3 (a) represents electric current μ A；Fig. 3 (b), Fig. 3 (c) and The ordinate of Fig. 3 (d) represents voltage V, and abscissa represents time μ S.Fig. 3 (a) is the load electricity of band-gap reference output voltage terminal Stream, Fig. 3 (b) are that the output 1.25V, Fig. 3 (c) of traditional bandgap reference circuit are the output of improved band-gap reference circuit 1.25V, Fig. 3 (d) are the linear partial pressure 0.8V of improved band-gap reference circuit output voltage.Can from result shown in figure Go out, the output voltage of traditional bandgap reference circuit can be pulled low when drawing load current, improved band-gap reference circuit it is defeated Go out voltage to be basically unchanged when drawing load current.
The present invention is described in detail above by embodiment, but these are not formed to the present invention's Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims (5)

  1. A kind of 1. band-gap reference circuit, it is characterised in that including：
    First PMOS transistor (Pmirr), the first nmos pass transistor (NMO), the first operational amplifier (YF1), the first PNP crystal Manage (Q0), the second PNP transistor (Q1), first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4), 5th resistance (R5), the 6th resistance (R0)；
    The source electrode of first PMOS transistor (Pmirr) is connected with power voltage terminal VDD, its grid and current biasing circuit it is defeated Outlet PB is connected, it drains and one end of 3rd resistor (R3), the drain electrode of the first nmos pass transistor (NMO) and the 4th resistance (R4) one end is connected, the reference voltage V BG output terminals of the node of the connection as band-gap reference circuit；
    The other end of the 3rd resistor (R3) is connected with one end of one end of first resistor (R1) and second resistance (R2)；
    The other end of the first resistor (R1) and the emitter of the first PNP transistor (Q0) and operational amplifier (YF1) it is anti- It is connected to input terminal；The base stage and grounded collector of first PNP transistor (Q0)；
    The positive input of first operational amplifier (YF1) and the other end of second resistance (R2) and the 6th resistance (R0) One end is connected, and the other end of the 6th resistance (R0) is connected with the emitter of the second PNP transistor (Q1)；2nd PNP crystal Manage the base stage and grounded collector of (Q1)；
    The output terminal of first operational amplifier (YF1) is connected with the grid of the first nmos pass transistor (NMO), the first NMOS The source electrode ground connection of transistor (NMO)；
    The other end of 4th resistance (R4) is connected with one end of the 5th resistance (R5), another termination of the 5th resistance (R5) Ground.
  2. 2. band-gap reference circuit as claimed in claim 1, it is characterised in that further include：One current biasing circuit, it includes： Second PMOS transistor (PM0), the 3rd PMOS transistor (PM1), the second nmos pass transistor (NM1) and the 3rd nmos pass transistor And the 7th resistance (Rb) (NM2),；
    The source electrode of second PMOS transistor (PM0) and the 3rd PMOS transistor (PM1) is connected with power voltage terminal VDD；Second The grid and drain electrode of the grid of PMOS transistor (PM0) and the 3rd PMOS transistor (PM1) are leaked with the 3rd nmos pass transistor (NM2) Pole is connected, output terminal PB of its node connected as current biasing circuit；
    The drain electrode of second PMOS transistor (PM0) and the drain and gate of the second nmos pass transistor (NM1) and the 3rd NMOS are brilliant The grid of body pipe (NM2) is connected；
    The source electrode ground connection of second nmos pass transistor (NM1), the source electrode and the 7th resistance (Rb) of the 3rd nmos pass transistor (NM2) One end be connected, the other end of the 7th resistance (Rb) ground connection.
  3. 3. band-gap reference circuit as claimed in claim 2, it is characterised in that further include：One current biasing circuit opens Dynamic circuit, it includes：4th PMOS transistor (PSTP), the 5th PMOS transistor (PST) and the 4th nmos pass transistor (Ncap)；
    The source electrode of 4th PMOS transistor (PSTP) is connected with power voltage terminal VDD, its grid and the current biasing circuit In the second PMOS transistor (PM0) be connected with the grid of the 3rd PMOS transistor (PM1)；
    The drain electrode of 4th PMOS transistor (PSTP) and the grid and the 4th nmos pass transistor of the 5th PMOS transistor (PST) (Ncap) grid is connected；The source electrode of 5th PMOS transistor (PST) is connected with power voltage terminal VDD；5th PMOS is brilliant The drain electrode of body pipe (PST) is connected with the drain and gate of the second nmos pass transistor (NM1) in the current biasing circuit；
    The source electrode and grounded drain of 4th nmos pass transistor (Ncap).
  4. 4. band-gap reference circuit as claimed in claim 2, it is characterised in that：After power supply electrifying, current biasing circuit is first established, The electric current of the 3rd PMOS transistor (PM1) of current biasing circuit is band gap base described in first PMOS transistor (Pmirr) mirror image Quasi- circuit provides operating current, and band-gap reference circuit, which is established, produces reference voltage V BG；First PMOS transistor (Pmirr) mirror image Electric current is produced, current driving ability is provided for the reference voltage V BG of output.
  5. 5. band-gap reference circuit as claimed in claim 1, it is characterised in that：Linear partial pressure output is less than reference voltage V BG's Any reference voltage.
CN201710068655.6A 2017-02-08 2017-02-08 Band-gap reference circuit Active CN106843352B (en)

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Application Number Priority Date Filing Date Title
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Publication number Priority date Publication date Assignee Title
CN111610812B (en) * 2019-02-26 2022-08-30 武汉杰开科技有限公司 Band-gap reference power supply generation circuit and integrated circuit
CN111381625B (en) * 2020-03-12 2022-05-20 上海华虹宏力半导体制造有限公司 Reference source circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9423033D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics A voltage reference circuit
US8149047B2 (en) * 2008-03-20 2012-04-03 Mediatek Inc. Bandgap reference circuit with low operating voltage
CN102073332B (en) * 2010-12-28 2012-07-04 华东师范大学 Low temperature coefficient complementary metal oxide semiconductor (CMOS) band-gap reference circuit of output belt low drop-out linear voltage regulator
CN102279611B (en) * 2011-05-11 2013-06-12 电子科技大学 Variable-curvature compensated bandgap voltage reference source
US9030186B2 (en) * 2012-07-12 2015-05-12 Freescale Semiconductor, Inc. Bandgap reference circuit and regulator circuit with common amplifier

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