CN116741225B - Clock correction circuit and memory - Google Patents
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- CN116741225B CN116741225B CN202311006147.7A CN202311006147A CN116741225B CN 116741225 B CN116741225 B CN 116741225B CN 202311006147 A CN202311006147 A CN 202311006147A CN 116741225 B CN116741225 B CN 116741225B
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- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 20
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 20
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- 239000004065 semiconductor Substances 0.000 description 5
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- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
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Abstract
Embodiments of the present disclosure provide a clock correction circuit and a memory, including: a delay phase-locked loop circuit and a duty cycle correction circuit; the delay phase-locked loop circuit receives an external clock signal and a feedback clock signal, adjusts a first adjustable delay circuit in the delay phase-locked loop circuit according to the phase difference of the external clock signal and the feedback clock signal so that the initial phase of the feedback clock signal is the same as the initial phase of the external clock signal in each clock period, and outputs an internal clock signal to the duty ratio correction circuit; the duty cycle correction circuit is used for determining the duty cycle corresponding to the internal clock signal according to the received internal clock signal output by the delay phase-locked loop circuit, and adjusting a second adjustable delay circuit in the duty cycle correction circuit according to the duty cycle so as to enable the duty cycle of the internal clock signal to be a preset duty cycle; the phase difference and the duty ratio are digital signals, so that the phase and the duty ratio can be quickly adjusted.
Description
Technical Field
Embodiments of the present disclosure relate to the field of semiconductor memory technology and other related technology, and in particular, to a clock correction circuit and a memory suitable for use therein.
Background
A Dynamic random access memory (Dynamic RandomAccessMemory, DRAM), also called main memory, is an internal memory that exchanges data directly with the CPU. It has the characteristics of fast reading and writing at any time, and is usually used as a temporary data storage medium of an operating system or other running programs.
When the internal circuit of the dynamic random access memory uses an external clock signal as an input signal, the clock signal is delayed and clock skew is generated due to the internal circuit, so that an output clock signal output from the dynamic random access memory is delayed. In order to compensate for clock skew so that the output clock signal output by the dynamic random access memory is equal to the phase of the external clock signal, a synchronization control circuit, such as a Delay-Locked Loop (DLL) circuit, is embedded in the internal circuit of the dynamic random access memory, and the DLL receives the external clock signal and controls the output time of the memory data to synchronize the DRAM output clock signal with the external clock signal. In addition, the clock signal supplied to the semiconductor device may be distorted by elements inside the semiconductor device when the semiconductor device transmits data or receives data. For example, a clock signal supplied to a semiconductor device may be delayed or a duty ratio of the clock signal may be changed, and thus a duty ratio correction circuit for compensating for the duty ratio of the clock signal is widely used in memories.
In the prior art, the duty ratio and the phase adjustment mostly adopt an accumulation or accumulation-reduction mode, and the problem of low adjustment speed exists.
Disclosure of Invention
Embodiments described herein provide a clock correction circuit and a memory to solve the problems of the prior art.
In a first aspect, according to the present disclosure, there is provided a clock correction circuit comprising: a delay phase-locked loop circuit and a duty cycle correction circuit;
wherein the delay locked loop circuit is configured to receive an external clock signal and a feedback clock signal, and adjust a first adjustable delay circuit in the delay locked loop circuit according to a phase difference of the external clock signal and the feedback clock signal so that an initial phase of the feedback clock signal and the external clock signal in each clock period is the same, and output an internal clock signal to the duty cycle correction circuit;
the duty cycle correction circuit is configured to determine a duty cycle corresponding to the internal clock signal according to the received internal clock signal output by the delay phase-locked loop circuit, and adjust a second adjustable delay circuit in the duty cycle correction circuit according to the duty cycle so that the duty cycle of the internal clock signal is a preset duty cycle;
wherein, the phase difference and the duty ratio are both digital signals.
In some embodiments of the present disclosure, optionally, the delay locked loop circuit includes at least: a first time-to-digital converter, a first decoder, and a first adjustable delay circuit;
wherein the first time-to-digital converter is configured to receive the external clock signal and the feedback clock signal and determine a phase difference of the external clock signal and the feedback clock signal;
the first decoder is configured to receive the phase difference output by the first time-to-digital converter, decode the phase difference, and output a first control signal corresponding to the phase difference to the first adjustable delay circuit.
In some embodiments of the present disclosure, optionally, the duty cycle correction circuit includes at least: the device comprises a clock processing unit, a charge pump, an analog-to-digital converter, a second decoder and a second adjustable delay circuit;
the clock processing unit is configured to receive an internal clock signal output by the delay locked loop circuit, and process the internal clock signal to obtain a target internal clock signal, wherein the target internal clock signal is a clock signal corresponding to at least one clock cycle in the internal clock signals;
the charge pump is configured to output an analog voltage signal after being charged and discharged in the period of the target internal clock signal, wherein the analog voltage signal is the voltage at two ends of a capacitor in the charge pump, and represents the duty ratio corresponding to the target internal clock signal;
the analog-to-digital converter is configured to receive the analog voltage signal and convert the analog voltage signal into a digital voltage signal;
and a second decoder configured to decode the digital voltage signal and output a second control signal corresponding to the digital voltage signal to the second adjustable delay circuit.
In some embodiments of the present disclosure, optionally, the duty cycle correction circuit includes at least a clock processing unit, a second time to digital converter, a subtractor, a second decoder, and a second adjustable delay chain;
the clock processing unit is configured to receive an internal clock signal output by the delay locked loop circuit, and process the internal clock signal to obtain a target internal clock signal, wherein the target internal clock signal is a clock signal corresponding to one clock cycle in the internal clock signals;
the second time-to-digital converter is configured to determine a duty ratio during which the target internal clock signal is at a high level based on the received target internal clock signal, and output digital voltage information corresponding to the duty ratio;
the subtracter is configured to determine digital voltage difference information between the digital voltage information and preset digital voltage information;
the second decoder is configured to receive the digital voltage difference information output by the subtracter, decode the digital voltage difference information, and output a second control signal corresponding to the digital voltage difference information to the second adjustable delay circuit.
In some embodiments of the present disclosure, optionally, the clock correction circuit further comprises a receiver and a transmitter; wherein the receiver is configured to receive the external clock signal and transmit the received external clock signal to the first adjustable delay circuit or transmit the received external clock signal to the second adjustable delay circuit, respectively;
the transmitter is configured to transmit an output clock signal.
In some embodiments of the present disclosure, optionally, the duty cycle correction circuit is located between the first adjustable delay circuit and the transmitter.
In some embodiments of the present disclosure, optionally, the duty cycle correction circuit is located between the receiver and the first adjustable delay circuit.
In some embodiments of the present disclosure, optionally, the duty cycle correction circuit further includes a current mirror circuit, a control terminal of the current mirror circuit is electrically connected to an output terminal of the second decoder, and an output terminal of the current mirror circuit is electrically connected to a second adjustable delay circuit;
the current mirror circuit is configured to control a current output to the second adjustable delay circuit according to a second control signal output from the second decoder.
In some embodiments of the present disclosure, optionally, the current mirror circuit includes a switch unit, a current mirror unit, a first transistor and a second transistor, the switch unit includes a plurality of switches, the current mirror unit includes a plurality of current mirrors, one of the switches is connected in series with one of the current mirrors, one of the switches and the current mirror connected in series form a current branch, and the plurality of current branches are connected in parallel;
the control end of each switch in the switch unit is electrically connected with the output end of the second decoder, the first end of each switch in the switch unit is electrically connected with the power supply voltage node, the second end of each switch in the switch unit is electrically connected with the first end of a current mirror of the current mirror unit, the second end of each current mirror is electrically connected with the first end and the control end of the first transistor, the second end of the first transistor is electrically connected with the grounding node, the control end of the second transistor is electrically connected with the control end of the first transistor, the first end of the second transistor is electrically connected with the second adjustable delay circuit, and the second end of the second transistor is electrically connected with the grounding node.
In a second aspect, according to the present disclosure, there is provided a memory comprising the clock correction circuit of any one of the first aspects.
The clock correction circuit and the memory provided by the embodiment of the disclosure, the delay locked loop circuit receives an external clock signal and a feedback clock signal, adjusts a first adjustable delay circuit in the delay locked loop circuit according to the phase difference of the external clock signal and the feedback clock signal so that the initial phase of the feedback clock signal is the same as the initial phase of the external clock signal in each clock period, and outputs an internal clock signal to the duty ratio correction circuit; the duty ratio correction circuit is configured to determine a duty ratio corresponding to the internal clock signal according to the received internal clock signal output by the delay phase-locked loop circuit, and adjust a second adjustable delay circuit in the duty ratio correction circuit according to the duty ratio so that the duty ratio of the internal clock signal is a preset duty ratio; the phase difference and the duty ratio are digital signals, and the phase difference and the duty ratio of the digital signals can quantize the phase information of the external clock signal and the feedback clock signal, and the duty ratio can quantize the duty ratio information corresponding to the high level interval of the internal clock signal in one clock period, so that the phase and the duty ratio can be quickly adjusted.
The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and may be implemented according to the content of the specification, so that the technical means of the embodiments of the present application can be more clearly understood, and the following specific embodiments of the present application are given for clarity and understanding.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
fig. 1 is a schematic circuit diagram of a clock correction circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic circuit diagram of another clock correction circuit provided by an embodiment of the present disclosure;
FIG. 3 is a schematic circuit diagram of a clock correction circuit according to another embodiment of the present disclosure;
FIG. 4 is a schematic circuit diagram of a clock correction circuit according to another embodiment of the present disclosure;
FIG. 5 is a schematic circuit diagram of a current mirror circuit according to an embodiment of the present disclosure;
wherein, 10, delay phase-locked loop circuit; 20. a duty cycle correction circuit; 30. a receiver; 40. a transmitter; 101. a first adjustable delay circuit; 102. a first time-to-digital converter; 103. a first decoder; 201. a second adjustable delay circuit; 202. a clock processing unit; 203. a charge pump; 204. an analog-to-digital converter; 205. a second decoder; 206. a second time-to-digital converter; 207. a subtracter; 208. a current mirror circuit; 2081. a switching unit; 2082. a current mirror unit; K. a switch; I. a current mirror; NMOS1, a first transistor; NMOS2, second transistor.
In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: there are three cases, a, B, a and B simultaneously. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present application, unless otherwise indicated, the meaning of "plurality" means two or more (including two), and similarly, "plural sets" means two or more (including two).
In order to make the person skilled in the art better understand the solution of the present application, the technical solution of the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings.
Based on the problems existing in the prior art, an embodiment of the present disclosure provides a clock correction circuit, and fig. 1 is a schematic structural diagram of the clock correction circuit provided in the embodiment of the present disclosure, as shown in fig. 1, the clock correction circuit includes: a delay locked loop circuit 10 and a duty correction circuit 20; wherein the delay locked loop circuit 10 is configured to receive the external clock signal CLK0 and the feedback clock signal CLK1, and adjust the first adjustable delay circuit 101 in the delay locked loop circuit 10 according to the phase difference between the external clock signal CLK0 and the feedback clock signal CLK1 so that the initial phase of the feedback clock signal CLK1 and the external clock signal CLK0 at each clock cycle is the same, and output the internal clock signal CLK2 to the duty cycle correction circuit 20; a duty cycle correction circuit 20 configured to determine a duty cycle corresponding to the internal clock signal CLK2 according to the received internal clock signal CLK2 output from the delay locked loop circuit 10, and adjust the second adjustable delay circuit 201 in the duty cycle correction circuit 20 according to the duty cycle so that the duty cycle of the internal clock signal CLK2 is a preset duty cycle; wherein, the phase difference and the duty cycle are both digital signals.
In the prior art, the feedback clock information and the external clock signal are adjusted through the delay phase-locked loop circuit so that the initial phases of the feedback clock signal and the external clock signal are the same, and the internal clock signal is adjusted through the duty cycle correction circuit, so that the duty cycle of the internal clock signal is stabilized at about 50%, namely the high level time and the low level time of the internal clock signal are the same. However, in the prior art, in the process of adjusting the clock signal by the delay locked loop circuit and the duty cycle correction circuit, the delay locked loop circuit and the duty cycle correction circuit adopt a feedback structure, wherein the delay locked loop circuit adjusts the phase according to the phase difference between the external clock signal and the feedback clock signal, the phase difference is an analog signal, that is, the phase of the feedback clock signal is advanced or retarded compared with the phase of the external clock signal by '1' or '0', for example, the output '1' indicates the phase of the feedback clock signal is advanced compared with the phase of the external clock signal, the output '0' indicates the phase of the feedback clock signal is retarded compared with the phase of the external clock signal, and the amount of the phase advance or the phase retard of the feedback clock signal compared with the phase of the external clock signal is not known, and the first adjustable delay circuit needs to adjust the initial phases of the external clock signal and the feedback clock signal by multiple times within each clock cycle is the same; the duty cycle correction circuit performs duty cycle adjustment according to the analog signal output by the phase detector, and the analog signal output by the phase detector usually adopts "1" or "0" to indicate that the duty cycle needs to be increased or decreased, for example, the output "1" indicates that the duty cycle needs to be increased, the output "0" indicates that the duty cycle needs to be decreased, and how much the increase or decrease is not known, and the second adjustable delay circuit needs to perform feedback adjustment for multiple times to achieve that the duty cycle is stabilized at about 50%, so that the rate of clock signal adjustment is low.
Based on the problems existing in the prior art, in the clock correction circuit provided in the embodiment of the disclosure, in the delay locked loop circuit 10, after the delay locked loop circuit 10 receives the external clock signal CLK0 and the feedback clock signal CLK1, according to the phase difference between the external clock signal CLK0 and the feedback clock signal CLK1 (the phase difference is a digital signal converted from the time difference between the rising edges of the external clock signal CLK0 and the feedback clock signal CLK1 in the same clock cycle), the first adjustable delay circuit 101 in the delay locked loop circuit 10 is adjusted, and since the phase difference determined based on the external clock signal CLK0 and the feedback clock signal CLK1 is a digital signal, when the first adjustable delay circuit 101 is adjusted based on the phase difference of the digital signal, the phase difference of the digital signal includes the time difference between the rising edges of the external clock signal CLK0 and the feedback clock signal CLK1, so that it can be determined how much the first adjustable delay circuit 101 is specifically adjusted, and the efficiency of adjusting the phase of the clock signal is improved. In contrast, in the duty cycle correction circuit 20, after receiving the internal clock signal CLK2 output from the delay locked loop circuit 10, the duty cycle corresponding to the internal clock signal CLK2 is determined (the duty cycle is a time-converted digital signal in which the internal clock signal CLK2 is in a high level section or a time-converted digital signal in which the internal clock signal CLK2 is in a low level section in one clock cycle), and therefore, when the duty cycle of the digital signal is adjusted based on the duty cycle of the digital signal, the duty cycle of the digital signal includes the time in the high level section or the time in the low level section of the internal clock signal CLK2 in the process of adjusting the second adjustable delay circuit 201 in the duty cycle correction circuit 20, and therefore, it is possible to determine how much to specifically adjust the second adjustable delay circuit 201, and to improve the duty cycle adjustment efficiency of the clock signal.
In the above embodiment, the preset duty ratio is 50%.
According to the clock correction circuit provided by the embodiment of the disclosure, a delay phase-locked loop circuit receives an external clock signal and a feedback clock signal, adjusts a first adjustable delay circuit in the delay phase-locked loop circuit according to the phase difference of the external clock signal and the feedback clock signal so that the initial phase of the feedback clock signal is the same as the initial phase of the external clock signal in each clock period, and outputs an internal clock signal to the duty cycle correction circuit; the duty ratio correction circuit is configured to determine a duty ratio corresponding to the internal clock signal according to the received internal clock signal output by the delay phase-locked loop circuit, and adjust a second adjustable delay circuit in the duty ratio correction circuit according to the duty ratio so that the duty ratio of the internal clock signal is a preset duty ratio; the phase difference and the duty ratio are digital signals, and the phase difference and the duty ratio of the digital signals can quantize the phase information of the external clock signal and the feedback clock signal, and the duty ratio can quantize the duty ratio information corresponding to the high level interval of the internal clock signal in one clock period, so that the phase and the duty ratio can be quickly adjusted.
With continued reference to fig. 1, the delay locked loop circuit 10 includes at least: a first time-to-digital converter 102, a first decoder 103 and a first adjustable delay circuit 101; wherein the first time-to-digital converter 102 is configured to receive the external clock signal CLK0 and the feedback clock signal CLK1 and determine a phase difference of the external clock signal CLK0 and the feedback clock signal CLK 1; the first decoder 103 is configured to receive the phase difference output by the first time-to-digital converter 102, and to decode the phase difference and output a first control signal corresponding to the phase difference to the first adjustable delay circuit 101.
In order to achieve fast adjustment of the clock signal phase, the delay locked loop circuit 10 includes a first time-to-digital converter 102, a first decoder 103 and a first adjustable delay circuit 101, where the first time-to-digital converter 102 receives the external clock signal CLK0 and the feedback clock signal CLK1, determines a phase difference (i.e., a time difference, the time difference is an analog signal) between the external clock signal CLK0 and the feedback clock signal CLK1 according to an initial phase of the external clock signal CLK0 and the feedback clock signal CLK1 in a same clock period, after determining the phase difference between the external clock signal CLK0 and the feedback clock signal CLK1, converts the analog signal representing the phase difference into a digital signal and sends the digital signal to the first decoder 103, and the first decoder 103 decodes the phase difference of the digital signal and outputs a first control signal to the first adjustable delay circuit 101, and adjusts the first adjustable delay circuit 101 through the first control signal so that the initial phase of the feedback clock signal CLK0 is the same as the initial phase of the external clock signal CLK 1.
It should be noted that, in the above embodiment, the phase difference between the external clock signal CLK0 and the feedback clock signal CLK1 is determined according to the initial phases of the external clock signal CLK0 and the feedback clock signal CLK1 in the same clock cycle, and as another implementation manner, the phase difference between the external clock signal CLK0 and the feedback clock signal CLK1 may be determined according to the end phases of the external clock signal CLK0 and the feedback clock signal CLK1 in the same clock cycle.
In the embodiment of the disclosure, the delay phase-locked loop circuit at least comprises a first time-to-digital converter, and the obtained analog signal phase difference of the external clock signal and the feedback clock signal is converted into a digital signal phase difference based on the first time-to-digital converter, so that the first adjustable delay circuit is quickly adjusted based on the digital signal phase difference, and the phase of the external clock signal and the phase of the feedback clock signal in the same clock cycle are the same.
With continued reference to fig. 1, on the basis of the above-described embodiment, the duty cycle correction circuit 20 includes at least: a clock processing unit 202, a charge pump 203, an analog-to-digital converter 204, a second decoder 205, and a second adjustable delay circuit 201; the clock processing unit 202 is configured to receive the internal clock signal CLK2 output by the delay locked loop circuit 10, and process the internal clock signal CLK2 to obtain a target internal clock signal, where the target internal clock signal is a clock signal corresponding to at least one clock cycle in the internal clock signal CLK 2; the charge pump 203 is configured to output an analog voltage signal after charging and discharging in a period of the target internal clock signal, where the analog voltage signal is a voltage across a capacitor in the charge pump 203, and the analog voltage signal represents a duty cycle corresponding to the target internal clock signal; an analog-to-digital converter 204 configured to receive the analog voltage signal and convert the analog voltage signal to a digital voltage signal; the second decoder 205 is configured to decode the digital voltage signal and then output a second control signal corresponding to the digital voltage signal to the second adjustable delay circuit.
In order to realize the fast adjustment of the duty ratio of the clock signal, the duty ratio correction circuit includes a clock processing unit 202, a charge pump 203, an analog-to-digital converter 204, a second decoder 205 and a second adjustable delay circuit 201, where the clock processing unit 202 receives an internal clock signal CLK2 output by the delay phase-locked loop circuit 10, the clock processing unit 202 processes the internal clock signal CLK2, selects a clock signal in at least one clock cycle as a target internal clock signal to send the target internal clock signal to the charge pump 203, the charge pump 203 charges the capacitor during the target internal clock signal (i.e. the target internal clock signal charges the capacitor in a high level interval and the target internal clock signal discharges the capacitor in a low level interval), outputs analog voltage signals corresponding to both ends of the capacitor (the analog voltage signals are voltages after charging and discharging in one clock cycle, since the capacitor is already charged to the preset voltage in the initial stage, in one clock period, the obtained voltage is the difference value of the compared preset voltage after the capacitor is charged and discharged, so that the conversion of the time difference signal of the high level and the low level into the voltage signal is realized, the analog voltage signal represents the duty ratio corresponding to the target internal clock signal, the analog-to-digital converter 204 outputs the digital voltage signal to the second decoder 205 after converting the analog voltage signal, the second decoder 205 decodes the digital voltage signal and then outputs the second control signal corresponding to the digital voltage signal to the second adjustable delay circuit 201, and the duty ratio of the internal clock signal is stabilized at 50% by adjusting the second adjustable delay circuit 201 through the second control signal.
It should be noted that, in the embodiment of the present disclosure, the target internal clock signal CLK2 is a clock signal corresponding to at least one clock cycle in the internal clock signals, in a specific embodiment, the number of clock cycles of the internal clock signals included in the target internal clock signal CLK2 is not specifically limited, and the more the number of clock cycles of the internal clock signals included in the target internal clock signal CLK2, the more accurate the obtained duty cycle information representing the internal clock signals.
In the embodiment of the present disclosure, by setting that the duty cycle correction circuit 20 includes at least an analog-to-digital converter 204, the analog voltage signal is converted into a digital voltage signal based on the analog-to-digital converter 204, and then the second control signal is output based on the digital voltage signal to adjust the second adjustable delay circuit 201, so as to realize rapid adjustment of the duty cycle of the clock signal.
On the basis of the above embodiment, fig. 2 is a schematic structural diagram of another clock correction circuit according to an embodiment of the present disclosure, and as shown in fig. 2, a duty cycle correction circuit 20 in the clock correction circuit includes at least a clock processing unit 202, a second time-to-digital converter 206, a subtractor 207, a second decoder 205, and a second adjustable delay chain 201; the clock processing unit 202 is configured to receive the internal clock signal CLK2 output by the delay locked loop circuit 10, and process the internal clock signal CLK2 to obtain a target internal clock signal, where the target internal clock signal is a clock signal corresponding to one clock cycle in the internal clock signals; a second time-to-digital converter 206 configured to determine a duty ratio during which the target internal clock signal is located at a high level (i.e., a period during which the target internal clock signal is located at a high level) based on the received target internal clock signal, and output digital voltage information corresponding to the duty ratio; a subtractor 207 configured to determine digital voltage difference information of the digital voltage information and preset digital voltage information; the second decoder 205 is configured to receive the digital voltage difference information output by the subtractor 207, and to output a second control signal corresponding to the digital voltage difference information to the second adjustable delay circuit 201 after decoding the digital voltage difference information.
In this embodiment, by setting that the duty cycle correction circuit 20 includes the clock processing unit 202, the second time-to-digital converter 206, the subtractor 207, the second decoder 205, and the second adjustable delay chain 201, the clock processing unit 202 receives the internal clock signal CLK2 output by the delay phase-locked loop circuit 10, the clock processing unit 202 processes the internal clock signal CLK2, selects a clock signal in one clock cycle as a target internal clock signal to send the target internal clock signal to the second time-to-digital converter 206, the second time-to-digital converter 206 acquires time information of the target internal clock signal during a high level period, converts the time information into digital voltage information corresponding to the time information, the subtractor 207 performs a difference between the received digital voltage information and preset digital voltage information (i.e., a digital voltage information corresponding to a time information of a half clock cycle of the target internal clock signal) to obtain digital voltage difference information (i.e., a time difference signal between the time of the target internal clock signal in the high level interval and the time of the half clock cycle of the target internal clock signal is converted into a digital voltage signal), the duty cycle corresponding to the internal clock signal and the preset duty cycle, that is greater than the preset duty cycle, i.e., the second duty cycle is greater than the preset duty cycle can be controlled by the second time-to be smaller than the second duty cycle, the second duty cycle can be controlled by the second time-to realize the second stable decoding, and the second duty cycle control circuit is smaller than the second duty cycle control signal, or the second duty cycle can be controlled by the second duty cycle control signal, and is stable, and the second duty cycle control circuit is stable.
On the basis of the above embodiments, in combination with fig. 1 or 2, the clock correction circuit further includes a receiver 30 and a transmitter 40; wherein the receiver 30 is configured to receive the external clock signal CLK0 and transmit the received external clock signal CLK0 to the first adjustable delay circuit 101 or transmit the received external clock signal CLK0 to the second adjustable delay circuit 201, respectively; and a transmitter configured to transmit the output clock signal.
As a specific embodiment, as shown in fig. 1 or fig. 2, the duty cycle correction circuit 20 is located between the first adjustable delay circuit 101 and the transmitter 40.
As another specific embodiment, as shown in fig. 3 or fig. 4, the duty cycle correction circuit is located between the receiver and the first adjustable delay circuit.
In the above embodiment, as shown in fig. 5, the duty cycle correction circuit further includes a current mirror circuit 208, a control terminal of the current mirror circuit 208 is electrically connected to an output terminal of the second decoder 205, and an output terminal of the current mirror circuit 208 is electrically connected to the second adjustable delay circuit 201; the current mirror circuit 208 is configured to control the current output to the second adjustable delay circuit 201 according to the second control signal output from the second decoder 205.
The current mirror circuit 208 includes a switch unit 2081, a current mirror unit 2082, a first transistor NMOS1 and a second transistor NMOS2, the switch unit 2081 includes a plurality of switches K, the current mirror unit 2081 includes a plurality of current mirrors I, a switch K is connected in series with a current mirror I, a current branch is formed by the switch K and the current mirror I connected in series, and the plurality of current branches are connected in parallel; the control end of each switch K in the switch unit 2081 is electrically connected to the output end of the second decoder 205, the first end of each switch K in the switch unit 2081 is electrically connected to the power supply voltage node VCC, the second end of each switch K in the switch unit 2081 is electrically connected to the first end of a current mirror I of the current mirror unit 2082, the second end of each current mirror I is electrically connected to the first end and the control end of the first transistor NMOS1, the second end of the first transistor NMOS1 is electrically connected to the ground node, the control end of the second transistor NMOS2 is electrically connected to the control end of the first transistor NMOS1, the first end of the second transistor NMOS2 is electrically connected to the second adjustable delay circuit 201, and the second end of the second transistor NMOS2 is electrically connected to the ground node.
The switching unit 2081 of the current mirror circuit 208 receives the second control signal output by the second decoder 205, the second control signal controls the on number of the switches K in the switching unit 2081, and adjusts the current flowing through the first transistor NMOS1 according to the on number of the switches K, the first transistor NMOS1 and the second transistor NMOS2 are mirror transistors, the second transistor NMOS2 mirrors the current flowing through the first transistor NMOS1, and sends the current to the second adjustable delay circuit 201, so as to control the current output to the second adjustable delay circuit 201 according to the second control signal output by the second decoder 205, and further realize the adjustment of the duty ratio by controlling the inverter.
On the basis of the above embodiments, the embodiments of the present disclosure further provide a memory, where the memory includes the clock correction circuit according to any one of the above embodiments, and has the beneficial effects described in any one of the above embodiments.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (7)
1. A clock correction circuit, comprising: a delay phase-locked loop circuit and a duty cycle correction circuit;
wherein the delay locked loop circuit is configured to receive an external clock signal and a feedback clock signal, and adjust a first adjustable delay circuit in the delay locked loop circuit according to a phase difference of the external clock signal and the feedback clock signal so that an initial phase of the feedback clock signal and the external clock signal in each clock period is the same, and output an internal clock signal to the duty cycle correction circuit;
the duty cycle correction circuit is configured to determine a duty cycle corresponding to the internal clock signal according to the received internal clock signal output by the delay phase-locked loop circuit, and adjust a second adjustable delay circuit in the duty cycle correction circuit according to the duty cycle so that the duty cycle of the internal clock signal is a preset duty cycle;
the delay locked loop circuit at least comprises: a first time-to-digital converter, a first decoder, and a first adjustable delay circuit;
the first time-to-digital converter is configured to receive the external clock signal and the feedback clock signal, determine a phase difference between the external clock signal and the feedback clock signal, and output digital voltage information corresponding to the phase difference;
the first decoder is configured to receive the digital voltage information corresponding to the phase difference output by the first time-to-digital converter, decode the digital voltage information corresponding to the phase difference, and output a first control signal corresponding to the phase difference to the first adjustable delay circuit;
the duty cycle correction circuit includes at least: the device comprises a clock processing unit, a charge pump, an analog-to-digital converter, a second decoder and a second adjustable delay circuit;
the clock processing unit is configured to receive an internal clock signal output by the delay locked loop circuit, process the internal clock signal to obtain a target internal clock signal, wherein the target internal clock signal is a clock signal corresponding to at least one clock cycle in the internal clock signal;
the charge pump is configured to output an analog voltage signal after being charged and discharged in the period of the target internal clock signal, wherein the analog voltage signal is the voltage at two ends of a capacitor in the charge pump, and represents the duty ratio corresponding to the target internal clock signal;
the analog-to-digital converter is configured to receive the analog voltage signal and convert the analog voltage signal into a digital voltage signal;
a second decoder configured to decode the digital voltage signal and output a second control signal corresponding to the digital voltage signal to the second adjustable delay circuit; or alternatively, the first and second heat exchangers may be,
the duty ratio correction circuit at least comprises a clock processing unit, a second time-to-digital converter, a subtracter, a second decoder and a second adjustable delay chain;
the clock processing unit is configured to receive an internal clock signal output by the delay locked loop circuit, and process the internal clock signal to obtain a target internal clock signal, wherein the target internal clock signal is a clock signal corresponding to one clock cycle in the internal clock signals;
the second time-to-digital converter is configured to determine a duty ratio during which the target internal clock signal is at a high level based on the received target internal clock signal, and output digital voltage information corresponding to the duty ratio;
the subtracter is configured to determine digital voltage difference information between the digital voltage information and preset digital voltage information;
the second decoder is configured to receive the digital voltage difference information output by the subtracter, decode the digital voltage difference information, and output a second control signal corresponding to the digital voltage difference information to the second adjustable delay circuit.
2. The clock correction circuit of claim 1, further comprising a receiver and a transmitter;
wherein the receiver is configured to receive the external clock signal and transmit the received external clock signal to the first adjustable delay circuit or transmit the received external clock signal to the second adjustable delay circuit, respectively;
the transmitter is configured to transmit an output clock signal.
3. The clock correction circuit of claim 2, wherein the duty cycle correction circuit is located between the first adjustable delay circuit and the transmitter.
4. The clock correction circuit of claim 2, wherein the duty cycle correction circuit is located between the receiver and the first adjustable delay circuit.
5. The clock correction circuit of claim 1, further comprising a current mirror circuit, a control terminal of the current mirror circuit being electrically connected to the output terminal of the second decoder, an output terminal of the current mirror circuit being electrically connected to a second adjustable delay circuit;
the current mirror circuit is configured to control a current output to the second adjustable delay circuit according to a second control signal output from the second decoder.
6. The clock correction circuit of claim 5, wherein the current mirror circuit comprises a switching unit, a current mirror unit, a first transistor and a second transistor, the switching unit comprising a plurality of switches, the current mirror unit comprising a plurality of current mirrors, one of the switches being connected in series with one of the current mirrors, one of the switches and the current mirror being connected in series to form a current branch, the plurality of current branches being connected in parallel;
the control end of each switch in the switch unit is electrically connected with the output end of the second decoder, the first end of each switch in the switch unit is electrically connected with a power supply voltage node, the second end of each switch in the switch unit is electrically connected with the first end of a current mirror of the current mirror unit, the second end of each current mirror is electrically connected with the first end and the control end of the first transistor, the second end of the first transistor is electrically connected with a grounding node, the control end of the second transistor is electrically connected with the control end of the first transistor, the first end of the second transistor is electrically connected with the second adjustable delay circuit, and the second end of the second transistor is electrically connected with the grounding node.
7. A memory comprising the clock correction circuit of any one of claims 1 to 6.
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| CN202311006147.7A CN116741225B (en) | 2023-08-10 | 2023-08-10 | Clock correction circuit and memory |
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