CN112821884A - Signal generation circuit, memory storage device and signal generation method - Google Patents

Signal generation circuit, memory storage device and signal generation method Download PDF

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CN112821884A
CN112821884A CN201911126811.5A CN201911126811A CN112821884A CN 112821884 A CN112821884 A CN 112821884A CN 201911126811 A CN201911126811 A CN 201911126811A CN 112821884 A CN112821884 A CN 112821884A
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circuit
signal
phase
bias voltage
bias
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CN112821884B (en
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吴仁钜
廖宇强
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Phison Electronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Exemplary embodiments of the present invention provide a signal generating circuit, a memory storage device and a signal generating method, the signal generating circuit including a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is used for generating a phase control signal according to the phase adjusting signal. The bias control circuit is used for generating a bias voltage according to the phase control signal. The phase interpolation circuit is used for generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.

Description

Signal generation circuit, memory storage device and signal generation method
Technical Field
The present invention relates to signal processing technologies, and in particular, to a signal generating circuit, a memory storage device, and a signal generating method.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Generally, a clock data recovery circuit is commonly installed at a signal receiving end to synchronize a data signal and a clock signal. Some clock data recovery circuits implement phase adjustment of clock signals by phase interpolation circuits. For example, the phase interpolation circuit can synthesize a clock signal with an arbitrary phase by the IQ clock. However, in practice, due to the limitation of hardware design, the clock signal output by the phase interpolation circuit is often not accurate enough.
Disclosure of Invention
The invention provides a signal generating circuit, a memory storage device and a signal generating method, which can generate more accurate clock signals.
An exemplary embodiment of the present invention is a signal generating circuit including a phase control circuit, a bias control circuit, and a phase interpolation circuit. The phase control circuit is used for generating a phase control signal according to the phase adjusting signal. The bias control circuit is connected to the phase control circuit and is used for generating a bias voltage according to the phase control signal. The phase interpolation circuit is connected to the phase control circuit and the bias control circuit and used for generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
In an exemplary embodiment of the present invention, the bias control circuit includes an encoding circuit and a bias circuit. The encoding circuit is connected to the phase control circuit and is used for generating a bias control signal according to the phase control signal. The bias circuit is connected to the encoding circuit and is used for generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the invention, the bias control circuit further includes a filter circuit. The filter circuit is connected to the bias circuit and the phase interpolation circuit and is used for filtering the first bias voltage to generate the bias voltage.
In an exemplary embodiment of the present invention, the phase interpolation circuit includes a driving circuit and a phase interpolator. The phase interpolator is connected to the driving circuit. The driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and the phase interpolator is used for generating the clock signal according to the current.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The clock data recovery circuit is arranged in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit. The clock data recovery circuit comprises a signal generating circuit. The signal generating circuit is used for generating a phase control signal according to the phase adjusting signal. The signal generating circuit is further used for generating a bias voltage according to the phase control signal. The signal generating circuit is further configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
In an exemplary embodiment of the present invention, the signal generating circuit includes an encoding circuit and a bias circuit. The encoding circuit is used for generating a bias control signal according to the phase control signal. The bias circuit is connected to the encoding circuit and is used for generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the present invention, the bias circuit includes a current source and at least one switch circuit. The at least one switch circuit is connected in series to the current source and is configured to adjust a conduction state of the at least one switch circuit in response to the bias control signal to adjust the bias voltage.
In an exemplary embodiment of the invention, the signal generating circuit further includes a filter circuit. The filter circuit is connected to the bias circuit and is used for filtering the first bias voltage to generate the bias voltage.
In an exemplary embodiment of the present invention, the signal generating circuit includes a driving circuit and a phase interpolator. The phase interpolator is connected to the driving circuit. The driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and the phase interpolator is used for generating the clock signal according to the current.
In an exemplary embodiment of the invention, the bias voltage is used to adjust the voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage is used to adjust the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
An exemplary embodiment of the present invention further provides a signal generating method for a memory storage device. The signal generation method comprises the following steps: generating a phase control signal according to the phase adjustment signal; generating a bias voltage according to the phase control signal; and generating a clock signal according to the phase control signal and the bias voltage. The bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
In an exemplary embodiment of the present invention, the generating the bias voltage according to the phase control signal includes: generating a bias control signal according to the phase control signal; and generating a first bias voltage according to the bias control signal.
In an exemplary embodiment of the present invention, the generating the first bias voltage according to the bias control signal includes: adjusting a conduction state of at least one switching circuit in response to the bias control signal to adjust the bias voltage.
In an exemplary embodiment of the invention, the step of generating the bias voltage according to the phase control signal further includes: the first bias voltage is filtered to generate the bias voltage.
In an exemplary embodiment of the present invention, the step of generating the clock signal according to the phase control signal and the bias voltage comprises: providing the current to a phase interpolator according to the phase control signal and the bias voltage; and generating the clock signal by the phase interpolator according to the current.
In an exemplary embodiment of the invention, the bias voltage affects a current value of the current.
In an exemplary embodiment of the invention, the signal generating method further includes: adjusting the voltage of the clock signal according to the bias voltage and a first amplification ratio in response to a first target phase; and adjusting the voltage of the clock signal according to the bias voltage and a second amplification ratio in response to a second target phase. The first target phase is different from the second target phase, and the first amplification scale is different from the second amplification scale.
Based on the above, the phase control circuit may generate the phase control signal according to the phase adjustment signal, and the bias control circuit may generate the bias voltage according to the phase control signal. The bias voltage can be used to adjust the current of the phase interpolation circuit, thereby effectively correcting the clock signal generated by the phase interpolation circuit.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a signal generating circuit according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating phase interpolation according to an exemplary embodiment of the present invention;
FIGS. 3A and 3B are schematic diagrams illustrating correction of non-linear distortion of a clock signal according to various exemplary embodiments of the invention;
FIG. 4 is a schematic diagram of a signal generation circuit according to an exemplary embodiment of the present invention;
FIG. 5 is a diagram illustrating a calibrated clock signal according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of a bias control circuit according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram of a phase interpolation circuit according to an exemplary embodiment of the present invention;
FIG. 8 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the present invention;
FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
fig. 10 is a flowchart illustrating a signal generating method according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 40: signal generating circuit
11. 41: phase control circuit
12. 42: bias control circuit
13. 43: phase interpolation circuit
301. 302, 303: dotted line
401: encoding circuit
402: bias circuit
403: filter circuit
501: boundary of
601(1) to 601 (n): switching circuit
I (REF): current source
SW (1) to SW (n): switch with a switch body
R: resistance (RC)
C: capacitor with a capacitor element
N1(1) to N1(N), N2(1) to N2(m), N3(1) to N3(m), N4(1) to N4 (m): transistor with a metal gate electrode
80: clock data recovery circuit
81: phase detection circuit
82: phase adjustment circuit
83: signal generating circuit
90: memory storage device
91: connection interface unit
92: memory control circuit unit
93: rewritable nonvolatile memory module
PAS、PCS(1)、PCS(2)、CLK、Y、XI、XQY (1), Y (2), Y (i), VCS: signal
V (bias), v (bias)': bias voltage
a1、a2、a1(0)、a1(1)、a1(2)、a2(0)、a2(1)、a2(2): parameter(s)
Figure BDA0002277099560000051
: phase position
S1001: step (generating phase control signal according to phase adjustment signal)
S1002: step (generating a bias voltage according to the phase control signal)
S1003: step (generating a clock signal according to the phase control signal and the bias voltage)
Detailed Description
The present invention will be described in more detail with reference to exemplary embodiments, but the present invention is not limited to the exemplary embodiments. Also, suitable combinations between the exemplary embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
Fig. 1 is a schematic diagram of a signal generating circuit according to an exemplary embodiment of the present invention. Referring to fig. 1, a signal generating circuit 10 generates a signal (also referred to as a clock signal) CLK according to a signal (also referred to as a phase adjustment signal) PAS. For example, the signal PAS may carry information about the phase of the signal CLK and/or information that may be used to adjust the phase of the signal CLK. According to the signal PAS, the signal generating circuit 10 may generate the signal CLK having a specific phase and/or a specific frequency by means of phase interpolation.
The signal generation circuit 10 includes a phase control circuit 11, a bias control circuit 12, and a phase interpolation circuit 13. The phase control circuit 11 is connected to the bias control circuit 12 and the phase interpolation circuit 13. The phase control circuit 11 receives the signal PAS and generates signals PCS (1) and PCS (2) according to the signal PAS. Signals PCS (1) and PCS (2) may also be collectively referred to as phase control signals. The bias control circuit 12 receives the signal PCS (1) and generates a bias voltage v (bias) according to the signal PCS (1). The voltage value of the bias voltage V (bias) is controlled by the signal PCS (1). The bias voltage V (bias) can be used to drive the phase interpolation circuit 13. The phase interpolation circuit 13 receives the signal PCS (2) and the bias voltage v (bias) and performs phase interpolation according to the signal PCS (2) and the bias voltage v (bias) to generate the signal CLK.
It should be noted that the phase of the generated signal CLK is mainly specified by the signals PCS (1) and PCS (2), and the bias voltage V (bias) can adjust the current of the phase interpolation circuit 13 according to the specified phase, thereby correcting the error of the signal CLK. This error may be referred to as a phase error and/or an amplitude error, for example. In other words, the bias control circuit 12 can fine-tune the bias voltage V (bias) according to the signal PCS (1). The phase interpolation circuit 13 can generate a more accurate signal CLK according to the driving of the adjusted bias voltage v (bias).
Fig. 2 is a schematic diagram illustrating phase interpolation according to an exemplary embodiment of the present invention. Referring to FIG. 2, it is assumed that the phase interpolation is by signal XIAnd XQWaveform synthesis as a substrate to generate a signal having a phase
Figure BDA0002277099560000061
Signal Y of (2), signal XI、XQAnd Y may be represented by the following equations (1.1) to (1.3), respectively.
XI＝Asin(wt) (1.1)
XQ＝Asin(wt-π/2)＝-Acos(wt) (1.2)
Figure BDA0002277099560000062
In equations (1.1) to (1.3), A represents the signal XI、XQAnd the amplitude of Y. In an ideal state, the parameter a1And a2Need to satisfy a1 2+a2 2 Condition 1 to produce a signal Y with a perfect waveform. It should be noted that, in practice, the value is often a1+a2Substituted by 11 2+a2 21, to reduce the complexity and cost of the circuit design, but also to cause nonlinear distortion of the phase interpolation. In the exemplary embodiment of fig. 1, the adjustment of the bias voltage v (bias) can be used to improve the nonlinear distortion, so that the signal CLK generated by the phase interpolation circuit 13 is closer to the expected perfect waveform.
Fig. 3A and 3B are schematic diagrams illustrating correction of non-linear distortion of a clock signal according to various exemplary embodiments of the invention. Referring to FIG. 3A, the dotted line 301 represents the condition a1(0)+a2(0) 1, and the dashed line 302 is used to represent the condition a1(1)+a2(1) 1+ e (1). Under the default operation of the phase interpolation circuit 13 shown in FIG. 1, the phase interpolation circuit 13 can generate the signal XIAnd XQWaveform synthesis as a substrate to generate a signal having a phase
Figure BDA0002277099560000071
Signal Y (1) of (1). For example, the signal Y (1) may be the signal CLK of FIG. 1.
It should be noted that if the signal Y (1) is not corrected or compensated by adjusting the bias voltage v (bias) of fig. 1, the generated signal Y (1) will correspond to the dashed line 301Condition (i.e. a)1(0)+a2(0) 1) and the signal Y (1) may have the above-mentioned problem of nonlinear distortion. However, in the exemplary embodiment of fig. 3A, if the signal Y (1) is corrected and compensated by adjusting the bias voltage v (bias) of fig. 1, the generated signal Y (1) may meet the condition corresponding to the dashed line 302 (i.e., a)1(1)+a2(1) 1+ e (1)). For example, the parameter e (1) may be 0.5 (i.e., a)1(1)+a2(1) 1.5). It should be noted that the parameter e (1) is automatically generated by adjusting the bias voltage v (bias) to compensate for the non-linear distortion of the signal Y (1). Therefore, the corrected signal Y (1) is more suitable for a in the ideal state than the uncorrected signal Y (1)1(1)2+a2(1)2 Condition 1.
Referring to FIG. 3B, the dotted line 301 is also used to indicate the condition a1(0)+a2(0) 1, and the dotted line 303 indicates the condition a1(2)+a2(2) 1+ e (2). Under the default operation of the phase interpolation circuit 13 shown in FIG. 1, the phase interpolation circuit 13 can generate the signal XIAnd XQWaveform synthesis as a substrate to generate a signal having a phase
Figure BDA0002277099560000072
Signal Y (2). For example, the signal Y (2) may be the signal CLK of FIG. 1.
It should be noted that if the signal Y (2) is not corrected or compensated by adjusting the bias voltage v (bias) of fig. 1, the generated signal Y (2) will meet the condition (i.e. a) corresponding to the dashed line 3011(0)+a2(0) 1) and the signal Y (2) suffers from the nonlinear distortion described above. However, in the exemplary embodiment of fig. 3B, if the signal Y (2) is corrected and compensated by adjusting the bias voltage v (bias) of fig. 1, the generated signal Y (2) can satisfy the condition (i.e., a) corresponding to the dashed line 3031(2)+a2(2) 1+ e (2)). For example, the parameter e (2) may be 0.3 (i.e., a)1(2)+a2(2) 1.3). It should be noted that the parameter e (2) is also automatically generated by adjusting the bias voltage v (bias) to compensate for the non-linear distortion of the signal Y (2). In the example embodiment of FIG. 3B, the signal is compared to the uncorrected signalY (2), the corrected signal Y (2) more conforms to a in an ideal state1(2)2+a2(2)2 Condition 1. In addition, the bias voltage v (bias) for compensating the signal Y (1) in the example embodiment of fig. 3A may be different from the bias voltage v (bias) for compensating the signal Y (2) in the example embodiment of fig. 3B.
Viewed from another perspective, in one exemplary embodiment of FIG. 3A, in response to a target phase (also referred to as a first target phase)
Figure BDA0002277099560000081
The generated bias voltage v (bias) can be used to adjust the voltage (or amplitude) of the signal Y (1) according to an amplification ratio (also referred to as a first amplification ratio), thereby correcting and compensating the signal Y (1). Further, in the exemplary embodiment of FIG. 3B, in response to another target phase (also referred to as a second target phase)
Figure BDA0002277099560000082
The generated bias voltage v (bias) can be used to adjust the voltage (or amplitude) of the signal Y (2) according to another amplification ratio (also referred to as a second amplification ratio), thereby correcting and compensating the signal Y (2). The first target phase is different from the second target phase. The first magnification ratio is different from the second magnification ratio.
Fig. 4 is a schematic diagram of a signal generating circuit according to an exemplary embodiment of the invention. Referring to fig. 4, the signal generating circuit 40 includes a phase control circuit 41, a bias control circuit 42, and a phase interpolating circuit 43. The phase control circuit 41 generates signals PCS (1) and PCS (2) according to the signal PAS. The bias control circuit 42 generates a bias voltage V (bias) according to the signal PCS (1). The voltage value of the bias voltage V (bias) is controlled by the signal PCS (1). The phase interpolation circuit 43 performs phase interpolation to generate the signal CLK according to the signal PCS (2) and the bias voltage v (bias).
In an exemplary embodiment, the bias control circuit 42 includes an encoding circuit 401, a bias circuit 402, and a filter circuit 403. The bias circuit 402 is connected to the encoding circuit 401 and the filter circuit 403. The encoding circuit 401 receives the signal PCS (1) and generates a signal (also referred to as a bias control signal) VCS according to the signal PCS (1). For example, the signal VCS may correspond to a digital code. The bias circuit 402 receives the signal VCS and generates a bias voltage (also referred to as a first bias voltage) v (bias) according to the signal VCS. The filter circuit 403 may receive the bias voltage v (bias) 'and filter (e.g., low-pass filter) the bias voltage v (bias)' to generate the bias voltage v (bias). It is noted that the filter circuit 403 may make the change of the bias voltage v (bias) more continuous and/or smooth. In another exemplary embodiment, the phase interpolation circuit 43 may be directly driven by the bias voltage v (bias) without providing the filter circuit 403 in the signal generating circuit 40. In an exemplary embodiment, the phase interpolation circuit 43 is directly driven by the bias voltage v (bias)' to achieve the calibration effect similar to that shown in fig. 3A and 3B.
FIG. 5 is a diagram illustrating a calibrated clock signal according to an exemplary embodiment of the invention. Referring to fig. 5, under the premise of providing the filter circuit 403 in fig. 4, when adjusting the phase of the generated signal y (i), since the change of the bias voltage v (bias) is continuous and/or smooth, the signal y (i) can be closer to the ideal state under the condition a1(i)2+a2(i)2A circular boundary 501 for 1. It should be noted that, in other exemplary embodiments, the signal y (i) may have other phases with different angles, and the invention is not limited thereto.
FIG. 6 is a schematic diagram of a bias control circuit according to an exemplary embodiment of the present invention. Referring to fig. 6, in an exemplary embodiment, the bias circuit 402 includes a current source i (ref) and a switch circuit (also referred to as a first switch circuit) 601(1) -601 (n). The switch circuit 601(i) includes a switch sw (i) and a transistor N1 (i). i may be 1 to n. Transistor N1(i) may be connected across switch sw (i). The switch circuits 601(1) to 601(n) are connected in series. Specific connection relationships of the switch circuits 601(1) to 601(n) can be as shown in fig. 6.
In an exemplary embodiment, the signal VCS can be used to control the ON state of each of the switches SW (1) -SW (n) to be ON or OFF. Therefore, the switch circuits 601(1) to 601(n) can adjust the on states of the switches SW (1) to SW (n) according to the signal VCS to adjust the bias voltage v (bias). For example, by increasing or decreasing the total number of conducting ones of the switches SW (1) -SW (n), the voltage value of the bias voltage V (bias)' can be changed accordingly. In addition, the filter circuit 403 may include an RC circuit composed of at least one resistor R and at least one capacitor C, as shown in fig. 6. The bias voltage v (bias) may be filtered by the filter circuit 403 to generate the bias voltage v (bias).
Fig. 7 is a schematic diagram of a phase interpolation circuit according to an exemplary embodiment of the present invention. Referring to fig. 7, in an exemplary embodiment, the phase interpolation circuit 43 includes a driving circuit 71 and a phase interpolator 72. The drive circuit 71 is connected to the phase interpolator 72. The driving circuit 71 is used for receiving the signal PCS (2) and the bias voltage V (bias) and providing a current I (X) according to the signal PCS (2) and the bias voltage V (bias)I) And I (X)Q) To the phase interpolator 72.
In an exemplary embodiment, the driving circuit 71 includes transistors N2(0) -N2 (m), N3(0) -N3 (m), and N4(0) -N4 (m). The signal PCS (2) may comprise a plurality of sub-signals S (0) to S (m) and Sb (0) to Sb (m). The sub-signals S (0) -S (m) may be provided to gate terminals of the transistors N3(0) -N3 (m), respectively, to adjust the on-state of each of the transistors N3(0) -N3 (m). The sub-signals Sb (0) -Sb (m) may be provided to gate terminals of the transistors N4(0) -N4 (m), respectively, to adjust the on-state of each of the transistors N4(0) -N4 (m). In addition, a bias voltage v (bias) may be provided to the gate terminals of the transistors N2(0) -N2 (m) to adjust the on-state of each of the transistors N2(0) -N2 (m). The specific connection relationships of the transistors N2(0) to N2(m), N3(0) to N3(m), and N4(0) to N4(m) can be as shown in fig. 7, and the present invention is not limited thereto. Thus, the driving circuit 71 can adjust the current I (X) according to the sub-signals S (0) -S (m) and Sb (0) -Sb (m)I) And I (X)Q) In addition, the current I (X) can be further increased or decreased according to the variation of the bias voltage V (bias)I) And I (X)Q) The current value of (1).
The phase interpolator 72 is configured to receive the current I (X)I) And I (X)Q) And according to the current I (X)I) And I (X)Q) Generating a signal CLK. It should be noted that, in the operation of generating the signal CLK,current I (X)I) And I (X)Q) Can respectively influence the parameter a in the equation (1.3)1And a2. For example, parameter a1Can positively correlate with the current I (X)I) Current value of (d), and parameter a2Can positively correlate with the current I (X)Q) The current value of (1). Alternatively, taking fig. 5 as an example, the current I (X) is adjusted (e.g., increased) by the bias voltage v (bias)I) And I (X)Q) Parameter a1(i) And a2(i) May be automatically adjusted (e.g., enlarged). Thus, the signal Y (i) generated by the phase interpolator 72 can be more close to the ideal condition, the condition a1(i)2+a2(i)2A circular boundary 501 for 1.
Fig. 8 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the invention. Referring to fig. 8, in an exemplary embodiment, the clock data recovery circuit 80 includes a phase detection circuit 81, a phase adjustment circuit 82, and a signal generation circuit 83. The signal generating circuit 83 may include the signal generating circuit 10 of fig. 1 or the signal generating circuit 40 of fig. 4.
The phase detection circuit 81 is configured to receive a signal (also referred to as a first signal or a DATA signal) DATA and a signal (also referred to as a clock signal or a recovery clock signal) CLK. The phase detection circuit 81 can detect a phase relationship (e.g., a phase difference) between the signal DATA and the signal CLK and generate a signal (also referred to as a phase signal) PS. For example, the signal PS may be reflected at a point in time where the phase of the signal DATA is leading or lagging the phase of the signal CLK. For example, the signal PS may include a first signal and a second signal. The first signal may reflect that the phase of the signal DATA leads the phase of the signal CLK. The second signal may reflect that the phase of the signal DATA lags the phase of the signal CLK.
The phase adjustment circuit 82 is connected to the phase detection circuit 81 and the signal generation circuit 83. The phase adjustment circuit 82 generates a signal (also referred to as a phase control signal) PAS according to the signal PS. For example, the phase adjustment circuit 82 may generate the signal PAS according to the number of occurrences and/or the frequency of the first signal and/or the second signal in the signal PS. For example, the signal PAS may be used to instruct the signal generating circuit 83 to generate the signal CLK having a certain phase.
In an exemplary embodiment, the clock DATA recovery circuit 80 can gradually synchronize the phase of the signal CLK and the phase of the signal DATA through the cooperation of the phase detection circuit 81, the phase adjustment circuit 82 and the signal generation circuit 83. When the phase of the signal DATA changes, the clock DATA recovery circuit 80 may again synchronize the phase of the signal CLK with the phase of the signal DATA. In an exemplary embodiment, the operation of synchronizing the phase of the signal CLK and the phase of the signal DATA is also referred to as phase locking. In an example embodiment, the signal generating circuit 83 of fig. 8, the signal generating circuit 10 of fig. 1, and/or the signal generating circuit 40 of fig. 4 may also be referred to as a phase interpolator module or a phase interpolation circuit module.
In an example embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4, and/or the clock data recovery circuit 80 of fig. 8 may be disposed in a memory storage device. In another exemplary embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4, and/or the clock data recovery circuit 80 of fig. 8 may be disposed in other types of electronic devices, and is not limited to memory storage devices.
FIG. 9 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 9, the memory storage device 90 is a memory storage device including a rewritable nonvolatile memory module 93, such as a Solid State Drive (SSD). The memory storage device 90 may be used with a host system that may write data to the memory storage device 90 or read data from the memory storage device 90. For example, the host system may be any system that can substantially cooperate with the memory storage device 90 to store data, such as a desktop computer, a notebook computer, a digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like.
The memory storage device 90 includes a connection interface unit 91, a memory control circuit unit 92, and a rewritable nonvolatile memory module 93. The connection interface unit 91 is used to connect the memory storage device 90 to a host system. In an exemplary embodiment, the connection interface unit 91 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 91 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard or other suitable standards. The connection interface unit 91 and the memory control circuit unit 92 may be packaged in one chip, or the connection interface unit 1001 may be disposed outside a chip including the memory control circuit unit 92.
The memory control circuit unit 92 is used for performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 93 according to instructions of the host system. In an example embodiment, the memory control circuit unit 92 is also referred to as a memory controller or a flash memory controller.
The rewritable nonvolatile memory module 93 is connected to the memory control circuit unit 92 and is used for storing data written by the host system. The rewritable nonvolatile memory module 93 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
In an exemplary embodiment, the signal generating circuit 10 of fig. 1, the signal generating circuit 40 of fig. 4, and/or the clock data recovery circuit 80 of fig. 8 may be disposed in the connection interface unit 91, the memory control circuit unit 92, and/or the rewritable nonvolatile memory module 93.
It should be noted that the electronic circuit structures shown in fig. 1, fig. 4, and fig. 6 to fig. 8 are only schematic diagrams of the signal generating circuit and the clock data recovery circuit in some exemplary embodiments, and are not intended to limit the present invention. In some applications not mentioned, more electronic components may be added to or replace portions of the signal generating circuit and/or the clock data recovery circuit to provide additional, the same or similar functionality. In addition, in some applications not mentioned, the circuit layout and/or the connection relationship of the elements inside the signal generating circuit and/or the clock data recovery circuit can be changed appropriately to meet the practical requirements.
Fig. 10 is a flowchart illustrating a signal generating method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a phase control signal is generated according to a phase adjustment signal. In step S1002, a bias voltage is generated according to the phase control signal. In step S1003, a clock signal is generated according to the phase control signal and the bias voltage. It should be noted that the bias voltage is used to adjust the current of the phase interpolation circuit to correct the error of the clock signal.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, after generating the bias voltage according to the phase control signal, the bias voltage can be used to adjust the current of the phase interpolation circuit, so as to effectively correct the clock signal generated by the phase interpolation circuit. For example, in an exemplary embodiment, the adjusted bias voltage can be used to increase the current of the phase interpolation circuit, so that the waveform of the clock signal generated by the phase interpolation is closer to a perfect waveform.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A signal generating circuit comprising:
the phase control circuit is used for generating a phase control signal according to the phase adjusting signal;
a bias control circuit connected to the phase control circuit and configured to generate a bias voltage according to the phase control signal; and
a phase interpolation circuit connected to the phase control circuit and the bias control circuit and used for generating a clock signal according to the phase control signal and the bias voltage,
the bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
2. The signal generating circuit of claim 1, wherein the bias control circuit comprises:
the encoding circuit is connected to the phase control circuit and is used for generating a bias control signal according to the phase control signal; and
the bias circuit is connected to the encoding circuit and used for generating a first bias voltage according to the bias control signal.
3. The signal generating circuit of claim 2, wherein the biasing circuit comprises:
a current source; and
at least one switch circuit connected in series to the current source and used for adjusting the conducting state of the at least one switch circuit in response to the bias control signal so as to adjust the bias voltage.
4. The signal generating circuit of claim 2, wherein the bias control circuit further comprises:
and the filter circuit is connected to the bias circuit and the phase interpolation circuit and is used for filtering the first bias voltage to generate the bias voltage.
5. The signal generation circuit of claim 1, wherein the phase interpolation circuit comprises:
a drive circuit; and
a phase interpolator connected to the driving circuit,
wherein the driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and
the phase interpolator is used for generating the clock signal according to the current.
6. The signal generating circuit of claim 5, wherein the bias voltage affects a current value of the current.
7. The signal generating circuit of claim 1, wherein the bias voltage is configured to adjust a voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage is configured to adjust the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
8. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module;
the memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module; and
a clock data recovery circuit disposed in the connection interface unit, the rewritable nonvolatile memory module or the memory control circuit unit,
wherein the clock data recovery circuit comprises a signal generating circuit,
the signal generating circuit is used for generating a phase control signal according to the phase adjusting signal,
the signal generating circuit is further configured to generate a bias voltage according to the phase control signal,
the signal generating circuit is further used for generating a clock signal according to the phase control signal and the bias voltage, and
the bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
9. The memory storage device of claim 8, wherein the signal generation circuit comprises:
the encoding circuit is used for generating a bias control signal according to the phase control signal; and
the bias circuit is connected to the encoding circuit and used for generating a first bias voltage according to the bias control signal.
10. The memory storage device of claim 9, wherein the bias circuit comprises:
a current source; and
at least one switch circuit connected in series to the current source and used for adjusting the conducting state of the at least one switch circuit in response to the bias control signal so as to adjust the bias voltage.
11. The memory storage device of claim 9, wherein the signal generation circuit further comprises:
a filter circuit connected to the bias circuit and configured to filter the first bias voltage to generate the bias voltage.
12. The memory storage device of claim 8, wherein the signal generation circuit comprises:
a drive circuit; and
a phase interpolator connected to the driving circuit,
wherein the driving circuit is used for receiving the phase control signal and the bias voltage and providing the current to the phase interpolator according to the phase control signal and the bias voltage, and
the phase interpolator is used for generating the clock signal according to the current.
13. The memory storage device of claim 12, wherein the bias voltage affects a current value of the current.
14. The memory storage device of claim 8, wherein the bias voltage is to adjust a voltage of the clock signal according to a first amplification ratio in response to a first target phase, the bias voltage is to adjust the voltage of the clock signal according to a second amplification ratio in response to a second target phase, the first target phase is different from the second target phase, and the first amplification ratio is different from the second amplification ratio.
15. A signal generation method for a memory storage device, and comprising:
generating a phase control signal according to the phase adjustment signal;
generating a bias voltage according to the phase control signal; and
generating a clock signal according to the phase control signal and the bias voltage,
the bias voltage is used for adjusting the current of the phase interpolation circuit so as to correct the error of the clock signal.
16. The signal generating method of claim 15, wherein the step of generating the bias voltage according to the phase control signal comprises:
generating a bias control signal according to the phase control signal; and
a first bias voltage is generated according to the bias control signal.
17. The signal generating method of claim 16, wherein generating the first bias voltage according to the bias control signal comprises:
adjusting a conduction state of at least one switching circuit in response to the bias control signal to adjust the bias voltage.
18. The signal generating method of claim 16, wherein the step of generating the bias voltage according to the phase control signal further comprises:
the first bias voltage is filtered to generate the bias voltage.
19. The method according to claim 15, wherein the step of generating the clock signal according to the phase control signal and the bias voltage comprises:
providing the current to a phase interpolator according to the phase control signal and the bias voltage; and
and generating the clock signal by the phase interpolator according to the current.
20. The signal generating method according to claim 19, wherein the bias voltage affects a current value of the current.
21. The signal generating method of claim 15, further comprising:
adjusting the voltage of the clock signal according to the bias voltage and a first amplification ratio in response to a first target phase; and
adjusting the voltage of the clock signal according to the bias voltage and a second amplification ratio in response to a second target phase, wherein the first target phase is different from the second target phase and the first amplification ratio is different from the second amplification ratio.
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US20020006171A1 (en) * 2000-07-06 2002-01-17 Nielsen Gert Lynge Low phase noise frequency converter
KR20020034253A (en) * 2000-10-31 2002-05-09 구자홍 Apparatus for compensating white balance of display device
CN101132173A (en) * 2006-08-22 2008-02-27 阿尔特拉公司 Techniques for providing calibrated on-chip termination impedance
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