CN117424594A - Spread spectrum clock generator, memory storage device and spread spectrum clock generating method - Google Patents

Spread spectrum clock generator, memory storage device and spread spectrum clock generating method Download PDF

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Publication number
CN117424594A
CN117424594A CN202311351494.3A CN202311351494A CN117424594A CN 117424594 A CN117424594 A CN 117424594A CN 202311351494 A CN202311351494 A CN 202311351494A CN 117424594 A CN117424594 A CN 117424594A
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CN
China
Prior art keywords
frequency
spread spectrum
spectrum clock
circuit
clock signal
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CN202311351494.3A
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Chinese (zh)
Inventor
李昆叡
吴仁钜
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Phison Electronics Corp
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Phison Electronics Corp
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Priority to CN202311351494.3A priority Critical patent/CN117424594A/en
Publication of CN117424594A publication Critical patent/CN117424594A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Abstract

The invention provides a spread spectrum clock generator, a memory storage device and a spread spectrum clock generating method. The method comprises the following steps: generating a spread spectrum clock signal according to the reference clock signal and the control signal; and adjusting the control signal to cause the frequency of the spread spectrum clock signal to vary based on a plurality of frequency variation rates, wherein an initial frequency variation rate of the spread spectrum clock signal is greater than a frequency variation rate of the spread spectrum clock signal within a target time range. Therefore, electromagnetic interference caused by spread spectrum clock signals can be further reduced, and the reliability of the system is improved.

Description

Spread spectrum clock generator, memory storage device and spread spectrum clock generating method
Technical Field
The present invention relates to spread spectrum clock generation, and more particularly, to a spread spectrum clock generator, a memory storage device, and a spread spectrum clock generation method.
Background
Electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.
Spread Spectrum (SS) clock signals have low electromagnetic interference (Electromagnetic Interference, EMI) characteristics. Therefore, the spread spectrum clock signal can be applied to electronic devices such as memory storage devices. However, although the spread spectrum clock signal can reduce electromagnetic interference compared to a clock signal of a fixed frequency, electromagnetic interference caused by the spread spectrum clock signal may rise within a specific time range, thereby reducing system reliability.
Disclosure of Invention
The invention provides a spread spectrum clock generator, a memory storage device and a spread spectrum clock generating method, which can further reduce electromagnetic interference caused by a spread spectrum clock signal, thereby improving the reliability of a system.
Exemplary embodiments of the present invention provide a spread spectrum clock generator, which includes a clock generating circuit and a frequency control circuit. The clock generation circuit is used for generating a spread spectrum clock signal according to the reference clock signal and the control signal. The frequency control circuit is connected to the clock generation circuit. The frequency control circuit is used for adjusting the control signal so that the frequency of the spread spectrum clock signal changes based on a plurality of frequency change rates, wherein the initial frequency change rate of the spread spectrum clock signal is larger than the frequency change rate of the spread spectrum clock signal in a target time range.
In an example embodiment of the present invention, the operation of the frequency control circuit to adjust the control signal includes: detecting whether the spread spectrum clock signal enters the target time range; and adjusting the control signal to reduce the rate of change of the frequency of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
In an example embodiment of the present invention, a rate of change of frequency of the spread spectrum clock signal outside the target time range is greater than the rate of change of frequency of the spread spectrum clock signal within the target time range.
In an exemplary embodiment of the present invention, at the turning point within the target time range, the frequency value of the spread spectrum clock signal is changed from falling with time to rising with time or from rising with time to falling with time.
In an exemplary embodiment of the present invention, the target time range includes a first sub-target time range and a second sub-target time range, the first sub-target time range is closer to the turning point than the second sub-target time range, and a frequency change rate of the spread spectrum clock signal in the first sub-target time range is smaller than a frequency change rate of the spread spectrum clock signal in the second sub-target time range.
In an exemplary embodiment of the present invention, the frequency change rate of the spread spectrum clock signal in the target time range is 10% to 80% of the initial frequency change rate.
In an exemplary embodiment of the present invention, the clock generating circuit includes a phase frequency detecting circuit, a charge pump circuit, and a voltage controlled oscillating circuit. The phase frequency detection circuit is connected to the frequency control circuit. The charge pump circuit is connected to the phase frequency detection circuit. The voltage-controlled oscillation circuit is connected to the charge pump circuit and the frequency control circuit. The phase frequency detection circuit is used for detecting a phase difference or a frequency difference between the reference clock signal and the control signal. The charge pump circuit is used for controlling the voltage-controlled oscillation circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
In an exemplary embodiment of the invention, the frequency control circuit includes a frequency divider circuit and a controller. The frequency dividing circuit is connected to the clock generating circuit. The controller is connected to the frequency dividing circuit. The controller is used for controlling the output of the frequency-dividing circuit so as to adjust the control signal.
In an exemplary embodiment of the invention, the frequency control circuit includes a frequency divider circuit, a multiplexer circuit, a phase interpolation circuit, and a controller. The frequency dividing circuit is connected to the clock generating circuit. The multiplexer circuit is connected to the clock generation circuit and the frequency dividing circuit. The phase interpolation circuit is connected to the clock generation circuit and the multiplexer circuit. The controller is connected to the phase interpolation circuit. The controller is used for controlling the output of the phase interpolation circuit to adjust the control signal.
In an exemplary embodiment of the invention, the frequency control circuit includes a controller for controlling the frequency dividing circuit or the phase interpolation circuit to adjust the control signal. The controller includes a signal profile generator, a modulator, and an encoder. The signal profile generator is configured to provide a fundamental frequency control signal. The modulator is connected to the signal profile generator and is used for generating a modulation signal according to the basic frequency control signal. The encoder is connected to the modulator and is used for generating an encoded signal according to the modulation signal, wherein the encoded signal is used for being provided to the frequency dividing circuit or the phase interpolation circuit so as to adjust the control signal.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The spread spectrum clock signal generator is arranged in the connection interface unit. The spread spectrum clock signal generator is configured to: generating a spread spectrum clock signal according to the reference clock signal and the control signal; and adjusting the control signal to cause the frequency of the spread spectrum clock signal to vary based on a plurality of frequency variation rates, wherein an initial frequency variation rate of the spread spectrum clock signal is greater than a frequency variation rate of the spread spectrum clock signal within a target time range.
In an example embodiment of the present invention, the operation of adjusting the control signal includes: detecting whether the spread spectrum clock signal enters the target time range; and adjusting the control signal to reduce the rate of change of the frequency of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
In an exemplary embodiment of the present invention, the spread spectrum clock signal generator includes a phase frequency detection circuit, a charge pump circuit, and a voltage controlled oscillation circuit. The charge pump circuit is connected to the phase frequency detection circuit. The voltage-controlled oscillation circuit is connected to the charge pump circuit. The phase frequency detection circuit is used for detecting a phase difference or a frequency difference between the reference clock signal and the control signal. The charge pump circuit is used for controlling the voltage-controlled oscillation circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
In an exemplary embodiment of the invention, the spread spectrum clock signal generator includes a frequency divider circuit and a controller. The controller is connected to the frequency dividing circuit. The controller is used for controlling the output of the frequency-dividing circuit so as to adjust the control signal.
In an exemplary embodiment of the invention, the spread spectrum clock signal generator includes a frequency divider circuit, a multiplexer circuit, a phase interpolation circuit, and a controller. The multiplexer circuit is connected to the frequency divider circuit. The phase interpolation circuit is connected to the multiplexer circuit. The controller is connected to the phase interpolation circuit. The controller is used for controlling the output of the phase interpolation circuit to adjust the control signal.
In an exemplary embodiment of the invention, the spread spectrum clock signal generator includes a controller for controlling a frequency divider circuit or a phase interpolation circuit to adjust the control signal. The controller includes a signal profile generator, a modulator, and an encoder. The signal profile generator is configured to provide a fundamental frequency control signal. The modulator is connected to the signal profile generator and is used for generating a modulation signal according to the basic frequency control signal. The encoder is connected to the modulator and is used for generating an encoded signal according to the modulation signal, wherein the encoded signal is used for being provided to the frequency dividing circuit or the phase interpolation circuit so as to adjust the control signal.
The exemplary embodiments of the present invention further provide a spread spectrum clock generating method for a memory storage device. The spread spectrum clock generation method comprises the following steps: generating a spread spectrum clock signal according to the reference clock signal and the control signal; and adjusting the control signal to cause the frequency of the spread spectrum clock signal to vary based on a plurality of frequency variation rates, wherein an initial frequency variation rate of the spread spectrum clock signal is greater than a frequency variation rate of the spread spectrum clock signal within a target time range.
In an exemplary embodiment of the present invention, the step of adjusting the control signal includes: detecting whether the spread spectrum clock signal enters the target time range; and adjusting the control signal to reduce the rate of change of the frequency of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
In an exemplary embodiment of the present invention, the step of generating the spread spectrum clock signal according to the reference clock signal and the control signal includes: detecting a phase difference or a frequency difference between the reference clock signal and the control signal; and controlling the voltage-controlled oscillating circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
In an exemplary embodiment of the present invention, the step of adjusting the control signal includes: and controlling the output of the frequency dividing circuit to adjust the control signal.
In an exemplary embodiment of the present invention, the step of adjusting the control signal includes: the output of the phase interpolation circuit is controlled to adjust the control signal.
In an exemplary embodiment of the present invention, the step of adjusting the control signal includes: providing a fundamental frequency control signal; generating a modulation signal according to the basic frequency control signal; and generating an encoded signal according to the modulation signal, wherein the encoded signal is provided to a frequency divider circuit or a phase interpolation circuit to adjust the control signal.
Based on the above, after generating the spread spectrum clock signal according to the reference clock signal and the control signal, the control signal may be adjusted in a specific time range so that the frequency of the spread spectrum clock signal is changed based on various frequency change rates. In particular, the initial rate of change of the frequency of the spread spectrum clock signal is greater than the rate of change of the frequency of the spread spectrum clock signal over a target time range. Therefore, electromagnetic interference caused by spread spectrum clock signals can be further reduced, and the reliability of the system is improved.
Drawings
Fig. 1 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention;
FIG. 2 is a schematic diagram showing the change of the frequency of a conventional spread spectrum clock signal with time;
FIG. 3 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame, according to an example embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame, according to an example embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame, according to an example embodiment of the present invention;
Fig. 6 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention;
fig. 7 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention;
FIG. 8 is a schematic diagram of a controller shown according to an example embodiment of the invention;
FIG. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
fig. 10 is a flowchart illustrating a spread spectrum clock generating method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The following sets forth several embodiments to illustrate the invention, however the invention is not limited to the several embodiments illustrated. Also, suitable combinations are allowed between the embodiments. The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect means of coupling. For example, if a first device is described herein as being connected to a second device, it should be interpreted that the first device may be directly connected to the second device, or that the first device may be indirectly connected to the second device through other devices or some connection means. Further, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
Fig. 1 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention. Referring to fig. 1, the spread spectrum clock generator 10 may be disposed in a memory storage device or other type of electronic device. The spread spectrum clock generator 10 may include a clock generating circuit 11 and a frequency control circuit 12. The clock generation circuit 11 is connected to the frequency control circuit 12.
The clock generation circuit 11 may be configured to receive a signal (also referred to as a reference clock signal) RCLK and a signal (also referred to as a control signal) CTRL. The clock generation circuit 11 may generate a signal (also referred to as a spread clock signal) SCLK according to the signals RCLK and CTRL. For example, the frequency of the signal SCLK may continuously vary with increasing time. It should be noted that the signal CTRL can be used to adjust the frequency of the signal SCLK based on the frequency of the signal RCLK. The frequency control circuit 12 is configured to receive a signal FB (also referred to as a feedback signal) and generate a signal CTRL according to the signal FB. For example, the frequency of the signal SCLK may be the same as the frequency of the signal FB.
In an exemplary embodiment, the frequency control circuit 12 may continuously adjust the signal CTRL during the period when the clock generating circuit 11 generates the signal SCLK, so that the frequency of the signal SCLK varies based on various frequency variation rates. In particular, the initial rate of change of frequency of the signal SCLK may be greater than the rate of change of frequency of the signal SCLK within a specific time range (also referred to as a target time range). For example, the initial frequency change rate refers to a frequency change rate preset by the signal SCLK. For example, without actively changing the rate of change of the frequency of the signal SCLK, the spread clock generator 10 may adjust the frequency of the signal SCLK and continuously output the signal SCLK based on this initial rate of change of the frequency.
In an exemplary embodiment, the frequency control circuit 12 may continuously detect whether the signal SCLK enters the target time range during the period when the clock generating circuit 11 generates the signal SCLK. In response to the signal SCLK coming into the target time range, the frequency control circuit 12 may adjust the signal CTRL to reduce the frequency change rate of the signal SCLK. Thus, the rate of change of the frequency of the signal SCLK may be smaller than the initial rate of change of the frequency of the signal SCLK within the target time range. Alternatively, in another example embodiment, the rate of frequency change of the signal SCLK outside the target time range (i.e., the initial rate of frequency change) may be greater than the rate of frequency change of the signal SCLK within the target time range.
In an exemplary embodiment, the higher the frequency change rate of the signal SCLK, the larger the change amplitude of the frequency of the signal SCLK with time. Conversely, the lower the rate of change of the frequency of the signal SCLK, the smaller the amplitude of the change of the frequency of the signal SCLK with time. Thus, in an exemplary embodiment, the rate of change of the frequency of the signal SCLK outside the target time range (i.e., the initial rate of change of the frequency) is greater than the rate of change of the frequency of the signal SCLK within the target time range, which means that the frequency of the signal SCLK changes with time with a relatively small amplitude, and the frequency of the signal SCLK changes with time with a relatively large amplitude outside the target time range. For example, outside the target time range, the frequency of the signal SCLK may vary based on the initial rate of change of the frequency of the signal SCLK.
Fig. 2 is a schematic diagram showing a change in frequency of a conventional spread spectrum clock signal with an increase in time. Referring to fig. 1 and 2, a waveform 21 may be used to represent a conventional frequency change of a spread spectrum clock signal with time. For example, as time increases, the frequency of the spread spectrum clock signal may vary between frequencies f (a) and f (b). For example, at time point T (i), the frequency of the spread spectrum clock signal may be frequency f (i). At time T (j), the frequency of the spread spectrum clock signal may be frequency f (j). The time point T (i) is different from the time point T (j), and the frequency f (i) is different from the frequency f (j).
It should be noted that, conventionally, although the spread spectrum clock signal can reduce electromagnetic interference (Electromagnetic Interference, EMI) compared to the clock signal with a fixed frequency, electromagnetic interference caused by the spread spectrum clock signal still increases in a specific time range (e.g., time ranges 201-203 in fig. 2), thereby reducing system reliability. However, in an exemplary embodiment, by dynamically adjusting (e.g., reducing) the rate of frequency change of the signal SCLK within the target time range, electromagnetic interference caused by the signal SCLK may be effectively reduced.
Fig. 3 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame according to an example embodiment of the invention. Referring to fig. 1 and 3, the waveform 31 may be used to indicate that the frequency of the signal SCLK varies with time. For example, as time increases, the frequency of the signal SCLK may vary between frequencies f (a) 'and f (b)'. The frequency f (a) 'is smaller than the frequency f (a), and the frequency f (b)' is larger than the frequency f (b). That is, in an example embodiment, the waveform 31 represents a smaller (or narrower) range of variation of the frequency of the signal SCLK than the waveform 21 of fig. 2. In addition, the slope of the waveform 31 may be used to represent the rate of change of the frequency of the signal SCLK. For example, when the slope of the waveform 31 is larger, the frequency change rate of the signal SCLK is represented to be larger. Conversely, when the slope of the waveform 31 is smaller, the frequency change rate of the signal SCLK is smaller.
In an example embodiment, the target time range includes time ranges ΔT (1) and/or ΔT (2). In the target time range, the frequency change rate of the signal SCLK may be reduced, for example, to be lower than the initial frequency change rate of the signal SCLK. In addition, the rate of change of the frequency of the signal SCLK may be increased, e.g. reverted to the initial rate of change of the frequency of the signal SCLK, before entering the target time range or after leaving the target time range. Taking fig. 3 as an example, the slope of waveform 31 within the target time range (i.e., time range Δt (1) and/or Δt (2)) is less than the slope of waveform 31 outside the target time range (i.e., time range Δt (1) and/or Δt (2)). That is, the rate of change of frequency of the signal SCLK outside the target time range is greater than the rate of change of frequency of the signal SCLK within the target time range.
In an exemplary embodiment, the starting point of the time range Δt (1) is a time point T (0), the center point of the time range Δt (1) is T (1), and the end point of the time range Δt (1) is T (2). In an exemplary embodiment, at a turning point (e.g., time point T (1)) within the time range Δt (1), the frequency value of the signal SCLK changes from decreasing with increasing time to rising with increasing time. For example, between time points T (1) and T (2), the frequency value of the signal SCLK decreases with increasing time. However, after the time point T (2) has elapsed, the frequency value of the signal SCLK changes to rise as time increases.
In an exemplary embodiment, the starting point of the time range Δt (2) is the time point T (3), the center point of the time range Δt (2) is T (4), and the end point of the time range Δt (2) is T (5). In an exemplary embodiment, at a turning point (e.g., time point T (4)) within the time range Δt (2), the frequency value of the signal SCLK changes from rising with time to falling with time. For example, between time points T (3) and T (4), the frequency value of the signal SCLK rises with time. However, after the time point T (4) has elapsed, the frequency value of the signal SCLK changes to decrease as time increases.
In an exemplary embodiment, the closer to the turning point (e.g., time points T (1) and/or T (4)) the frequency change rate of the signal SCLK may be lower within the target time range (e.g., time ranges Δt (1) and/or Δt (2)). Conversely, the farther from the turning point (e.g., time points T (1) and/or T (4)) within the target time range (e.g., time ranges Δt (1) and/or Δt (2)), the higher the rate of change of the frequency of the signal SCLK may be.
In an example embodiment, one target time range may be divided into a plurality of sub-target time ranges. For example, such sub-target time ranges may include a first sub-target time range and a second sub-target time range. In particular, the first sub-target time range is closer to the turning point than the second sub-target time range, and the frequency change rate of the signal SCLK in the first sub-target time range may be smaller than the frequency change rate of the signal SCLK in the second sub-target time range.
Fig. 4 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame according to an example embodiment of the invention. Referring to fig. 3 and 4, in an exemplary embodiment, the time range Δt (1) may be divided into sub-time ranges Δt (11) to Δt (14). The sub-time range Δt (11) is between the time points T (0) and T (0)'. The sub-time range Δt (12) is between the time points T (0)' and T (1). The sub-time range Δt (13) is between the time points T (1) and T (1)'. The sub-time range Δt (14) is between the time points T (1)' and T (2).
It should be noted that in the time range Δt (1), the sub-time ranges Δt (12) and Δt (13) (i.e., the first sub-target time range) are closer to the turning point (i.e., the time point T (1)) than the sub-time ranges Δt (11) and Δt (14) (i.e., the second sub-target time range). In addition, the slope of waveform 31 in sub-time ranges ΔT (12) and ΔT (13) is less than the slope of waveform 31 in sub-time ranges ΔT (11) and ΔT (14). That is, the frequency change rate of the signal SCLK in the sub-time ranges Δt (12) and Δt (13) is smaller than the frequency change rate of the signal SCLK in the sub-time ranges Δt (11) and Δt (14).
Fig. 5 is a schematic diagram illustrating dynamically adjusting the rate of change of the frequency of a spread spectrum clock signal over a target time frame according to an example embodiment of the invention. Referring to fig. 3 and 5, in an exemplary embodiment, the time range Δt (2) may be divided into sub-time ranges Δt (21) to Δt (24). The sub-time range Δt (21) is between the time points T (3) and T (3)'. The sub-time range Δt (22) is between the time points T (3)' and T (4). The sub-time range Δt (23) is between the time points T (4) and T (4)'. The sub-time range Δt (24) is between the time points T (4)' and T (5).
It should be noted that in the time range Δt (2), the sub-time ranges Δt (22) and Δt (23) (i.e., the first sub-target time range) are closer to the turning point (i.e., the time point T (2)) than the sub-time ranges Δt (21) and Δt (24) (i.e., the second sub-target time range). In addition, the slope of waveform 31 in sub-time ranges ΔT (22) and ΔT (23) is less than the slope of waveform 31 in sub-time ranges ΔT (21) and ΔT (24). That is, the frequency change rate of the signal SCLK in the sub-time ranges Δt (22) and Δt (23) is smaller than the frequency change rate of the signal SCLK in the sub-time ranges Δt (21) and Δt (24).
In an exemplary embodiment, the rate of change of the frequency of the signal SCLK in the target time range may be 10% -80% of the initial rate of change of the frequency of the signal SCLK. Alternatively, in an exemplary embodiment, the frequency change rate of the signal SCLK within the target time range may be adjusted according to the practical requirement, which is not limited by the present invention. In an exemplary embodiment, by dynamically adjusting (e.g., reducing) the rate of frequency change of the signal SCLK within the target time range, electromagnetic interference caused by the signal SCLK can be effectively reduced.
Fig. 6 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention. Referring to fig. 6, in an exemplary embodiment, the clock generating circuit 11 may include a phase frequency detecting circuit 601, a charge pump (charge pump) circuit 602, a Low-pass filter (Low-pass filter) circuit 603, and a voltage-controlled oscillating circuit 604.
The phase frequency detection circuit 601 is connected to the frequency control circuit 12. The phase frequency detection circuit 601 may receive the signal RCLK and the signal CTRL and detect a phase difference or a frequency difference between the signal RCLK and the signal CTRL.
The charge pump circuit 602 is connected to the phase frequency detection circuit 601, the low-pass filter circuit 603, and the voltage-controlled oscillation circuit 604. The charge pump circuit 602 may generate a voltage (also referred to as a control voltage) VC with the low-pass filter circuit 603 according to a phase difference or a frequency difference (i.e., an output of the phase frequency detection circuit 601) between the signal RCLK and the signal CTRL. The voltage VC can be used to control the voltage-controlled oscillating circuit 604 to generate the signal SCLK. For example, the frequency of the signal SCLK may vary according to the voltage VC variation. For example, the voltage controlled oscillation circuit 604 may include a voltage controlled oscillator.
In an exemplary embodiment, the frequency control circuit 12 includes a frequency dividing circuit 611 and a controller 612. The frequency dividing circuit 611 is connected to the phase frequency detecting circuit 601 and the voltage controlled oscillating circuit 604. The controller 612 is connected to the frequency dividing circuit 611 and is used for controlling the output of the frequency dividing circuit 611 to adjust the signal CTRL. In an exemplary embodiment, the controller 612 may provide a signal (also referred to as a divide control signal) DIV to the divide circuit 611. The frequency divider 611 receives the signals FB and DIV and performs frequency division according to the signals FB and DIV to generate the signal CTRL. For example, the frequency divider circuit 611 may include a frequency divider.
Fig. 7 is a schematic diagram of a spread spectrum clock generator according to an example embodiment of the invention. Referring to fig. 7, in an exemplary embodiment, the clock generating circuit 11 may include a phase frequency detecting circuit 601, a charge pump circuit 602, a low-pass filter circuit 603 and a voltage-controlled oscillating circuit 604. The operation of the phase frequency detection circuit 601, the charge pump circuit 602, the low-pass filter circuit 603 and the voltage-controlled oscillation circuit 604 can be described with reference to the exemplary embodiment of fig. 6, and the description thereof is not repeated here.
In an example embodiment, the frequency control circuit 12 includes a frequency divider circuit 711, a Multiplexer (multiplexor) circuit 712, a phase interpolation (phase interpolation) circuit 713, and a controller 714. The multiplexer circuit 712 is connected to the frequency dividing circuit 711, the voltage-controlled oscillating circuit 604, and the phase interpolating circuit 713. For example, the frequency dividing circuit 711 is connected to an output terminal of the multiplexer circuit 712. The voltage controlled oscillating circuit 604 is connected to a first input of the multiplexer circuit 712. The phase interpolation circuit 713 is connected to a second input of the multiplexer circuit 712. The phase interpolation circuit 713 is further connected to the voltage controlled oscillation circuit 604 and the controller 714.
In an example embodiment, the controller 714 may dynamically control the multiplexer circuit 712 to turn on the first input terminal or the second input terminal. The frequency divider 711 generates the signal CTRL according to the signal FB when the first input is turned on. The controller 714 may provide a signal (also referred to as an interpolation control signal) PI to the phase interpolation circuit 713 while the second input is turned on. The phase interpolation circuit 713 may perform phase interpolation according to the signals FB and PI. Then, the frequency dividing circuit 711 may generate a signal CTRL according to the output of the phase interpolation circuit 713. For example, the frequency divider circuit 711 may include a frequency divider, and the phase interpolation circuit 713 may include a phase interpolator.
Fig. 8 is a schematic diagram of a controller according to an example embodiment of the invention. Referring to fig. 8, in an example embodiment, the controller 612 of fig. 6 and/or the controller 714 of fig. 7 may include the controller 81. The controller 81 includes a signal profile generator 811, a modulator 812, and an encoder 813. Modulator 812 is connected to signal profile generator 811 and encoder 813.
The signal profile generator 811 is configured to provide a signal (also referred to as a fundamental frequency control signal) SP. The waveform of the signal SP may affect the frequency and/or the rate of change of the frequency of the signal SCLK. For example, the waveform of the signal SP may coincide with or correspond to the rate of change of the frequency of the signal SCLK (or waveform 31 of fig. 3). The modulator 812 may receive the signal SP and generate a signal (also referred to as a modulated signal) MS from the signal SP. For example, the modulator 812 may modulate the signal SP to generate the signal MS. For example, the modulator 812 may comprise a Delta-sigma modulator, and the invention is not limited to the type of modulator 812.
The encoder 813 may receive the signal MS and generate the signal DIV of fig. 6 or the signal PI of fig. 7 according to the signal MS. For example, encoder 813 may encode signal MS to generate signal DIV or PI. Thereafter, the signal DIV or PI may be provided to the frequency divider 611 of fig. 6 or the phase interpolator 713 of fig. 7, respectively, to adjust the signal CTRL output by the frequency control circuit 12.
It should be noted that the circuit structures shown in fig. 6, 7 and 8 are only examples and are not intended to limit the present invention. In an exemplary embodiment, the connection relationship between the electronic circuits in the circuit structures shown in fig. 6, 7 and 8 may be adjusted according to the actual requirements. In an exemplary embodiment, each of the electronic circuits in the circuit structures shown in fig. 6, 7 and 8 may be replaced by an electronic circuit having the same or similar functions. In addition, in an exemplary embodiment, the circuit structures shown in fig. 6, 7 and 8 may further include other types of electronic circuits to provide other additional functions, which are not limited by the present invention.
In an exemplary embodiment, the spread spectrum clock generator 10 of fig. 1 may be disposed in a memory storage device or a memory control circuit unit to operate together with the memory storage device or the memory control circuit unit. However, in an exemplary embodiment, the spread spectrum clock generator 10 of fig. 1 may be disposed in other types of electronic devices.
Fig. 9 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to FIG. 9, a memory storage device 90 may be used with a host system 91. For example, the host system 91 may write data to the memory storage device 90 or read data from the memory storage device 90. Host system 91 may be any system that may cooperate with memory storage device 90 to store data, such as a smart phone, tablet computer, desktop computer, notebook computer, digital camera, video camera, communication device, audio player, or video player, among others.
The memory storage device 90 includes a connection interface unit 901, a memory control circuit unit 902, and a rewritable nonvolatile memory module 903. The connection interface unit 901 is used to connect the memory storage device 90 to the host system 91. For example, the connection interface unit 901 may be compatible with a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, a peripheral component interconnect Express (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, or other suitable standards. The connection interface unit 901 may be packaged in one chip with the memory control circuit unit 902, or the connection interface unit 901 may be disposed outside the chip including the memory control circuit unit 902.
The memory control circuit unit 902 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware. The memory control circuit unit 902 performs operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 903 according to the instruction of the host system 91.
The rewritable nonvolatile memory module 903 may be connected to the memory control circuit unit 902 and used to store data written by the host system 91. The rewritable non-volatile memory module 903 may include a single Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same or similar characteristics.
In an example embodiment, the rewritable non-volatile memory module 903 of fig. 9 may include a flash memory module. In an example embodiment, the memory control circuit unit 902 of fig. 9 may include a flash memory controller for controlling the flash memory modules. In an exemplary embodiment, the spread spectrum clock generator 10 of fig. 1 may be disposed in the connection interface unit 901, the memory control circuit unit 902 or the rewritable nonvolatile memory module 903 of fig. 9 to provide the spread spectrum clock signal SCLK required for the device operation.
Fig. 10 is a flowchart illustrating a spread spectrum clock generating method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a spread spectrum clock signal is generated according to a reference clock signal and a control signal. In step S1002, the control signal is adjusted such that the frequency of the spread spectrum clock signal changes based on a plurality of frequency change rates, wherein the initial frequency change rate of the spread spectrum clock signal is greater than the frequency change rate of the spread spectrum clock signal within a target time range.
However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.
In summary, the spread spectrum clock generator, the memory storage device and the method for generating a spread spectrum clock according to the exemplary embodiments of the invention can dynamically adjust the frequency change rate of the spread spectrum clock signal. Therefore, electromagnetic interference caused by spread spectrum clock signals can be further reduced, and the reliability of the system is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (30)

1. A spread spectrum clock generator, comprising:
the clock generation circuit is used for generating a spread spectrum clock signal according to the reference clock signal and the control signal; and
a frequency control circuit connected to the clock generation circuit,
the frequency control circuit is used for adjusting the control signal so that the frequency of the spread spectrum clock signal changes based on a plurality of frequency change rates, wherein the initial frequency change rate of the spread spectrum clock signal is larger than the frequency change rate of the spread spectrum clock signal in a target time range.
2. The spread spectrum clock generator of claim 1, wherein the operation of the frequency control circuit to adjust the control signal comprises:
Detecting whether the spread spectrum clock signal enters the target time range; and
and adjusting the control signal to reduce the frequency change rate of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
3. The spread spectrum clock generator of claim 1, wherein a rate of change of frequency of the spread spectrum clock signal outside the target time range is greater than the rate of change of frequency of the spread spectrum clock signal within the target time range.
4. The spread spectrum clock generator of claim 1, wherein at a turning point within the target time range, the frequency value of the spread spectrum clock signal changes from falling with increasing time to rising with increasing time or from rising with increasing time to falling with increasing time.
5. The spread spectrum clock generator of claim 4, wherein the target time range comprises a first sub-target time range and a second sub-target time range, the first sub-target time range is closer to the turning point than the second sub-target time range, and a rate of frequency change of the spread spectrum clock signal within the first sub-target time range is less than a rate of frequency change of the spread spectrum clock signal within the second sub-target time range.
6. The spread spectrum clock generator of claim 1, wherein the rate of frequency change of the spread spectrum clock signal over the target time range is 10-80% of the initial rate of frequency change.
7. The spread spectrum clock generator of claim 1, wherein the clock generation circuit comprises:
a phase frequency detection circuit connected to the frequency control circuit;
a charge pump circuit connected to the phase frequency detection circuit; and
a voltage-controlled oscillation circuit connected to the charge pump circuit and the frequency control circuit,
wherein the phase frequency detection circuit is used for detecting the phase difference or the frequency difference between the reference clock signal and the control signal, and
the charge pump circuit is used for controlling the voltage-controlled oscillation circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
8. The spread spectrum clock generator of claim 1, wherein the frequency control circuit comprises:
a frequency divider circuit connected to the clock generation circuit; and
a controller connected to the frequency-dividing circuit,
the controller is used for controlling the output of the frequency dividing circuit so as to adjust the control signal.
9. The spread spectrum clock generator of claim 1, wherein the frequency control circuit comprises:
a frequency divider circuit connected to the clock generation circuit;
a multiplexer circuit connected to the clock generation circuit and the frequency dividing circuit;
a phase interpolation circuit connected to the clock generation circuit and the multiplexer circuit; and
a controller connected to the phase interpolation circuit,
the controller is used for controlling the output of the phase interpolation circuit to adjust the control signal.
10. The spread spectrum clock generator of claim 1, wherein the frequency control circuit comprises:
a controller for controlling the frequency-dividing circuit or the phase interpolation circuit to adjust the control signal,
wherein the controller comprises:
a signal profile generator for providing a fundamental frequency control signal;
a modulator connected to the signal profile generator and configured to generate a modulation signal according to the fundamental frequency control signal; and
and an encoder connected to the modulator and used for generating an encoded signal according to the modulation signal, wherein the encoded signal is used for being provided to the frequency dividing circuit or the phase interpolation circuit so as to adjust the control signal.
11. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable nonvolatile memory module;
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module; and
a spread spectrum clock signal generator arranged in the connection interface unit,
wherein the spread spectrum clock signal generator is configured to:
generating a spread spectrum clock signal according to the reference clock signal and the control signal; and
the control signal is adjusted such that the frequency of the spread spectrum clock signal varies based on a plurality of frequency variation rates, wherein an initial frequency variation rate of the spread spectrum clock signal is greater than a frequency variation rate of the spread spectrum clock signal within a target time range.
12. The memory storage device of claim 11, wherein adjusting the control signal comprises:
detecting whether the spread spectrum clock signal enters the target time range; and
and adjusting the control signal to reduce the frequency change rate of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
13. The memory storage device of claim 11, wherein a rate of change of frequency of the spread spectrum clock signal outside the target time range is greater than the rate of change of frequency of the spread spectrum clock signal within the target time range.
14. The memory storage device of claim 11, wherein at a turning point within the target time range, a frequency value of the spread spectrum clock signal changes from falling with increasing time to rising with increasing time or from rising with increasing time to falling with increasing time.
15. The memory storage device of claim 14, wherein the target time range comprises a first sub-target time range and a second sub-target time range, the first sub-target time range is closer to the turning point than the second sub-target time range, and a rate of change of frequency of the spread-spectrum clock signal within the first sub-target time range is less than a rate of change of frequency of the spread-spectrum clock signal within the second sub-target time range.
16. The memory storage device of claim 11, wherein the rate of change of the frequency of the spread spectrum clock signal over the target time range is 10-80% of the initial rate of change of frequency.
17. The memory storage device of claim 11, wherein the spread spectrum clock signal generator comprises:
a phase frequency detection circuit;
a charge pump circuit connected to the phase frequency detection circuit; and
a voltage-controlled oscillation circuit connected to the charge pump circuit,
wherein the phase frequency detection circuit is used for detecting the phase difference or the frequency difference between the reference clock signal and the control signal, and
the charge pump circuit is used for controlling the voltage-controlled oscillation circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
18. The memory storage device of claim 11, wherein the spread spectrum clock signal generator comprises:
a frequency removing circuit; and
a controller connected to the frequency-dividing circuit,
the controller is used for controlling the output of the frequency dividing circuit so as to adjust the control signal.
19. The memory storage device of claim 11, wherein the spread spectrum clock signal generator comprises:
a frequency removing circuit;
a multiplexer circuit connected to the frequency divider circuit;
a phase interpolation circuit connected to the multiplexer circuit; and
a controller connected to the phase interpolation circuit,
The controller is used for controlling the output of the phase interpolation circuit to adjust the control signal.
20. The memory storage device of claim 11, wherein the spread spectrum clock signal generator comprises:
a controller for controlling the frequency-dividing circuit or the phase interpolation circuit to adjust the control signal,
wherein the controller comprises:
a signal profile generator for providing a fundamental frequency control signal;
a modulator connected to the signal profile generator and configured to generate a modulation signal according to the fundamental frequency control signal; and
and an encoder connected to the modulator and used for generating an encoded signal according to the modulation signal, wherein the encoded signal is used for being provided to the frequency dividing circuit or the phase interpolation circuit so as to adjust the control signal.
21. A spread spectrum clock generating method for a memory storage device, the spread spectrum clock generating method comprising:
generating a spread spectrum clock signal according to the reference clock signal and the control signal; and
the control signal is adjusted such that the frequency of the spread spectrum clock signal varies based on a plurality of frequency variation rates, wherein an initial frequency variation rate of the spread spectrum clock signal is greater than a frequency variation rate of the spread spectrum clock signal within a target time range.
22. The spread spectrum clock generating method as recited in claim 21, wherein the step of adjusting the control signal comprises:
detecting whether the spread spectrum clock signal enters the target time range; and
and adjusting the control signal to reduce the frequency change rate of the spread spectrum clock signal in response to the spread spectrum clock signal entering the target time range.
23. The spread spectrum clock generating method as recited in claim 21, wherein a rate of change of frequency of the spread spectrum clock signal outside the target time range is greater than the rate of change of frequency of the spread spectrum clock signal within the target time range.
24. The spread spectrum clock generating method as recited in claim 21, wherein at a turning point within the target time range, a frequency value of the spread spectrum clock signal changes from falling with an increase in time to rising with an increase in time or from rising with an increase in time to falling with an increase in time.
25. The spread spectrum clock generating method as recited in claim 24, wherein the target time range comprises a first sub-target time range and a second sub-target time range, the first sub-target time range is closer to the turning point than the second sub-target time range, and a rate of frequency change of the spread spectrum clock signal within the first sub-target time range is less than a rate of frequency change of the spread spectrum clock signal within the second sub-target time range.
26. The spread spectrum clock generating method as recited in claim 21, wherein the frequency change rate of the spread spectrum clock signal in the target time range is 10% to 80% of the initial frequency change rate.
27. The spread spectrum clock generating method as recited in claim 21, wherein generating the spread spectrum clock signal from the reference clock signal and the control signal comprises:
detecting a phase difference or a frequency difference between the reference clock signal and the control signal; and
and controlling a voltage-controlled oscillating circuit to generate the spread spectrum clock signal according to the phase difference or the frequency difference.
28. The spread spectrum clock generating method as recited in claim 21, wherein the step of adjusting the control signal comprises:
and controlling the output of the frequency dividing circuit to adjust the control signal.
29. The spread spectrum clock generating method as recited in claim 21, wherein the step of adjusting the control signal comprises:
the output of the phase interpolation circuit is controlled to adjust the control signal.
30. The spread spectrum clock generating method as recited in claim 21, wherein the step of adjusting the control signal comprises:
providing a fundamental frequency control signal;
Generating a modulation signal according to the basic frequency control signal; and
and generating a code signal according to the modulation signal, wherein the code signal is used for being provided to a frequency dividing circuit or a phase interpolation circuit so as to adjust the control signal.
CN202311351494.3A 2023-10-18 2023-10-18 Spread spectrum clock generator, memory storage device and spread spectrum clock generating method Pending CN117424594A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311351494.3A CN117424594A (en) 2023-10-18 2023-10-18 Spread spectrum clock generator, memory storage device and spread spectrum clock generating method

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